From e8ce0eb5e2254b85415e4b58e73f24a5d13846a1 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 26 Aug 2011 20:28:52 +0100 Subject: ARM: pm: preallocate a page table for suspend/resume Preallocate a page table and setup an identity mapping for the MMU enable code. This means we don't have to "borrow" a page table to do this, avoiding complexities with L2 cache coherency. Tested-by: Santosh Shilimkar Tested-by: Shawn Guo Tested-by: Lorenzo Pieralisi Signed-off-by: Russell King --- arch/arm/mm/proc-arm920.S | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm/mm/proc-arm920.S') diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 2e6849b41f66..035d57bf1b7a 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -400,10 +400,6 @@ ENTRY(cpu_arm920_do_resume) mcr p15, 0, r5, c3, c0, 0 @ Domain ID mcr p15, 0, r6, c2, c0, 0 @ TTB address mov r0, r7 @ control register - mov r2, r6, lsr #14 @ get TTB0 base - mov r2, r2, lsl #14 - ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ - PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE b cpu_resume_mmu ENDPROC(cpu_arm920_do_resume) #endif -- cgit v1.2.1 From de8e71ca4f2e17329f6718ae88d5c8336cb249ee Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 27 Aug 2011 22:39:09 +0100 Subject: ARM: pm: only use preallocated page table during resume Only use the preallocated page table during the resume, not while suspending. This avoids the overhead of having to switch unnecessarily to the resume page table in the suspend path. Tested-by: Santosh Shilimkar Tested-by: Shawn Guo Tested-by: Lorenzo Pieralisi Signed-off-by: Russell King --- arch/arm/mm/proc-arm920.S | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'arch/arm/mm/proc-arm920.S') diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 035d57bf1b7a..88fb3d9e0640 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -379,27 +379,26 @@ ENTRY(cpu_arm920_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm920_suspend_size -.equ cpu_arm920_suspend_size, 4 * 4 +.equ cpu_arm920_suspend_size, 4 * 3 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm920_do_suspend) - stmfd sp!, {r4 - r7, lr} + stmfd sp!, {r4 - r6, lr} mrc p15, 0, r4, c13, c0, 0 @ PID mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ TTB address - mrc p15, 0, r7, c1, c0, 0 @ Control register - stmia r0, {r4 - r7} - ldmfd sp!, {r4 - r7, pc} + mrc p15, 0, r6, c1, c0, 0 @ Control register + stmia r0, {r4 - r6} + ldmfd sp!, {r4 - r6, pc} ENDPROC(cpu_arm920_do_suspend) ENTRY(cpu_arm920_do_resume) mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches - ldmia r0, {r4 - r7} + ldmia r0, {r4 - r6} mcr p15, 0, r4, c13, c0, 0 @ PID mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r6, c2, c0, 0 @ TTB address - mov r0, r7 @ control register + mcr p15, 0, r1, c2, c0, 0 @ TTB address + mov r0, r6 @ control register b cpu_resume_mmu ENDPROC(cpu_arm920_do_resume) #endif -- cgit v1.2.1