From 0fcfdbcacf6fa234064126e5b18c720ca27bc6e7 Mon Sep 17 00:00:00 2001 From: Josh Cartwright Date: Tue, 23 Oct 2012 17:34:22 -0500 Subject: zynq: use pl310 device tree bindings The Zynq has a PL310 L2 cache controller. Convert in-tree uses to using the device tree. Signed-off-by: Josh Cartwright Cc: John Linn Acked-by: Arnd Bergmann Tested-by: Michal Simek --- arch/arm/mach-zynq/include/mach/zynq_soc.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm/mach-zynq/include') diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h index 3d1c6a6a8feb..218283a94247 100644 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h @@ -25,9 +25,6 @@ #define TTC0_PHYS 0xF8001000 #define TTC0_VIRT TTC0_PHYS -#define PL310_L2CC_PHYS 0xF8F02000 -#define PL310_L2CC_VIRT PL310_L2CC_PHYS - #define SCU_PERIPH_PHYS 0xF8F00000 #define SCU_PERIPH_VIRT SCU_PERIPH_PHYS @@ -35,7 +32,6 @@ #define TTC0_BASE IOMEM(TTC0_VIRT) #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) /* * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical -- cgit v1.2.1