From 1fb3726cf33a7402d797231fdba6ba49ed5eba75 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Wed, 2 Nov 2011 19:13:25 +0900 Subject: ARM: SAMSUNG: Move timer irq numbers to end of linux irq space The timer irqs statically mapped from linux irq numbers 11 to 15 are moved to the end of the statically mapped linux irq space. The GIC PPI and SPI interrupts are relocated to start from 16 and 32 of the linux irq space. This is a required to add device tree support for GIC and Interrupt combiner for EXYNOS4. A new macro 'IRQ_TIMER_BASE' specifies a platform specific base of the linux virq number for the timer interrupts. For exynos4, this base is set to end of the linux virq space. For the other S5P platforms, the existing base '11' is retained. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/entry-macro.S | 1 - arch/arm/mach-exynos/include/mach/irqs.h | 8 +++++--- 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S index f5e9fd8e37b4..d7dfcd7eb921 100644 --- a/arch/arm/mach-exynos/include/mach/entry-macro.S +++ b/arch/arm/mach-exynos/include/mach/entry-macro.S @@ -72,7 +72,6 @@ cmpcc \irqnr, \irqnr cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr - addne \irqnr, \irqnr, #32 .endm diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index dfd4b7eecb90..713dd5251c64 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -17,13 +17,13 @@ /* PPI: Private Peripheral Interrupt */ -#define IRQ_PPI(x) S5P_IRQ(x+16) +#define IRQ_PPI(x) (x+16) #define IRQ_MCT_LOCALTIMER IRQ_PPI(12) /* SPI: Shared Peripheral Interrupt */ -#define IRQ_SPI(x) S5P_IRQ(x+32) +#define IRQ_SPI(x) (x+32) #define IRQ_EINT0 IRQ_SPI(16) #define IRQ_EINT1 IRQ_SPI(17) @@ -163,7 +163,9 @@ #define IRQ_GPIO2_NR_GROUPS 9 #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) +#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) + /* Set the default NR_IRQS */ -#define NR_IRQS (IRQ_GPIO_END + 64) +#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) #endif /* __ASM_ARCH_IRQS_H */ -- cgit v1.2.1 From f983575aa90ceeb2cc7923223882dcf1debf5aa2 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Wed, 2 Nov 2011 19:14:37 +0900 Subject: ARM: EXYNOS: Enable conversion of GIC dt irq specifier to linux virq Enable conversion of device tree interrupt specifier to linux virq domain for GIC controller. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/cpu.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c index 90ec247f3b37..0eb7b6a6903d 100644 --- a/arch/arm/mach-exynos/cpu.c +++ b/arch/arm/mach-exynos/cpu.c @@ -10,6 +10,8 @@ #include #include +#include +#include #include #include @@ -218,13 +220,26 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d) (gic_bank_offset * smp_processor_id()); } +#ifdef CONFIG_OF +static const struct of_device_id exynos4_dt_irq_match[] = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + {}, +}; +#endif + void __init exynos4_init_irq(void) { int irq; gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); + if (!of_have_populated_dt()) + gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); +#ifdef CONFIG_OF + else + of_irq_init(exynos4_dt_irq_match); +#endif + gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base; -- cgit v1.2.1 From afba7f91e64025748a2cfec181e5a910fd0dee0e Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 24 Oct 2011 11:47:51 +0200 Subject: ARM: SAMSUNG: remove struct 's3c24xx_uart_clksrc' and all uses of it With clkdev based clock lookup added to samsung serial driver, the use of 'struct s3c24xx_uart_clksrc' to supply clock names in platform data is removed from all the Samsung platform code. Cc: Ben Dooks Cc: Ramax Lo Cc: Vasily Khoruzhick Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/init.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c index a8a83e3881a4..e836c9cdc200 100644 --- a/arch/arm/mach-exynos/init.c +++ b/arch/arm/mach-exynos/init.c @@ -14,15 +14,6 @@ #include #include -static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = { - [0] = { - .name = "uclk1", - .divisor = 1, - .min_baud = 0, - .max_baud = 0, - }, -}; - /* uart registration process */ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) { @@ -30,11 +21,7 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) u32 ucnt; for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { - if (!tcfg->clocks) { - tcfg->has_fracval = 1; - tcfg->clocks = exynos4_serial_clocks; - tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks); - } + tcfg->has_fracval = 1; tcfg->flags |= NO_NEED_CHECK_CLKSRC; } -- cgit v1.2.1 From c3310fbbeb9db6967900ed22eb3d0bd0bb0e892c Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 24 Oct 2011 11:47:57 +0200 Subject: serial: samsung: remove all uses of get_clksrc and set_clksrc With clkdev based clock lookup support, the clock set and get operation using clock names communicated between the samsung uart driver and the SoC specific extension can be removed. In addition to that, for each platform specific extension, add the default clock selection, number of clock options for uart baud generator, clock selection bit mask and shift values which is required by the clkdev support in samsung uart driver. The default clock selection value 'def_clk_sel' specifies the default clock to be used as the source clock for baud rate generator in case the platform code does not specify the same. Cc: Ben Dooks Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/init.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c index e836c9cdc200..3c9590b1703f 100644 --- a/arch/arm/mach-exynos/init.c +++ b/arch/arm/mach-exynos/init.c @@ -20,10 +20,8 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) struct s3c2410_uartcfg *tcfg = cfg; u32 ucnt; - for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { + for (ucnt = 0; ucnt < no; ucnt++, tcfg++) tcfg->has_fracval = 1; - tcfg->flags |= NO_NEED_CHECK_CLKSRC; - } s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); } -- cgit v1.2.1 From 0cfb26e1fb9d7afe9c79a40a257808eafb2aff34 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 24 Oct 2011 12:08:42 +0200 Subject: ARM: SAMSUNG: register uart clocks to clock lookup list Samsung uart driver lookups the clock using the connection id 'clk_uart_baud'. The uart clocks for all Samsung platforms are reorganized to register them with the lookup name as required by the uart driver. Cc: Ben Dooks Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/clock.c | 106 +++++++++++++++++++++++++++---------------- arch/arm/mach-exynos/init.c | 2 +- 2 files changed, 67 insertions(+), 41 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index 2894f0adef5c..fe1851914dac 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -1009,46 +1009,6 @@ static struct clksrc_clk clk_dout_mmc4 = { static struct clksrc_clk clksrcs[] = { { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.0", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.1", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 4), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.2", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.3", - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 << 12), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, - }, { .clk = { .name = "sclk_pwm", .enable = exynos4_clksrc_mask_peril0_ctrl, @@ -1237,6 +1197,54 @@ static struct clksrc_clk clksrcs[] = { } }; +static struct clksrc_clk clk_sclk_uart0 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.0", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart1 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.1", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart2 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.2", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk clk_sclk_uart3 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.3", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, +}; + /* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll, @@ -1271,6 +1279,20 @@ static struct clksrc_clk *sysclks[] = { &clk_mout_mfc1, }; +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uart0, + &clk_sclk_uart1, + &clk_sclk_uart2, + &clk_sclk_uart3, +}; + +static struct clk_lookup exynos4_clk_lookup[] = { + CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk), + CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), + CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), + CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), +}; + static int xtal_rate; static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) @@ -1478,11 +1500,15 @@ void __init exynos4_register_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) s3c_register_clksrc(sclk_tv[ptr], 1); + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) + s3c_register_clksrc(clksrc_cdev[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); register_syscore_ops(&exynos4_clock_syscore_ops); s3c24xx_register_clock(&dummy_apb_pclk); diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c index 3c9590b1703f..5b35978029be 100644 --- a/arch/arm/mach-exynos/init.c +++ b/arch/arm/mach-exynos/init.c @@ -23,5 +23,5 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) for (ucnt = 0; ucnt < no; ucnt++, tcfg++) tcfg->has_fracval = 1; - s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); + s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no); } -- cgit v1.2.1 From e1cd8454dac99473c2349efce1346264c494f28d Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 24 Oct 2011 11:43:22 +0200 Subject: ARM: EXYNOS: Modify platform data for pl330 driver With the 'struct dma_pl330_peri' removed, the platfrom data for dma driver can be simplified to a simple list of peripheral request ids. Cc: Jassi Brar Acked-by: Boojin Kim Signed-off-by: Thomas Abraham Acked-by: Grant Likely Acked-by: Vinod Koul Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/dma.c | 225 +++++++++++++-------------------------------- 1 file changed, 64 insertions(+), 161 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index 9667c61e64fb..141093d60d0d 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c @@ -35,95 +35,42 @@ static u64 dma_dmamask = DMA_BIT_MASK(32); -struct dma_pl330_peri pdma0_peri[28] = { - { - .peri_id = (u8)DMACH_PCM0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MSM_REQ0, - }, { - .peri_id = (u8)DMACH_MSM_REQ2, - }, { - .peri_id = (u8)DMACH_SPI0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SPI2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0S_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART4_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART4_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS2_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS2_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS4_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS4_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_AC97_MICIN, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_AC97_PCMIN, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_AC97_PCMOUT, - .rqtype = MEMTODEV, - }, +u8 pdma0_peri[] = { + DMACH_PCM0_RX, + DMACH_PCM0_TX, + DMACH_PCM2_RX, + DMACH_PCM2_TX, + DMACH_MSM_REQ0, + DMACH_MSM_REQ2, + DMACH_SPI0_RX, + DMACH_SPI0_TX, + DMACH_SPI2_RX, + DMACH_SPI2_TX, + DMACH_I2S0S_TX, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S2_RX, + DMACH_I2S2_TX, + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART2_RX, + DMACH_UART2_TX, + DMACH_UART4_RX, + DMACH_UART4_TX, + DMACH_SLIMBUS0_RX, + DMACH_SLIMBUS0_TX, + DMACH_SLIMBUS2_RX, + DMACH_SLIMBUS2_TX, + DMACH_SLIMBUS4_RX, + DMACH_SLIMBUS4_TX, + DMACH_AC97_MICIN, + DMACH_AC97_PCMIN, + DMACH_AC97_PCMOUT, }; struct dma_pl330_platdata exynos4_pdma0_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma0_peri), - .peri = pdma0_peri, + .peri_id = pdma0_peri, }; struct amba_device exynos4_device_pdma0 = { @@ -142,86 +89,37 @@ struct amba_device exynos4_device_pdma0 = { .periphid = 0x00041330, }; -struct dma_pl330_peri pdma1_peri[25] = { - { - .peri_id = (u8)DMACH_PCM0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_PCM1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_PCM1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_MSM_REQ1, - }, { - .peri_id = (u8)DMACH_MSM_REQ3, - }, { - .peri_id = (u8)DMACH_SPI1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SPI1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0S_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_I2S1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_I2S1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART0_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART0_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_UART3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_UART3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS1_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS1_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS3_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS3_TX, - .rqtype = MEMTODEV, - }, { - .peri_id = (u8)DMACH_SLIMBUS5_RX, - .rqtype = DEVTOMEM, - }, { - .peri_id = (u8)DMACH_SLIMBUS5_TX, - .rqtype = MEMTODEV, - }, +u8 pdma1_peri[] = { + DMACH_PCM0_RX, + DMACH_PCM0_TX, + DMACH_PCM1_RX, + DMACH_PCM1_TX, + DMACH_MSM_REQ1, + DMACH_MSM_REQ3, + DMACH_SPI1_RX, + DMACH_SPI1_TX, + DMACH_I2S0S_TX, + DMACH_I2S0_RX, + DMACH_I2S0_TX, + DMACH_I2S1_RX, + DMACH_I2S1_TX, + DMACH_UART0_RX, + DMACH_UART0_TX, + DMACH_UART1_RX, + DMACH_UART1_TX, + DMACH_UART3_RX, + DMACH_UART3_TX, + DMACH_SLIMBUS1_RX, + DMACH_SLIMBUS1_TX, + DMACH_SLIMBUS3_RX, + DMACH_SLIMBUS3_TX, + DMACH_SLIMBUS5_RX, + DMACH_SLIMBUS5_TX, }; struct dma_pl330_platdata exynos4_pdma1_pdata = { .nr_valid_peri = ARRAY_SIZE(pdma1_peri), - .peri = pdma1_peri, + .peri_id = pdma1_peri, }; struct amba_device exynos4_device_pdma1 = { @@ -242,7 +140,12 @@ struct amba_device exynos4_device_pdma1 = { static int __init exynos4_dma_init(void) { + dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); amba_device_register(&exynos4_device_pdma0, &iomem_resource); + + dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask); + dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); amba_device_register(&exynos4_device_pdma1, &iomem_resource); return 0; -- cgit v1.2.1 From fca3de6ab9bfc6f3b5beebd8f9792357c4e4d441 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 24 Oct 2011 13:57:43 +0200 Subject: ARM: EXYNOS: Limit usage of pl330 device instance to non-dt build The pl330 device instances and associated platform data is required only for non-device-tree builds. With device tree enabled, the data about the platform is obtained from the device tree. For images that include both dt and non-dt platforms, an addditional check is added to ensure that static amba device registrations is applicable to only non-dt platforms. Cc: Kukjin Kim Cc: Kyungmin Park Signed-off-by: Thomas Abraham Acked-by: Grant Likely Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Kconfig | 10 ++++++++++ arch/arm/mach-exynos/Makefile | 3 ++- arch/arm/mach-exynos/dma.c | 4 ++++ 3 files changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 724ec0f3560d..68e4ab0c9375 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -57,6 +57,11 @@ config EXYNOS4_MCT help Use MCT (Multi Core Timer) as kernel timers +config EXYNOS4_DEV_DMA + bool + help + Compile in amba device definitions for DMA controller + config EXYNOS4_DEV_AHCI bool help @@ -177,6 +182,7 @@ config MACH_SMDKV310 select SAMSUNG_DEV_BACKLIGHT select EXYNOS4_DEV_AHCI select SAMSUNG_DEV_KEYPAD + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_PD select SAMSUNG_DEV_PWM select EXYNOS4_DEV_SYSMMU @@ -197,6 +203,7 @@ config MACH_ARMLEX4210 select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 select EXYNOS4_DEV_AHCI + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_SYSMMU select EXYNOS4_SETUP_SDHCI help @@ -222,6 +229,7 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_MFC select S5P_DEV_ONENAND select S5P_DEV_TV + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_PD select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 @@ -255,6 +263,7 @@ config MACH_NURI select S5P_DEV_MFC select S5P_DEV_USB_EHCI select S5P_SETUP_MIPIPHY + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_PD select EXYNOS4_SETUP_FIMC select EXYNOS4_SETUP_FIMD0 @@ -287,6 +296,7 @@ config MACH_ORIGEN select S5P_DEV_USB_EHCI select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM + select EXYNOS4_DEV_DMA select EXYNOS4_DEV_PD select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_SDHCI diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 59069a35e40b..cb6fb0e8bcaf 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -13,7 +13,7 @@ obj- := # Core support for EXYNOS4 system obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o -obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o dma.o pmu.o +obj-$(CONFIG_ARCH_EXYNOS4) += irq-eint.o pmu.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_PM) += pm.o @@ -44,6 +44,7 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o +obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index 141093d60d0d..b10fcd270f07 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -140,6 +141,9 @@ struct amba_device exynos4_device_pdma1 = { static int __init exynos4_dma_init(void) { + if (of_have_populated_dt()) + return 0; + dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); amba_device_register(&exynos4_device_pdma0, &iomem_resource); -- cgit v1.2.1 From 66fdb29d370436ca43a0637f831a2b4d92b243ca Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Mon, 24 Oct 2011 14:01:03 +0200 Subject: ARM: EXYNOS: Add a alias for pdma clocks PDMA controllers when instantiated from device tree are registered using amba_device_register(). The registration process enables clock to the controllers to read the peripheral id of the PDMA amba device. In case of Exynos4, the clocks to the PDMA controllers are named as 'dma' but amba_device_register() looks up the clock using the name 'apb_pclk'. Hence, alias clocks with name 'apb_pclk' clock are created for clocks with name 'dma'. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/clock.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index fe1851914dac..7dee8694486a 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -552,16 +552,6 @@ static struct clk init_clocks_off[] = { .devname = "s5p-sdo", .enable = exynos4_clk_dac_ctrl, .ctrlbit = (1 << 0), - }, { - .name = "dma", - .devname = "dma-pl330.0", - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "dma", - .devname = "dma-pl330.1", - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 1), }, { .name = "adc", .enable = exynos4_clk_ip_peril_ctrl, @@ -778,6 +768,20 @@ static struct clk init_clocks[] = { } }; +static struct clk clk_pdma0 = { + .name = "dma", + .devname = "dma-pl330.0", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 0), +}; + +static struct clk clk_pdma1 = { + .name = "dma", + .devname = "dma-pl330.1", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 1), +}; + struct clk *clkset_group_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_xusbxti, @@ -1279,6 +1283,11 @@ static struct clksrc_clk *sysclks[] = { &clk_mout_mfc1, }; +static struct clk *clk_cdev[] = { + &clk_pdma0, + &clk_pdma1, +}; + static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uart0, &clk_sclk_uart1, @@ -1291,6 +1300,8 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), + CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), + CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), }; static int xtal_rate; @@ -1506,6 +1517,10 @@ void __init exynos4_register_clocks(void) s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) + s3c_disable_clocks(clk_cdev[ptr], 1); + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); -- cgit v1.2.1 From 6b5ab4f442e32f248b6fad29aafd1d5153f4dbd3 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sun, 6 Nov 2011 21:54:27 +0530 Subject: ARM: EXYNOS: Add Exynos4 device tree enabled board file Add a new EXYNOS4 compatible device tree enabled board file. Boards based on the EXYNOS4 family of SoC's can use this as the machine/board file. When using this machine fike, a corresponding device tree blob which describes the board's properties should be supplied at boot time to the kernel. Signed-off-by: Thomas Abraham Acked-by: Grant Likely Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Kconfig | 14 ++++++ arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/mach-exynos4-dt.c | 85 ++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 arch/arm/mach-exynos/mach-exynos4-dt.c (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 68e4ab0c9375..0afcc3b0f870 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -337,6 +337,20 @@ config MACH_SMDK4412 Machine support for Samsung SMDK4412 endif +comment "Flattened Device Tree based board for Exynos4 based SoC" + +config MACH_EXYNOS4_DT + bool "Samsung Exynos4 Machine using device tree" + select CPU_EXYNOS4210 + select USE_OF + select ARM_AMBA + select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD + help + Machine support for Samsung Exynos4 machine with device tree enabled. + Select this if a fdt blob is available for the Exynos4 SoC based board. + Note: This is under development and not all peripherals can be supported + with this machine file. + if ARCH_EXYNOS4 comment "Configuration for HSMMC 8-bit bus width" diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index cb6fb0e8bcaf..8d85ae635ac2 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -37,6 +37,8 @@ obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o +obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o + # device support obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c new file mode 100644 index 000000000000..85fa02767d67 --- /dev/null +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -0,0 +1,85 @@ +/* + * Samsung's Exynos4210 flattened device tree enabled machine + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include + +#include +#include + +#include +#include +#include + +/* + * The following lookup table is used to override device names when devices + * are registered from device tree. This is temporarily added to enable + * device tree support addition for the Exynos4 architecture. + * + * For drivers that require platform data to be provided from the machine + * file, a platform data pointer can also be supplied along with the + * devices names. Usually, the platform data elements that cannot be parsed + * from the device tree by the drivers (example: function pointers) are + * supplied. But it should be noted that this is a temporary mechanism and + * at some point, the drivers should be capable of parsing all the platform + * data from the device tree. + */ +static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0, + "exynos4210-uart.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1, + "exynos4210-uart.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2, + "exynos4210-uart.2", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3, + "exynos4210-uart.3", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0), + "exynos4-sdhci.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1), + "exynos4-sdhci.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2), + "exynos4-sdhci.2", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3), + "exynos4-sdhci.3", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), + "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), + {}, +}; + +static void __init exynos4210_dt_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); +} + +static void __init exynos4210_dt_machine_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + exynos4210_auxdata_lookup, NULL); +} + +static char const *exynos4210_dt_compat[] __initdata = { + "samsung,exynos4210", + NULL +}; + +DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") + /* Maintainer: Thomas Abraham */ + .init_irq = exynos4_init_irq, + .map_io = exynos4210_dt_map_io, + .init_machine = exynos4210_dt_machine_init, + .timer = &exynos4_timer, + .dt_compat = exynos4210_dt_compat, +MACHINE_END -- cgit v1.2.1