From aff18a67078e61088ea05efa6d077ffb838786e9 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 25 Jul 2012 17:56:48 +0200 Subject: ARM: pxa: add .dtsi files This adds .dtsi files to describe the PXA SoCs. pxa3xx simply augments pxa2xx. Not all devices are listed yet, and it will need some time to get all the drivers ported. For now, pxa27x.dtsi only enables the PXA's interrupt priority feature. Signed-off-by: Daniel Mack Acked-by: Arnd Bergmann Signed-off-by: Haojian Zhuang --- arch/arm/boot/dts/pxa27x.dtsi | 14 +++++ arch/arm/boot/dts/pxa2xx.dtsi | 132 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/pxa3xx.dtsi | 32 ++++++++++ 3 files changed, 178 insertions(+) create mode 100644 arch/arm/boot/dts/pxa27x.dtsi create mode 100644 arch/arm/boot/dts/pxa2xx.dtsi create mode 100644 arch/arm/boot/dts/pxa3xx.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi new file mode 100644 index 000000000000..d7c5d721a5c7 --- /dev/null +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -0,0 +1,14 @@ +/* The pxa3xx skeleton simply augments the 2xx version */ +/include/ "pxa2xx.dtsi" + +/ { + model = "Marvell PXA27x familiy SoC"; + compatible = "marvell,pxa27x"; + + pxabus { + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <34>; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi new file mode 100644 index 000000000000..f18aad35e8b3 --- /dev/null +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -0,0 +1,132 @@ +/* + * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC + * + * Copyright (C) 2011 Marek Vasut + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Marvell PXA2xx family SoC"; + compatible = "marvell,pxa2xx"; + interrupt-parent = <&pxairq>; + + aliases { + serial0 = &ffuart; + serial1 = &btuart; + serial2 = &stuart; + serial3 = &hwuart; + i2c0 = &pwri2c; + i2c1 = &pxai2c1; + }; + + cpus { + cpu@0 { + compatible = "arm,xscale"; + }; + }; + + pxabus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pxairq: interrupt-controller@40d00000 { + #interrupt-cells = <1>; + compatible = "marvell,pxa-intc"; + interrupt-controller; + interrupt-parent; + marvell,intc-nr-irqs = <32>; + reg = <0x40d00000 0xd0>; + }; + + gpio: gpio@40e00000 { + compatible = "mrvl,pxa-gpio"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x40e00000 0x10000>; + gpio-controller; + #gpio-cells = <0x2>; + interrupts = <10>; + interrupt-names = "gpio_mux"; + interrupt-controller; + #interrupt-cells = <0x2>; + ranges; + + gcb0: gpio@40e00000 { + reg = <0x40e00000 0x4>; + }; + + gcb1: gpio@40e00004 { + reg = <0x40e00004 0x4>; + }; + + gcb2: gpio@40e00008 { + reg = <0x40e00008 0x4>; + }; + gcb3: gpio@40e0000c { + reg = <0x40e0000c 0x4>; + }; + }; + + ffuart: uart@40100000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40100000 0x30>; + interrupts = <22>; + status = "disabled"; + }; + + btuart: uart@40200000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40200000 0x30>; + interrupts = <21>; + status = "disabled"; + }; + + stuart: uart@40700000 { + compatible = "mrvl,pxa-uart"; + reg = <0x40700000 0x30>; + interrupts = <20>; + status = "disabled"; + }; + + hwuart: uart@41100000 { + compatible = "mrvl,pxa-uart"; + reg = <0x41100000 0x30>; + interrupts = <7>; + status = "disabled"; + }; + + pxai2c1: i2c@40301680 { + compatible = "mrvl,pxa-i2c"; + reg = <0x40301680 0x30>; + interrupts = <18>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb0: ohci@4c000000 { + compatible = "mrvl,pxa-ohci"; + reg = <0x4c000000 0x10000>; + interrupts = <3>; + status = "disabled"; + }; + + mmc0: mmc@41100000 { + compatible = "mrvl,pxa-mmc"; + reg = <0x41100000 0x1000>; + interrupts = <23>; + status = "disabled"; + }; + + rtc@40900000 { + compatible = "marvell,pxa-rtc"; + reg = <0x40900000 0x3c>; + interrupts = <30 31>; + }; + }; +}; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi new file mode 100644 index 000000000000..f9d92da86783 --- /dev/null +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -0,0 +1,32 @@ +/* The pxa3xx skeleton simply augments the 2xx version */ +/include/ "pxa2xx.dtsi" + +/ { + model = "Marvell PXA3xx familiy SoC"; + compatible = "marvell,pxa3xx"; + + pxabus { + pwri2c: i2c@40f500c0 { + compatible = "mrvl,pwri2c"; + reg = <0x40f500c0 0x30>; + interrupts = <6>; + #address-cells = <0x1>; + #size-cells = <0>; + status = "disabled"; + }; + + nand0: nand@43100000 { + compatible = "marvell,pxa3xx-nand"; + reg = <0x43100000 90>; + interrupts = <45>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <56>; + }; + }; +}; -- cgit v1.2.1 From a03d8b1e4606be10c0fedf1ccabe22dc3a5060f9 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 4 Aug 2012 23:57:38 +0800 Subject: ARM: mmp: enable tauros2 cache in pxa910 Signed-off-by: Haojian Zhuang --- arch/arm/boot/dts/pxa910.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index aebf32de73b4..a3be44d86bcd 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -25,6 +25,11 @@ interrupt-parent = <&intc>; ranges; + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; + axi@d4200000 { /* AXI */ compatible = "mrvl,axi-bus", "simple-bus"; #address-cells = <1>; -- cgit v1.2.1 From 51931b37fcb17a2f48f726fd21b88e3af770ddc2 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sun, 5 Aug 2012 10:28:30 +0800 Subject: ARM: mmp: enable tauros2 cache in mmp2 dt Signed-off-by: Haojian Zhuang --- arch/arm/boot/dts/mmp2.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 80f74e256408..0514fb41627e 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -26,6 +26,11 @@ interrupt-parent = <&intc>; ranges; + L2: l2-cache { + compatible = "marvell,tauros2-cache"; + marvell,tauros2-cache-features = <0x3>; + }; + axi@d4200000 { /* AXI */ compatible = "mrvl,axi-bus", "simple-bus"; #address-cells = <1>; -- cgit v1.2.1 From 98916a2fbc4f9b7bf85d9c4d2f9aa301c1f71259 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 Jul 2012 16:33:44 -0300 Subject: ARM: imx23-olinuxino.dts: Add AUART0 support Add AUART0 support. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-olinuxino.dts | 6 ++++++ arch/arm/boot/dts/imx23.dtsi | 11 +++++++++++ 2 files changed, 17 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 20912b1d8893..a28687303e49 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -39,6 +39,12 @@ pinctrl-0 = <&duart_pins_a>; status = "okay"; }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index e6138310e5ce..9700872794d0 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -140,6 +140,17 @@ fsl,pull-up = <0>; }; + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */ + 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + gpmi_pins_a: gpmi-nand@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v1.2.1 From aef35104a9e5b8555cdaeebd4563df9921f6d605 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Aug 2012 10:42:52 +0800 Subject: ARM: dts: imx28: Add compatible and interrupt for LRADC Signed-off-by: Marek Vasut Cc: Jonathan Cameron Cc: Juergen Beisert Cc: Lars-Peter Clausen Cc: Wolfgang Denk Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 3fa6d190fab4..e2240da7ba95 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -638,7 +638,10 @@ }; lradc@80050000 { + compatible = "fsl,imx28-lradc"; reg = <0x80050000 0x2000>; + interrupts = <10 14 15 16 17 18 19 + 20 21 22 23 24 25>; status = "disabled"; }; -- cgit v1.2.1 From 2c7c2c1d01a2559d452c0f0aa5e6f6ca2643e6b1 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 13 Jul 2012 14:15:34 +0800 Subject: ARM: mxs: tx28: reset fec phy for device tree boot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For non-DT boot, function tx28_add_fec0 configures all ENET0 pins into gpio mode for resetting fec phy, and then reconfigures those pins into ENET function after that. For DT boot, all the pin configuration is done by pinctrl subsystem. Ideally, when gpio_request gets called, GPIO subsystem should call pinctrl to configure pins into gpio mode automatically, and have pins freed up from pinctrl subsystem when gpio_free is called. But right now, this cooperation between gpio and pinctrl hasn't been available. As the result, we have to explicitly call pinctrl_get_select and pinctrl_put for device tree boot. Signed-off-by: Shawn Guo Acked-by: Lothar Waßmann --- arch/arm/boot/dts/imx28-tx28.dts | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 62bf767409a6..a56ae05f9fa9 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -34,6 +34,24 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + mac0_pins_gpio: mac0-gpio-mode@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */ + 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */ + 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */ + 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */ + 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */ + 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */ + 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */ + 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */ + 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; }; @@ -72,8 +90,9 @@ ahb@80080000 { mac0: ethernet@800f0000 { phy-mode = "rmii"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio_mode"; pinctrl-0 = <&mac0_pins_a>; + pinctrl-1 = <&mac0_pins_gpio>; status = "okay"; }; }; -- cgit v1.2.1 From 59bafcf69cdc74f848f212086a8b9c51866da384 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 22 Aug 2012 14:10:03 +0530 Subject: arm/dts: omap4: Add ocp2scp data Add ocp2scp data node in omap4 device tree file. Acked-by: Felipe Balbi Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/omap4.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 04cbbcb6ff91..8a780b2a5083 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -295,5 +295,13 @@ interrupt-parent = <&gic>; ti,hwmods = "dmic"; }; + + ocp2scp { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "ocp2scp_usb_phy"; + }; }; }; -- cgit v1.2.1 From e0e35b48a81d7bf4d9894b6e506ad8fbf8abf811 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 22 Aug 2012 13:25:31 -0300 Subject: ARM: mxs: Rename 'hog-gpios' hog_pins is used to setup the pin functions, and it is not neccesarily used only for GPIO pins, so use only 'hog' to describe a more generic term. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-evk.dts | 2 +- arch/arm/boot/dts/imx23-stmp378x_devb.dts | 2 +- arch/arm/boot/dts/imx28-apx4devkit.dts | 2 +- arch/arm/boot/dts/imx28-evk.dts | 2 +- arch/arm/boot/dts/imx28-m28evk.dts | 2 +- arch/arm/boot/dts/imx28-tx28.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index e3486f486b40..1093dd55c87a 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -42,7 +42,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index 757a327ff3e8..85c3864b6a56 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -36,7 +36,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index b383417a558f..5171667a7763 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -37,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 773c0e84d1fb..ab78ee53fdc7 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -50,7 +50,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 183a3fd2d859..ac3eff96a70c 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -69,7 +69,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index a56ae05f9fa9..37be532f0055 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -25,7 +25,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; - hog_pins_a: hog-gpios@0 { + hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ -- cgit v1.2.1 From 74b42123f2605ab83bb264fac8ea57cd33e2580c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 22 Aug 2012 13:25:32 -0300 Subject: ARM: mxs: Let mmc0 pin detect be generic Instead of assigning SSP1_DETECT inside mmc0_4bit_pins_a, let the board dts handle this setup. Not every board will use MX23_PAD_SSP1_DETECT as SSP1 functionality. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-evk.dts | 1 + arch/arm/boot/dts/imx23.dtsi | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 1093dd55c87a..035c13f9d3c0 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -48,6 +48,7 @@ 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 9700872794d0..b00f3cfb3bf8 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -194,7 +194,6 @@ 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ - 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ >; fsl,drive-strength = <1>; -- cgit v1.2.1 From ba5db4990c2d1774fe854de3e3f6398fe9074fde Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 22 Aug 2012 13:25:33 -0300 Subject: ARM: olinuxino: Add gpio-led support Olinuxino has a LED connected to MX23_PAD_SSP1_DETECT__GPIO_2_1 pin. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-olinuxino.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index a28687303e49..711dcf5742b6 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -31,6 +31,21 @@ bus-width = <4>; status = "okay"; }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; }; apbx@80040000 { @@ -47,4 +62,14 @@ }; }; }; + + leds { + compatible = "gpio-leds"; + + user { + label = "green"; + gpios = <&gpio2 1 0>; + linux,default-trigger = "default-on"; + }; + }; }; -- cgit v1.2.1 From a9d1f92407a2114aff580a2e28803d64b4c437e0 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 18 Jul 2012 11:42:43 +0200 Subject: ARM i.MX53: dts: add flexcan to imx53 Cc: Sascha Hauer Signed-off-by: Steffen Trumtrar Signed-off-by: Marc Kleine-Budde Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index cd37165edce5..0132078aca03 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -203,6 +203,20 @@ status = "disabled"; }; + can1: can@53fc8000 { + compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + status = "disabled"; + }; + + can2: can@53fcc000 { + compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fcc000 0x4000>; + interrupts = <83>; + status = "disabled"; + }; + gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fdc000 0x4000>; -- cgit v1.2.1 From 03b276505435927b5c4f7d246557a991fbedad92 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 30 Jul 2012 11:03:16 -0300 Subject: ARM: dts: imx: Always enable the watchdog Instead of enabling the watchdog in each individual dts file, select in the SoC dtsi file instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore.dts | 4 ---- arch/arm/boot/dts/imx27.dtsi | 1 - arch/arm/boot/dts/imx51-babbage.dts | 4 ---- arch/arm/boot/dts/imx51.dtsi | 1 - arch/arm/boot/dts/imx53-ard.dts | 4 ---- arch/arm/boot/dts/imx53-evk.dts | 4 ---- arch/arm/boot/dts/imx53-qsb.dts | 4 ---- arch/arm/boot/dts/imx53-smd.dts | 4 ---- arch/arm/boot/dts/imx53.dtsi | 1 - arch/arm/boot/dts/imx6q.dtsi | 1 - 10 files changed, 28 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts index 2b0ff60247a4..777caa33cd85 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts @@ -23,10 +23,6 @@ soc { aipi@10000000 { /* aipi */ - wdog@10002000 { - status = "okay"; - }; - serial@1000a000 { fsl,uart-has-rtscts; status = "okay"; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 5303ab680a34..3e54f1498841 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -62,7 +62,6 @@ compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x4000>; interrupts = <27>; - status = "disabled"; }; uart1: serial@1000a000 { diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index cd86177a3ea2..ce08d19f8414 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -169,10 +169,6 @@ }; }; - wdog@73f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@73fa8000 { compatible = "fsl,imx51-iomuxc-babbage"; reg = <0x73fa8000 0x4000>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index aba28dc87fc8..140fd28de6ab 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -174,7 +174,6 @@ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; - status = "disabled"; }; wdog@73f9c000 { /* WDOG2 */ diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index da895e93a999..d356f10dd35a 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -31,10 +31,6 @@ }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { compatible = "fsl,imx53-iomuxc-ard"; reg = <0x53fa8000 0x4000>; diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 9c798034675e..5d36dde14038 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts @@ -62,10 +62,6 @@ }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { compatible = "fsl,imx53-iomuxc-evk"; reg = <0x53fa8000 0x4000>; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 2d803a9a6949..3bfa6f147296 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -41,10 +41,6 @@ }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { compatible = "fsl,imx53-iomuxc-qsb"; reg = <0x53fa8000 0x4000>; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 08091029168e..45848afab1bd 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -77,10 +77,6 @@ }; }; - wdog@53f98000 { /* WDOG1 */ - status = "okay"; - }; - iomuxc@53fa8000 { compatible = "fsl,imx53-iomuxc-smd"; reg = <0x53fa8000 0x4000>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 0132078aca03..25b216e610f5 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -179,7 +179,6 @@ compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; - status = "disabled"; }; wdog@53f9c000 { /* WDOG2 */ diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index fd57079f71a9..a8cd96eed298 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -362,7 +362,6 @@ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 0x04>; - status = "disabled"; }; wdog@020c0000 { /* WDOG2 */ -- cgit v1.2.1 From 7e4f03657d3751adda76f1fecf12283bf8082af8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 8 Aug 2012 11:28:07 -0300 Subject: ARM: dts: imx: Move SDMA firmware to SoC dtsi file Instead of adding sdma-ram-script-name into each board dts file, move it to the SoC dtsi file instead. Signed-off-by: Fabio Estevam Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 4 ---- arch/arm/boot/dts/imx51.dtsi | 1 + arch/arm/boot/dts/imx53-ard.dts | 6 ------ arch/arm/boot/dts/imx53-evk.dts | 4 ---- arch/arm/boot/dts/imx53-qsb.dts | 4 ---- arch/arm/boot/dts/imx53-smd.dts | 4 ---- arch/arm/boot/dts/imx53.dtsi | 1 + 7 files changed, 2 insertions(+), 22 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index ce08d19f8414..68460008f662 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -185,10 +185,6 @@ }; aips@80000000 { /* aips-2 */ - sdma@83fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; - }; - i2c@83fc4000 { /* I2C2 */ status = "okay"; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 140fd28de6ab..b166e8a5242c 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -218,6 +218,7 @@ compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; }; cspi@83fc0000 { diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index d356f10dd35a..e6a189096017 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -40,12 +40,6 @@ status = "okay"; }; }; - - aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - }; }; eim-cs1@f4000000 { diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 5d36dde14038..86aebc5b4091 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts @@ -73,10 +73,6 @@ }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ status = "okay"; diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 3bfa6f147296..a0e816f2182b 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -52,10 +52,6 @@ }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ status = "okay"; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 45848afab1bd..8cdf0a2b0ff3 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -92,10 +92,6 @@ }; aips@60000000 { /* AIPS2 */ - sdma@63fb0000 { - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; - }; - i2c@63fc4000 { /* I2C2 */ status = "okay"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 25b216e610f5..4994e01a1838 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -290,6 +290,7 @@ compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; cspi@63fc0000 { -- cgit v1.2.1 From 212d0b8327b21d6dfe0a9e9dc8935a7150e370d0 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Thu, 23 Aug 2012 12:35:57 +0200 Subject: ARM: dts: imx: add imx5x usb entries Signed-off-by: Michael Grzeschik Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/boot/dts/imx53.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index b166e8a5242c..6aedb323f184 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -130,6 +130,34 @@ }; }; + usb@73f80000 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80000 0x0200>; + interrupts = <18>; + status = "disabled"; + }; + + usb@73f80200 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80200 0x0200>; + interrupts = <14>; + status = "disabled"; + }; + + usb@73f80400 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80400 0x0200>; + interrupts = <16>; + status = "disabled"; + }; + + usb@73f80600 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80600 0x0200>; + interrupts = <17>; + status = "disabled"; + }; + gpio1: gpio@73f84000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f84000 0x4000>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 4994e01a1838..776ce410d057 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -135,6 +135,34 @@ }; }; + usb@53f80000 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80000 0x0200>; + interrupts = <18>; + status = "disabled"; + }; + + usb@53f80200 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80200 0x0200>; + interrupts = <14>; + status = "disabled"; + }; + + usb@53f80400 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80400 0x0200>; + interrupts = <16>; + status = "disabled"; + }; + + usb@53f80600 { + compatible = "fsl,imx53-usb", "fsl,imx27-usb"; + reg = <0x53f80600 0x0200>; + interrupts = <17>; + status = "disabled"; + }; + gpio1: gpio@53f84000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53f84000 0x4000>; -- cgit v1.2.1 From 5dd18b0150e6f4eb3a9d06a2621cad8c73a3eccf Mon Sep 17 00:00:00 2001 From: Balaji T K Date: Tue, 7 Aug 2012 12:48:21 +0530 Subject: arm/dts: omap5: Add mmc controller nodes and board data Add OMAP MMC related device tree data for OMAP5. Signed-off-by: Balaji T K Acked-by: Arnd Bergmann Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-evm.dts | 31 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap5.dtsi | 31 +++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index 200c39ad1c82..7bb0c9dc5257 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts @@ -17,4 +17,35 @@ device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; + + vmmcsd_fixed: fixedregulator-mmcsd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + bus-width = <4>; + ti,non-removable; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 57e527083746..881d60cb12ae 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -180,5 +180,36 @@ ti,hwmods = "uart6"; clock-frequency = <48000000>; }; + + mmc1: mmc@4809c000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc1"; + ti,dual-volt; + ti,needs-special-reset; + }; + + mmc2: mmc@480b4000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc2"; + ti,needs-special-reset; + }; + + mmc3: mmc@480ad000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc3"; + ti,needs-special-reset; + }; + + mmc4: mmc@480d1000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc4"; + ti,needs-special-reset; + }; + + mmc5: mmc@480d5000 { + compatible = "ti,omap4-hsmmc"; + ti,hwmods = "mmc5"; + ti,needs-special-reset; + }; }; }; -- cgit v1.2.1 From 53d91034cf29936cabf9a4d59270dc94ed7e6c1d Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Wed, 15 Aug 2012 16:53:25 +0530 Subject: arm/dts: AM33XX: Set the default status of module to "disabled" state Ideally in common SoC dtsi file should set all modules to "disabled" state and it should get enabled in respective EVM/Board dts file as per usage. This patch sets default status of all modules to "disabled" state in am33xx.dtsi file. Currently there are no modules supported as part of Bone and EVM dts support, so care to add entry "status = "okay"" while adding support for any module. Signed-off-by: Vaibhav Hiremath Acked-by: Arnd Bergmann Cc: Benoit Cousson Cc: Grant Likely Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone.dts | 6 ++++++ arch/arm/boot/dts/am335x-evm.dts | 6 ++++++ arch/arm/boot/dts/am33xx.dtsi | 9 +++++++++ 3 files changed, 21 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index a9af4db7234c..a7906cb7989f 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -17,4 +17,10 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + ocp { + uart1: serial@44E09000 { + status = "okay"; + }; + }; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index d6a97d9eff72..5dd8a6b9f194 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -17,4 +17,10 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + ocp { + uart1: serial@44E09000 { + status = "okay"; + }; + }; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 59509c48d7e5..5f6c8e33060f 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -102,36 +102,42 @@ compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; + status = "disabled"; }; uart2: serial@48022000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; + status = "disabled"; }; uart3: serial@48024000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; + status = "disabled"; }; uart4: serial@481A6000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; + status = "disabled"; }; uart5: serial@481A8000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; + status = "disabled"; }; uart6: serial@481AA000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; + status = "disabled"; }; i2c1: i2c@44E0B000 { @@ -139,6 +145,7 @@ #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; + status = "disabled"; }; i2c2: i2c@4802A000 { @@ -146,6 +153,7 @@ #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; + status = "disabled"; }; i2c3: i2c@4819C000 { @@ -153,6 +161,7 @@ #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; + status = "disabled"; }; }; }; -- cgit v1.2.1 From 5c697ea2eec2bf4146e57f964e1163333659cbf8 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 23 Aug 2012 10:42:29 +0200 Subject: ARM: dts: mxs: Add alternative I2C muxing options for imx28 Signed-off-by: Maxime Ripard Cc: Brian Lilly Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index e2240da7ba95..fac0f69a16ec 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -410,6 +410,17 @@ fsl,pull-up = <1>; }; + i2c0_pins_b: i2c0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ + 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + saif0_pins_a: saif0@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v1.2.1 From 2f44211f938397be1a9a06945e8c6e07a7232333 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 23 Aug 2012 10:42:30 +0200 Subject: ARM: dts: mxs: Add pwm4 muxing options for imx28 Signed-off-by: Maxime Ripard Cc: Brian Lilly Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index fac0f69a16ec..ece801c727f9 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -464,6 +464,16 @@ fsl,pull-up = <0>; }; + pwm4_pins_a: pwm4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + lcdif_24bit_pins_a: lcdif-24bit@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v1.2.1 From 7f1222130c1ba4171eac1e4794c8c41631aad915 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Aug 2012 01:51:37 +0200 Subject: ARM: mx28: Add SPI 2 pinmux into imx28.dtsi Add this SSP port 2 pin multiplexing configuration into the imx28.dtsi file. Signed-off-by: Marek Vasut Cc: Chris Ball Cc: Fabio Estevam Cc: Mark Brown Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index ece801c727f9..fa5253a1f16d 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -528,6 +528,19 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; + + spi2_pins_a: spi2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ + 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ + 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ + 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; }; digctl@8001c000 { -- cgit v1.2.1 From bb2f1261c2ededd168d774e84e456bdad25ffdbf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 25 Aug 2012 01:51:38 +0200 Subject: ARM: mx28: Add USB PHY overcurrent pinmux Add the pinmux settings for USB PHY overcurrent pins. Signed-off-by: Marek Vasut Cc: Chris Ball Cc: Fabio Estevam Cc: Mark Brown Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index fa5253a1f16d..5f9dbea7e6a5 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -541,6 +541,36 @@ fsl,voltage = <1>; fsl,pull-up = <1>; }; + + usbphy0_pins_a: usbphy0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + usbphy0_pins_b: usbphy0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + usbphy1_pins_a: usbphy1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { -- cgit v1.2.1 From ef1c2096fcf390f2f6a6a835d9d26105e82abda5 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 15 Aug 2012 16:28:36 +0100 Subject: ARM: 7492/1: add strstr declaration for decompressors With the generic unaligned.h, more kernel headers get pulled in including dynamic_debug.h which needs strstr. As it is not really used, we only need a declaration here. Signed-off-by: Rob Herring Tested-by: Thomas Petazzoni Reviewed-by: Arnd Bergmann Signed-off-by: Russell King --- arch/arm/boot/compressed/decompress.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c index f41b38cafce8..9deb56a702ce 100644 --- a/arch/arm/boot/compressed/decompress.c +++ b/arch/arm/boot/compressed/decompress.c @@ -32,6 +32,9 @@ extern void error(char *); # define Tracecv(c,x) #endif +/* Not needed, but used in some headers pulled in by decompressors */ +extern char * strstr(const char * s1, const char *s2); + #ifdef CONFIG_KERNEL_GZIP #include "../../../../lib/decompress_inflate.c" #endif -- cgit v1.2.1 From 91ed4938ced262e3356a377b08e1f367da941a85 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Aug 2012 14:59:31 +0200 Subject: ARM: mxs: Update DENX M28 machine and dts file Update the mach-mxs machine by removing the enet_clkout(). The new revision of the board doesn't need that. Also, update the DTS file with all the new drivers pulled in the mainline recently, that is, SPI, LRADC, USB. Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-m28evk.dts | 79 +++++++++++++++++++++++++++++++++++--- 1 file changed, 73 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index ac3eff96a70c..8118b64362b6 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -23,6 +23,8 @@ apb@80000000 { apbh@80000000 { gpmi-nand@8000c000 { + #address-cells = <1>; + #size-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; status = "okay"; @@ -62,9 +64,27 @@ &mmc0_sck_cfg>; bus-width = <8>; wp-gpios = <&gpio3 10 1>; + vmmc-supply = <®_vddio_sd0>; status = "okay"; }; + ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; + pinctrl@80018000 { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; @@ -72,8 +92,11 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ + 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */ + 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -129,6 +152,7 @@ i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; + clock-frequency = <400000>; status = "okay"; sgtl5000: codec@0a { @@ -151,32 +175,51 @@ }; }; + lradc@80050000 { + status = "okay"; + }; + duart: serial@80074000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; status = "okay"; }; - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; + usbphy0: usbphy@8007c000 { status = "okay"; }; - auart3: serial@80070000 { + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + + auart0: serial@8006a000 { pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; + pinctrl-0 = <&auart0_2pins_a>; status = "okay"; }; }; }; ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usbphy0_pins_a>; + status = "okay"; + }; + + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usbphy1_pins_a>; + status = "okay"; + }; + mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio3 11 0>; status = "okay"; }; @@ -198,6 +241,30 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 12 0>; + }; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 13 0>; + }; }; sound { -- cgit v1.2.1 From 5decb4b63ab25fa826e117f844d6428c5e442c6f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 27 Aug 2012 13:23:27 -0300 Subject: ARM: mx28evk: Add SPI flash support mx28evk has a free slot (J89) which can be used to populate an SPI NOR Flash. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-evk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index ab78ee53fdc7..8a9a2f4023ce 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -46,6 +46,23 @@ wp-gpios = <&gpio0 28 0>; }; + ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b"; + spi-max-frequency = <40000000>; + reg = <0>; + }; + }; + pinctrl@80018000 { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_a>; -- cgit v1.2.1 From 8495a24386d3b1f0cfd17fd42e4c3ad80d88edbb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 27 Aug 2012 13:23:28 -0300 Subject: ARM: mx28evk: Add LRADC support Add LRADC support. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 8a9a2f4023ce..ed92d61b8915 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -145,6 +145,10 @@ status = "okay"; }; + lradc@80050000 { + status = "okay"; + }; + i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; -- cgit v1.2.1 From 8b23f5132d319c790e5f56df6f3df3a84071ae6e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 28 Aug 2012 20:22:45 -0300 Subject: ARM: imx27-phytec-phycore: Fix I2C EEPROM address Fix I2C EEPROM address as per 24c32 datasheet. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer --- arch/arm/boot/dts/imx27-phytec-phycore.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts index 2b0ff60247a4..2acc86cfdd05 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts @@ -49,7 +49,7 @@ i2c@1001d000 { clock-frequency = <400000>; status = "okay"; - at24@4c { + at24@52 { compatible = "at,24c32"; pagesize = <32>; reg = <0x52>; -- cgit v1.2.1 From 624411ceba816b38e9e4a013c7e4c5f36a9f4cfe Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 30 Jul 2012 18:42:20 +0530 Subject: arm/dts: Cleanup regulator naming and remove @0,1 regulators do not have a 'reg' property, hence the regulator@0, regulator@1 do not make sense. get rid of it. Reported-by: David Brown Signed-off-by: Rajendra Nayak Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-beagle.dts | 2 +- arch/arm/boot/dts/omap4-sdp.dts | 4 ++-- arch/arm/boot/dts/twl4030.dtsi | 6 +++--- arch/arm/boot/dts/twl6030.dtsi | 26 +++++++++++++------------- 4 files changed, 19 insertions(+), 19 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index cdcb98c7e075..e60cba0ed6f1 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -27,7 +27,7 @@ interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; - vsim: regulator@10 { + vsim: regulator-vsim { compatible = "ti,twl4030-vsim"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 72216e932fc0..dbcdc4a79491 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -18,7 +18,7 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; - vdd_eth: fixedregulator@0 { + vdd_eth: fixedregulator-vdd-eth { compatible = "regulator-fixed"; regulator-name = "VDD_ETH"; regulator-min-microvolt = <3300000>; @@ -28,7 +28,7 @@ regulator-boot-on; }; - vbat: fixedregulator@2 { + vbat: fixedregulator-vbat { compatible = "regulator-fixed"; regulator-name = "VBAT"; regulator-min-microvolt = <3750000>; diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 22f4d1394ed3..ff000172c93c 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -19,19 +19,19 @@ interrupts = <11>; }; - vdac: regulator@0 { + vdac: regulator-vdac { compatible = "ti,twl4030-vdac"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vpll2: regulator@1 { + vpll2: regulator-vpll2 { compatible = "ti,twl4030-vpll2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vmmc1: regulator@2 { + vmmc1: regulator-vmmc1 { compatible = "ti,twl4030-vmmc1"; regulator-min-microvolt = <1850000>; regulator-max-microvolt = <3150000>; diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi index d351b27d7213..123e2c40218a 100644 --- a/arch/arm/boot/dts/twl6030.dtsi +++ b/arch/arm/boot/dts/twl6030.dtsi @@ -20,70 +20,70 @@ interrupts = <11>; }; - vaux1: regulator@0 { + vaux1: regulator-vaux1 { compatible = "ti,twl6030-vaux1"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; }; - vaux2: regulator@1 { + vaux2: regulator-vaux2 { compatible = "ti,twl6030-vaux2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <2800000>; }; - vaux3: regulator@2 { + vaux3: regulator-vaux3 { compatible = "ti,twl6030-vaux3"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; }; - vmmc: regulator@3 { + vmmc: regulator-vmmc { compatible = "ti,twl6030-vmmc"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3000000>; }; - vpp: regulator@4 { + vpp: regulator-vpp { compatible = "ti,twl6030-vpp"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2500000>; }; - vusim: regulator@5 { + vusim: regulator-vusim { compatible = "ti,twl6030-vusim"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <2900000>; }; - vdac: regulator@6 { + vdac: regulator-vdac { compatible = "ti,twl6030-vdac"; }; - vana: regulator@7 { + vana: regulator-vana { compatible = "ti,twl6030-vana"; }; - vcxio: regulator@8 { + vcxio: regulator-vcxio { compatible = "ti,twl6030-vcxio"; regulator-always-on; }; - vusb: regulator@9 { + vusb: regulator-vusb { compatible = "ti,twl6030-vusb"; }; - v1v8: regulator@10 { + v1v8: regulator-v1v8 { compatible = "ti,twl6030-v1v8"; regulator-always-on; }; - v2v1: regulator@11 { + v2v1: regulator-v2v1 { compatible = "ti,twl6030-v2v1"; regulator-always-on; }; - clk32kg: regulator@12 { + clk32kg: regulator-clk32kg { compatible = "ti,twl6030-clk32kg"; }; }; -- cgit v1.2.1 From d5d08e2e1672da627d7c9d34a9dc1089c653e23a Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 21 Aug 2012 16:47:27 +0530 Subject: arm/dts: regulator: Add tps65910 device tree data Add device tree data for tps65910 regulator by adding all tps65910 regulator nodes. Regulator is initialized based on compatiable name provided in tps65910 DT file. All tps65910 PMIC regulator device tree nodes are placed in a seperate device tree include file (tps65910.dtsi). This patch was tested on AM335x-EVM. Signed-off-by: AnilKumar Ch Reviewed-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/tps65910.dtsi | 86 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/arm/boot/dts/tps65910.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi new file mode 100644 index 000000000000..92693a89160e --- /dev/null +++ b/arch/arm/boot/dts/tps65910.dtsi @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65910.pdf + */ + +&tps { + compatible = "ti,tps65910"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vrtc_reg: regulator@0 { + reg = <0>; + regulator-compatible = "vrtc"; + }; + + vio_reg: regulator@1 { + reg = <1>; + regulator-compatible = "vio"; + }; + + vdd1_reg: regulator@2 { + reg = <2>; + regulator-compatible = "vdd1"; + }; + + vdd2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "vdd2"; + }; + + vdd3_reg: regulator@4 { + reg = <4>; + regulator-compatible = "vdd3"; + }; + + vdig1_reg: regulator@5 { + reg = <5>; + regulator-compatible = "vdig1"; + }; + + vdig2_reg: regulator@6 { + reg = <6>; + regulator-compatible = "vdig2"; + }; + + vpll_reg: regulator@7 { + reg = <7>; + regulator-compatible = "vpll"; + }; + + vdac_reg: regulator@8 { + reg = <8>; + regulator-compatible = "vdac"; + }; + + vaux1_reg: regulator@9 { + reg = <9>; + regulator-compatible = "vaux1"; + }; + + vaux2_reg: regulator@10 { + reg = <10>; + regulator-compatible = "vaux2"; + }; + + vaux33_reg: regulator@11 { + reg = <11>; + regulator-compatible = "vaux33"; + }; + + vmmc_reg: regulator@12 { + reg = <12>; + regulator-compatible = "vmmc"; + }; + }; +}; -- cgit v1.2.1 From 54a37bae248d5b9e1d1057c4f8b4f8af8d6e5456 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 21 Aug 2012 16:47:28 +0530 Subject: arm/dts: regulator: Add tps65217 device tree data Add device tree data for tps65217 regulator by adding all tps65217 regulator nodes. Regulator is initialized based on compatiable name provided in tps65217 DT file. All tps65910 PMIC regulator device tree nodes are placed in a seperate device tree include file (tps65217.dtsi). This patch was tested on AM335x-Bone. Signed-off-by: AnilKumar Ch Reviewed-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/tps65217.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 arch/arm/boot/dts/tps65217.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi new file mode 100644 index 000000000000..a63272422d76 --- /dev/null +++ b/arch/arm/boot/dts/tps65217.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65217.pdf + */ + +&tps { + compatible = "ti,tps65217"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "dcdc1"; + }; + + dcdc2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "dcdc2"; + }; + + dcdc3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "dcdc3"; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-compatible = "ldo1"; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo2"; + }; + + ldo3_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo3"; + }; + + ldo4_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo4"; + }; + }; +}; -- cgit v1.2.1 From 1b2a9702b0f5f377ceacdbd3b2cfdf863ef53bbc Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 21 Aug 2012 16:47:29 +0530 Subject: arm/dts: Add tps65910 regulator DT data to am335x-evm.dts Add tps65910 regulator device tree data to AM335x-EVM by adding regulator consumers with tightened constraints and regulator-name. TPS65910 regulator handle can be obtained by using this regulator name. This patch also add I2C node with I2C frequency and tps65910 PMIC I2C slave address. Signed-off-by: AnilKumar Ch Reviewed-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evm.dts | 94 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 5dd8a6b9f194..9fcbacdb8f38 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -22,5 +22,99 @@ uart1: serial@44E09000 { status = "okay"; }; + + i2c1: i2c@44E0B000 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2D { + reg = <0x2D>; + }; + }; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-always-on; + }; }; }; -- cgit v1.2.1 From a06ceff6f29e34edff5d6b082885c1c4139a0362 Mon Sep 17 00:00:00 2001 From: AnilKumar Ch Date: Tue, 21 Aug 2012 16:47:30 +0530 Subject: arm/dts: Add tps65217 regulator DT data to am335x-bone.dts Add tps65217 regulator device tree data to AM335x-Bone by adding regulator consumers with tightened constraints and regulator-name. TPS65217 regulator handle can be obtained by using this regulator name. This patch also add I2C node with I2C frequency and tps65217 PMIC I2C slave address. Signed-off-by: AnilKumar Ch Reviewed-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone.dts | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index a7906cb7989f..917e7843bee7 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -22,5 +22,59 @@ uart1: serial@44E09000 { status = "okay"; }; + + i2c1: i2c@44E0B000 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + }; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + regulators { + dcdc1_reg: regulator@0 { + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-always-on; + }; }; }; -- cgit v1.2.1 From eeca6e604032af8336baafef84144dd47f5a0f99 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 20 Aug 2012 08:51:45 +0800 Subject: ARM: mxs: retrieve timer irq from device tree Rather than using the static timer irq definition, we should retrieve timer irq from device tree for better. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23.dtsi | 3 ++- arch/arm/boot/dts/imx28.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index e6138310e5ce..573066bc4c51 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -389,8 +389,9 @@ }; timrot@80068000 { + compatible = "fsl,imx23-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; - status = "disabled"; + interrupts = <28 29 30 31>; }; auart0: serial@8006c000 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 3fa6d190fab4..183fc65faa56 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -683,8 +683,9 @@ }; timrot@80068000 { + compatible = "fsl,imx28-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; - status = "disabled"; + interrupts = <48 49 50 51>; }; auart0: serial@8006a000 { -- cgit v1.2.1 From 83a84efcefe8d7935883ab9d8e45c689d5760ddf Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 20 Aug 2012 21:34:56 +0800 Subject: ARM: mxs: adopt irq_domain support for icoll driver Remove irq_domain_add_legacy call from mach-mxs.c and have icoll adopt irq_domain support in the driver. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23.dtsi | 2 +- arch/arm/boot/dts/imx28.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 573066bc4c51..bee37226399a 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -43,7 +43,7 @@ ranges; icoll: interrupt-controller@80000000 { - compatible = "fsl,imx23-icoll", "fsl,mxs-icoll"; + compatible = "fsl,imx23-icoll", "fsl,icoll"; interrupt-controller; #interrupt-cells = <1>; reg = <0x80000000 0x2000>; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 183fc65faa56..99f7d7a8ba28 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -50,7 +50,7 @@ ranges; icoll: interrupt-controller@80000000 { - compatible = "fsl,imx28-icoll", "fsl,mxs-icoll"; + compatible = "fsl,imx28-icoll", "fsl,icoll"; interrupt-controller; #interrupt-cells = <1>; reg = <0x80000000 0x2000>; -- cgit v1.2.1 From de7e934f2bd27e2636946600e4335c929fae3c87 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 31 Aug 2012 16:00:40 +0200 Subject: ARM: dts: mxs: Add I2C1 muxing options for imx28 Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 5f9dbea7e6a5..a9bda8e2ecca 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -421,6 +421,17 @@ fsl,pull-up = <1>; }; + i2c1_pins_a: i2c1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ + 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + saif0_pins_a: saif0@0 { reg = <0>; fsl,pinmux-ids = < -- cgit v1.2.1 From db84c038d6d7ff5ad1f18e2613b4d67583a7e40f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 31 Aug 2012 16:00:41 +0200 Subject: ARM: dts: mxs: Add the second I2C adapter to the CFA10049 expansion board Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-cfa10049.dts | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 arch/arm/boot/dts/imx28-cfa10049.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts new file mode 100644 index 000000000000..e0e4b8cad628 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2012 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * The CFA-10049 is an expansion board for the CFA-10036 module, thus we + * need to include the CFA-10036 DTS. + */ +/include/ "imx28-cfa10036.dts" + +/ { + model = "Crystalfontz CFA-10049 Board"; + compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; + + apb@80000000 { + apbx@80040000 { + i2c1: i2c@8005a000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + }; + }; +}; -- cgit v1.2.1 From 186e3d943a2e8cd42b2c87cba7413168e8159d3e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 3 Sep 2012 16:15:25 +0200 Subject: ARM: dts: mxs: Enable USB1 Host on the CFA-10049 expansion board Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-cfa10049.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index e0e4b8cad628..557befe1830d 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -26,6 +26,31 @@ pinctrl-0 = <&i2c1_pins_a>; status = "okay"; }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usbphy1_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; }; }; }; -- cgit v1.2.1 From fa876ceff9a78e05fb4df2b8639caa2bea24b878 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 27 Aug 2012 16:39:59 -0300 Subject: ARM: mx28evk: Add I2C EEPROM support mx28evk has a free slot U50 that can be used to populate an I2C EEPROM. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-evk.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index ed92d61b8915..a0ad71ca3a44 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -161,6 +161,12 @@ VDDIO-supply = <®_3p3v>; }; + + at24@51 { + compatible = "at24,24c32"; + pagesize = <32>; + reg = <0x51>; + }; }; pwm: pwm@80064000 { -- cgit v1.2.1 From 41bf5706f46a19a35c5b38dd1202f8e69eb2ffbf Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 4 Sep 2012 10:44:02 +0200 Subject: ARM: dts: mxs: Add missing address and size cells in SSP nodes Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index a9bda8e2ecca..96fe74e4935c 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -86,6 +86,8 @@ }; ssp0: ssp@80010000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80010000 0x2000>; interrupts = <96 82>; fsl,ssp-dma-channel = <0>; @@ -93,6 +95,8 @@ }; ssp1: ssp@80012000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80012000 0x2000>; interrupts = <97 83>; fsl,ssp-dma-channel = <1>; @@ -100,6 +104,8 @@ }; ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80014000 0x2000>; interrupts = <98 84>; fsl,ssp-dma-channel = <2>; @@ -107,6 +113,8 @@ }; ssp3: ssp@80016000 { + #address-cells = <1>; + #size-cells = <0>; reg = <0x80016000 0x2000>; interrupts = <99 85>; fsl,ssp-dma-channel = <3>; -- cgit v1.2.1 From 223d1f9213d0c5473da905ab5984c5751a8d3d6f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 4 Sep 2012 10:44:03 +0200 Subject: ARM: dts: cfa10049: Add SSP3 to the 10049 board Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-cfa10049.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 557befe1830d..1f7fa50414b6 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -20,6 +20,28 @@ compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28"; apb@80000000 { + apbh@80000000 { + pinctrl@80018000 { + spi3_pins_cfa10049: spi3-cfa10049@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */ + 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + }; + + ssp3: ssp@80016000 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_cfa10049>; + status = "okay"; + }; + }; + apbx@80040000 { i2c1: i2c@8005a000 { pinctrl-names = "default"; -- cgit v1.2.1 From acd3b69f303173b88413ba5daf5b920cd3700a48 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Sep 2012 04:56:56 +0200 Subject: ARM: dts: m28evk: Fix MMC WP pin being inverted The MMC WP is active high on the m28evk, fix this. Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-m28evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 8118b64362b6..3bab6b00c52d 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -63,7 +63,7 @@ &mmc0_cd_cfg &mmc0_sck_cfg>; bus-width = <8>; - wp-gpios = <&gpio3 10 1>; + wp-gpios = <&gpio3 10 0>; vmmc-supply = <®_vddio_sd0>; status = "okay"; }; -- cgit v1.2.1 From 500b6ae3c1edbc8fc7a3ba551f9e09acffaa4304 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Thu, 23 Aug 2012 10:47:52 +0800 Subject: ARM: PRIMA2: add missing interrupts property for pinctrl node commit 5130216265f6f924a4 missed the interrupts property Signed-off-by: Barry Song Acked-by: Linus Walleij --- arch/arm/boot/dts/prima2-cb.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts index 34ae3a64ba25..4245306d60e1 100644 --- a/arch/arm/boot/dts/prima2-cb.dts +++ b/arch/arm/boot/dts/prima2-cb.dts @@ -284,6 +284,7 @@ #interrupt-cells = <2>; compatible = "sirf,prima2-gpio-pinmux"; reg = <0xb0120000 0x10000>; + interrupts = <43 44 45 46 47>; gpio-controller; interrupt-controller; }; -- cgit v1.2.1 From 434e1c574cc304eaff630f4e92ed239f7886815f Mon Sep 17 00:00:00 2001 From: Barry Song Date: Thu, 23 Aug 2012 10:47:53 +0800 Subject: ARM: PRIMA2: rename prima2-cb.dts to prima2.dtsi as it only has SoC features The current prima2-cb.dts only includes prima2 SoC feature without board- specific descriptions. This patches rename it to dtsi and clean some useless content. Signed-off-by: Barry Song Acked-by: Linus Walleij --- arch/arm/boot/dts/prima2-cb.dts | 425 ---------------------------------------- arch/arm/boot/dts/prima2.dtsi | 423 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 423 insertions(+), 425 deletions(-) delete mode 100644 arch/arm/boot/dts/prima2-cb.dts create mode 100644 arch/arm/boot/dts/prima2.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts deleted file mode 100644 index 4245306d60e1..000000000000 --- a/arch/arm/boot/dts/prima2-cb.dts +++ /dev/null @@ -1,425 +0,0 @@ -/dts-v1/; -/ { - model = "SiRF Prima2 eVB"; - compatible = "sirf,prima2-cb", "sirf,prima2"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - memory { - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1"; - linux,stdout-path = &uart1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - reg = <0x0>; - d-cache-line-size = <32>; - i-cache-line-size = <32>; - d-cache-size = <32768>; - i-cache-size = <32768>; - /* from bootloader */ - timebase-frequency = <0>; - bus-frequency = <0>; - clock-frequency = <0>; - }; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0x80000000>; - - l2-cache-controller@80040000 { - compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; - reg = <0x80040000 0x1000>; - interrupts = <59>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - arm,filter-ranges = <0 0x40000000>; - }; - - intc: interrupt-controller@80020000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "sirf,prima2-intc"; - reg = <0x80020000 0x1000>; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x88000000 0x88000000 0x40000>; - - clock-controller@88000000 { - compatible = "sirf,prima2-clkc"; - reg = <0x88000000 0x1000>; - interrupts = <3>; - }; - - reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - }; - - rsc-controller@88020000 { - compatible = "sirf,prima2-rsc"; - reg = <0x88020000 0x1000>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90000000 0x90000000 0x10000>; - - memory-controller@90000000 { - compatible = "sirf,prima2-memc"; - reg = <0x90000000 0x10000>; - interrupts = <27>; - }; - }; - - disp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x90010000 0x90010000 0x30000>; - - display@90010000 { - compatible = "sirf,prima2-lcd"; - reg = <0x90010000 0x20000>; - interrupts = <30>; - }; - - vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x98000000 0x98000000 0x8000000>; - - graphics@98000000 { - compatible = "powervr,sgx531"; - reg = <0x98000000 0x8000000>; - interrupts = <6>; - }; - }; - - multimedia-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa0000000 0xa0000000 0x8000000>; - - multimedia@a0000000 { - compatible = "sirf,prima2-video-codec"; - reg = <0xa0000000 0x8000000>; - interrupts = <5>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xa8000000 0xa8000000 0x2000000>; - - dspif@a8000000 { - compatible = "sirf,prima2-dspif"; - reg = <0xa8000000 0x10000>; - interrupts = <9>; - }; - - gps@a8010000 { - compatible = "sirf,prima2-gps"; - reg = <0xa8010000 0x10000>; - interrupts = <7>; - }; - - dsp@a9000000 { - compatible = "sirf,prima2-dsp"; - reg = <0xa9000000 0x1000000>; - interrupts = <8>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb0000000 0xb0000000 0x180000>; - - timer@b0020000 { - compatible = "sirf,prima2-tick"; - reg = <0xb0020000 0x1000>; - interrupts = <0>; - }; - - nand@b0030000 { - compatible = "sirf,prima2-nand"; - reg = <0xb0030000 0x10000>; - interrupts = <41>; - }; - - audio@b0040000 { - compatible = "sirf,prima2-audio"; - reg = <0xb0040000 0x10000>; - interrupts = <35>; - }; - - uart0: uart@b0050000 { - cell-index = <0>; - compatible = "sirf,prima2-uart"; - reg = <0xb0050000 0x10000>; - interrupts = <17>; - }; - - uart1: uart@b0060000 { - cell-index = <1>; - compatible = "sirf,prima2-uart"; - reg = <0xb0060000 0x10000>; - interrupts = <18>; - }; - - uart2: uart@b0070000 { - cell-index = <2>; - compatible = "sirf,prima2-uart"; - reg = <0xb0070000 0x10000>; - interrupts = <19>; - }; - - usp0: usp@b0080000 { - cell-index = <0>; - compatible = "sirf,prima2-usp"; - reg = <0xb0080000 0x10000>; - interrupts = <20>; - }; - - usp1: usp@b0090000 { - cell-index = <1>; - compatible = "sirf,prima2-usp"; - reg = <0xb0090000 0x10000>; - interrupts = <21>; - }; - - usp2: usp@b00a0000 { - cell-index = <2>; - compatible = "sirf,prima2-usp"; - reg = <0xb00a0000 0x10000>; - interrupts = <22>; - }; - - dmac0: dma-controller@b00b0000 { - cell-index = <0>; - compatible = "sirf,prima2-dmac"; - reg = <0xb00b0000 0x10000>; - interrupts = <12>; - }; - - dmac1: dma-controller@b0160000 { - cell-index = <1>; - compatible = "sirf,prima2-dmac"; - reg = <0xb0160000 0x10000>; - interrupts = <13>; - }; - - vip@b00C0000 { - compatible = "sirf,prima2-vip"; - reg = <0xb00C0000 0x10000>; - }; - - spi0: spi@b00d0000 { - cell-index = <0>; - compatible = "sirf,prima2-spi"; - reg = <0xb00d0000 0x10000>; - interrupts = <15>; - }; - - spi1: spi@b0170000 { - cell-index = <1>; - compatible = "sirf,prima2-spi"; - reg = <0xb0170000 0x10000>; - interrupts = <16>; - }; - - i2c0: i2c@b00e0000 { - cell-index = <0>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00e0000 0x10000>; - interrupts = <24>; - }; - - i2c1: i2c@b00f0000 { - cell-index = <1>; - compatible = "sirf,prima2-i2c"; - reg = <0xb00f0000 0x10000>; - interrupts = <25>; - }; - - tsc@b0110000 { - compatible = "sirf,prima2-tsc"; - reg = <0xb0110000 0x10000>; - interrupts = <33>; - }; - - gpio: gpio-controller@b0120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,prima2-gpio-pinmux"; - reg = <0xb0120000 0x10000>; - interrupts = <43 44 45 46 47>; - gpio-controller; - interrupt-controller; - }; - - pwm@b0130000 { - compatible = "sirf,prima2-pwm"; - reg = <0xb0130000 0x10000>; - }; - - efusesys@b0140000 { - compatible = "sirf,prima2-efuse"; - reg = <0xb0140000 0x10000>; - }; - - pulsec@b0150000 { - compatible = "sirf,prima2-pulsec"; - reg = <0xb0150000 0x10000>; - interrupts = <48>; - }; - - pci-iobg { - compatible = "sirf,prima2-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56000000 0x56000000 0x1b00000>; - - sd0: sdhci@56000000 { - cell-index = <0>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56000000 0x100000>; - interrupts = <38>; - }; - - sd1: sdhci@56100000 { - cell-index = <1>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56100000 0x100000>; - interrupts = <38>; - }; - - sd2: sdhci@56200000 { - cell-index = <2>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56200000 0x100000>; - interrupts = <23>; - }; - - sd3: sdhci@56300000 { - cell-index = <3>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56300000 0x100000>; - interrupts = <23>; - }; - - sd4: sdhci@56400000 { - cell-index = <4>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56400000 0x100000>; - interrupts = <39>; - }; - - sd5: sdhci@56500000 { - cell-index = <5>; - compatible = "sirf,prima2-sdhc"; - reg = <0x56500000 0x100000>; - interrupts = <39>; - }; - - pci-copy@57900000 { - compatible = "sirf,prima2-pcicp"; - reg = <0x57900000 0x100000>; - interrupts = <40>; - }; - - rom-interface@57a00000 { - compatible = "sirf,prima2-romif"; - reg = <0x57a00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x80030000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,prima2-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <55 56 57>; - }; - - sysrtc@2000 { - compatible = "sirf,prima2-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <52 53 54>; - }; - - pwrc@3000 { - compatible = "sirf,prima2-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <32>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xb8000000 0xb8000000 0x40000>; - - usb0: usb@b00e0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8000000 0x10000>; - interrupts = <10>; - }; - - usb1: usb@b00f0000 { - compatible = "chipidea,ci13611a-prima2"; - reg = <0xb8010000 0x10000>; - interrupts = <11>; - }; - - sata@b00f0000 { - compatible = "synopsys,dwc-ahsata"; - reg = <0xb8020000 0x10000>; - interrupts = <37>; - }; - - security@b00f0000 { - compatible = "sirf,prima2-security"; - reg = <0xb8030000 0x10000>; - interrupts = <42>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi new file mode 100644 index 000000000000..1b716aae64f7 --- /dev/null +++ b/arch/arm/boot/dts/prima2.dtsi @@ -0,0 +1,423 @@ +/* + * DTS file for CSR SiRFprimaII SoC + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" +/ { + compatible = "sirf,prima2"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <32768>; + i-cache-size = <32768>; + /* from bootloader */ + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0x80000000>; + + l2-cache-controller@80040000 { + compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; + reg = <0x80040000 0x1000>; + interrupts = <59>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <1 1 1>; + arm,filter-ranges = <0 0x40000000>; + }; + + intc: interrupt-controller@80020000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "sirf,prima2-intc"; + reg = <0x80020000 0x1000>; + }; + + sys-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x88000000 0x88000000 0x40000>; + + clock-controller@88000000 { + compatible = "sirf,prima2-clkc"; + reg = <0x88000000 0x1000>; + interrupts = <3>; + }; + + reset-controller@88010000 { + compatible = "sirf,prima2-rstc"; + reg = <0x88010000 0x1000>; + }; + + rsc-controller@88020000 { + compatible = "sirf,prima2-rsc"; + reg = <0x88020000 0x1000>; + }; + }; + + mem-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90000000 0x90000000 0x10000>; + + memory-controller@90000000 { + compatible = "sirf,prima2-memc"; + reg = <0x90000000 0x10000>; + interrupts = <27>; + }; + }; + + disp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x90010000 0x90010000 0x30000>; + + display@90010000 { + compatible = "sirf,prima2-lcd"; + reg = <0x90010000 0x20000>; + interrupts = <30>; + }; + + vpp@90020000 { + compatible = "sirf,prima2-vpp"; + reg = <0x90020000 0x10000>; + interrupts = <31>; + }; + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x8000000>; + + graphics@98000000 { + compatible = "powervr,sgx531"; + reg = <0x98000000 0x8000000>; + interrupts = <6>; + }; + }; + + multimedia-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa0000000 0xa0000000 0x8000000>; + + multimedia@a0000000 { + compatible = "sirf,prima2-video-codec"; + reg = <0xa0000000 0x8000000>; + interrupts = <5>; + }; + }; + + dsp-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xa8000000 0xa8000000 0x2000000>; + + dspif@a8000000 { + compatible = "sirf,prima2-dspif"; + reg = <0xa8000000 0x10000>; + interrupts = <9>; + }; + + gps@a8010000 { + compatible = "sirf,prima2-gps"; + reg = <0xa8010000 0x10000>; + interrupts = <7>; + }; + + dsp@a9000000 { + compatible = "sirf,prima2-dsp"; + reg = <0xa9000000 0x1000000>; + interrupts = <8>; + }; + }; + + peri-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0xb0000000 0x180000>; + + timer@b0020000 { + compatible = "sirf,prima2-tick"; + reg = <0xb0020000 0x1000>; + interrupts = <0>; + }; + + nand@b0030000 { + compatible = "sirf,prima2-nand"; + reg = <0xb0030000 0x10000>; + interrupts = <41>; + }; + + audio@b0040000 { + compatible = "sirf,prima2-audio"; + reg = <0xb0040000 0x10000>; + interrupts = <35>; + }; + + uart0: uart@b0050000 { + cell-index = <0>; + compatible = "sirf,prima2-uart"; + reg = <0xb0050000 0x10000>; + interrupts = <17>; + }; + + uart1: uart@b0060000 { + cell-index = <1>; + compatible = "sirf,prima2-uart"; + reg = <0xb0060000 0x10000>; + interrupts = <18>; + }; + + uart2: uart@b0070000 { + cell-index = <2>; + compatible = "sirf,prima2-uart"; + reg = <0xb0070000 0x10000>; + interrupts = <19>; + }; + + usp0: usp@b0080000 { + cell-index = <0>; + compatible = "sirf,prima2-usp"; + reg = <0xb0080000 0x10000>; + interrupts = <20>; + }; + + usp1: usp@b0090000 { + cell-index = <1>; + compatible = "sirf,prima2-usp"; + reg = <0xb0090000 0x10000>; + interrupts = <21>; + }; + + usp2: usp@b00a0000 { + cell-index = <2>; + compatible = "sirf,prima2-usp"; + reg = <0xb00a0000 0x10000>; + interrupts = <22>; + }; + + dmac0: dma-controller@b00b0000 { + cell-index = <0>; + compatible = "sirf,prima2-dmac"; + reg = <0xb00b0000 0x10000>; + interrupts = <12>; + }; + + dmac1: dma-controller@b0160000 { + cell-index = <1>; + compatible = "sirf,prima2-dmac"; + reg = <0xb0160000 0x10000>; + interrupts = <13>; + }; + + vip@b00C0000 { + compatible = "sirf,prima2-vip"; + reg = <0xb00C0000 0x10000>; + }; + + spi0: spi@b00d0000 { + cell-index = <0>; + compatible = "sirf,prima2-spi"; + reg = <0xb00d0000 0x10000>; + interrupts = <15>; + }; + + spi1: spi@b0170000 { + cell-index = <1>; + compatible = "sirf,prima2-spi"; + reg = <0xb0170000 0x10000>; + interrupts = <16>; + }; + + i2c0: i2c@b00e0000 { + cell-index = <0>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00e0000 0x10000>; + interrupts = <24>; + }; + + i2c1: i2c@b00f0000 { + cell-index = <1>; + compatible = "sirf,prima2-i2c"; + reg = <0xb00f0000 0x10000>; + interrupts = <25>; + }; + + tsc@b0110000 { + compatible = "sirf,prima2-tsc"; + reg = <0xb0110000 0x10000>; + interrupts = <33>; + }; + + gpio: gpio-controller@b0120000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,prima2-gpio-pinmux"; + reg = <0xb0120000 0x10000>; + interrupts = <43 44 45 46 47>; + gpio-controller; + interrupt-controller; + }; + + pwm@b0130000 { + compatible = "sirf,prima2-pwm"; + reg = <0xb0130000 0x10000>; + }; + + efusesys@b0140000 { + compatible = "sirf,prima2-efuse"; + reg = <0xb0140000 0x10000>; + }; + + pulsec@b0150000 { + compatible = "sirf,prima2-pulsec"; + reg = <0xb0150000 0x10000>; + interrupts = <48>; + }; + + pci-iobg { + compatible = "sirf,prima2-pciiobg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56000000 0x56000000 0x1b00000>; + + sd0: sdhci@56000000 { + cell-index = <0>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56000000 0x100000>; + interrupts = <38>; + }; + + sd1: sdhci@56100000 { + cell-index = <1>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56100000 0x100000>; + interrupts = <38>; + }; + + sd2: sdhci@56200000 { + cell-index = <2>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56200000 0x100000>; + interrupts = <23>; + }; + + sd3: sdhci@56300000 { + cell-index = <3>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56300000 0x100000>; + interrupts = <23>; + }; + + sd4: sdhci@56400000 { + cell-index = <4>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56400000 0x100000>; + interrupts = <39>; + }; + + sd5: sdhci@56500000 { + cell-index = <5>; + compatible = "sirf,prima2-sdhc"; + reg = <0x56500000 0x100000>; + interrupts = <39>; + }; + + pci-copy@57900000 { + compatible = "sirf,prima2-pcicp"; + reg = <0x57900000 0x100000>; + interrupts = <40>; + }; + + rom-interface@57a00000 { + compatible = "sirf,prima2-romif"; + reg = <0x57a00000 0x100000>; + }; + }; + }; + + rtc-iobg { + compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80030000 0x10000>; + + gpsrtc@1000 { + compatible = "sirf,prima2-gpsrtc"; + reg = <0x1000 0x1000>; + interrupts = <55 56 57>; + }; + + sysrtc@2000 { + compatible = "sirf,prima2-sysrtc"; + reg = <0x2000 0x1000>; + interrupts = <52 53 54>; + }; + + pwrc@3000 { + compatible = "sirf,prima2-pwrc"; + reg = <0x3000 0x1000>; + interrupts = <32>; + }; + }; + + uus-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb8000000 0xb8000000 0x40000>; + + usb0: usb@b00e0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8000000 0x10000>; + interrupts = <10>; + }; + + usb1: usb@b00f0000 { + compatible = "chipidea,ci13611a-prima2"; + reg = <0xb8010000 0x10000>; + interrupts = <11>; + }; + + sata@b00f0000 { + compatible = "synopsys,dwc-ahsata"; + reg = <0xb8020000 0x10000>; + interrupts = <37>; + }; + + security@b00f0000 { + compatible = "sirf,prima2-security"; + reg = <0xb8030000 0x10000>; + interrupts = <42>; + }; + }; + }; +}; -- cgit v1.2.1 From 056876f6c73406c06d530d16d020177f5ec4a0bd Mon Sep 17 00:00:00 2001 From: Barry Song Date: Thu, 23 Aug 2012 10:47:54 +0800 Subject: pinctrl: sirf: add DT-binding pinmux mapping support This makes us possible to define pinmux mapping in board-specific DTS. prima2.dtsi provides all possible (groups,functions) configuration, and device in .dts select configurations from dtsi files. Signed-off-by: Barry Song Acked-by: Linus Walleij --- arch/arm/boot/dts/prima2-evb.dts | 37 +++++++ arch/arm/boot/dts/prima2.dtsi | 221 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 256 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/prima2-evb.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts new file mode 100644 index 000000000000..57286b4e7b87 --- /dev/null +++ b/arch/arm/boot/dts/prima2-evb.dts @@ -0,0 +1,37 @@ +/* + * DTS file for CSR SiRFprimaII Evaluation Board + * + * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "prima2.dtsi" + +/ { + model = "CSR SiRFprimaII Evaluation Board"; + compatible = "sirf,prima2", "sirf,prima2-cb"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + axi { + peri-iobg { + uart@b0060000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + }; + spi@b00d0000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + }; + spi@b0170000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 1b716aae64f7..055fca542120 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -277,14 +277,231 @@ interrupts = <33>; }; - gpio: gpio-controller@b0120000 { + gpio: pinctrl@b0120000 { #gpio-cells = <2>; #interrupt-cells = <2>; - compatible = "sirf,prima2-gpio-pinmux"; + compatible = "sirf,prima2-pinctrl"; reg = <0xb0120000 0x10000>; interrupts = <43 44 45 46 47>; gpio-controller; interrupt-controller; + + lcd_16pins_a: lcd0@0 { + lcd { + sirf,pins = "lcd_16bitsgrp"; + sirf,function = "lcd_16bits"; + }; + }; + lcd_18pins_a: lcd0@1 { + lcd { + sirf,pins = "lcd_18bitsgrp"; + sirf,function = "lcd_18bits"; + }; + }; + lcd_24pins_a: lcd0@2 { + lcd { + sirf,pins = "lcd_24bitsgrp"; + sirf,function = "lcd_24bits"; + }; + }; + lcdrom_pins_a: lcdrom0@0 { + lcd { + sirf,pins = "lcdromgrp"; + sirf,function = "lcdrom"; + }; + }; + uart0_pins_a: uart0@0 { + uart { + sirf,pins = "uart0grp"; + sirf,function = "uart0"; + }; + }; + uart1_pins_a: uart1@0 { + uart { + sirf,pins = "uart1grp"; + sirf,function = "uart1"; + }; + }; + uart2_pins_a: uart2@0 { + uart { + sirf,pins = "uart2grp"; + sirf,function = "uart2"; + }; + }; + uart2_noflow_pins_a: uart2@1 { + uart { + sirf,pins = "uart2_nostreamctrlgrp"; + sirf,function = "uart2_nostreamctrl"; + }; + }; + spi0_pins_a: spi0@0 { + spi { + sirf,pins = "spi0grp"; + sirf,function = "spi0"; + }; + }; + spi1_pins_a: spi1@0 { + spi { + sirf,pins = "spi1grp"; + sirf,function = "spi1"; + }; + }; + i2c0_pins_a: i2c0@0 { + i2c { + sirf,pins = "i2c0grp"; + sirf,function = "i2c0"; + }; + }; + i2c1_pins_a: i2c1@0 { + i2c { + sirf,pins = "i2c1grp"; + sirf,function = "i2c1"; + }; + }; + pwm0_pins_a: pwm0@0 { + pwm { + sirf,pins = "pwm0grp"; + sirf,function = "pwm0"; + }; + }; + pwm1_pins_a: pwm1@0 { + pwm { + sirf,pins = "pwm1grp"; + sirf,function = "pwm1"; + }; + }; + pwm2_pins_a: pwm2@0 { + pwm { + sirf,pins = "pwm2grp"; + sirf,function = "pwm2"; + }; + }; + pwm3_pins_a: pwm3@0 { + pwm { + sirf,pins = "pwm3grp"; + sirf,function = "pwm3"; + }; + }; + gps_pins_a: gps@0 { + gps { + sirf,pins = "gpsgrp"; + sirf,function = "gps"; + }; + }; + vip_pins_a: vip@0 { + vip { + sirf,pins = "vipgrp"; + sirf,function = "vip"; + }; + }; + sdmmc0_pins_a: sdmmc0@0 { + sdmmc0 { + sirf,pins = "sdmmc0grp"; + sirf,function = "sdmmc0"; + }; + }; + sdmmc1_pins_a: sdmmc1@0 { + sdmmc1 { + sirf,pins = "sdmmc1grp"; + sirf,function = "sdmmc1"; + }; + }; + sdmmc2_pins_a: sdmmc2@0 { + sdmmc2 { + sirf,pins = "sdmmc2grp"; + sirf,function = "sdmmc2"; + }; + }; + sdmmc3_pins_a: sdmmc3@0 { + sdmmc3 { + sirf,pins = "sdmmc3grp"; + sirf,function = "sdmmc3"; + }; + }; + sdmmc4_pins_a: sdmmc4@0 { + sdmmc4 { + sirf,pins = "sdmmc4grp"; + sirf,function = "sdmmc4"; + }; + }; + sdmmc5_pins_a: sdmmc5@0 { + sdmmc5 { + sirf,pins = "sdmmc5grp"; + sirf,function = "sdmmc5"; + }; + }; + i2s_pins_a: i2s@0 { + i2s { + sirf,pins = "i2sgrp"; + sirf,function = "i2s"; + }; + }; + ac97_pins_a: ac97@0 { + ac97 { + sirf,pins = "ac97grp"; + sirf,function = "ac97"; + }; + }; + nand_pins_a: nand@0 { + nand { + sirf,pins = "nandgrp"; + sirf,function = "nand"; + }; + }; + usp0_pins_a: usp0@0 { + usp0 { + sirf,pins = "usp0grp"; + sirf,function = "usp0"; + }; + }; + usp1_pins_a: usp1@0 { + usp1 { + sirf,pins = "usp1grp"; + sirf,function = "usp1"; + }; + }; + usp2_pins_a: usp2@0 { + usp2 { + sirf,pins = "usp2grp"; + sirf,function = "usp2"; + }; + }; + usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { + usb0_utmi_drvbus { + sirf,pins = "usb0_utmi_drvbusgrp"; + sirf,function = "usb0_utmi_drvbus"; + }; + }; + usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { + usb1_utmi_drvbus { + sirf,pins = "usb1_utmi_drvbusgrp"; + sirf,function = "usb1_utmi_drvbus"; + }; + }; + warm_rst_pins_a: warm_rst@0 { + warm_rst { + sirf,pins = "warm_rstgrp"; + sirf,function = "warm_rst"; + }; + }; + pulse_count_pins_a: pulse_count@0 { + pulse_count { + sirf,pins = "pulse_countgrp"; + sirf,function = "pulse_count"; + }; + }; + cko0_rst_pins_a: cko0_rst@0 { + cko0_rst { + sirf,pins = "cko0_rstgrp"; + sirf,function = "cko0_rst"; + }; + }; + cko1_rst_pins_a: cko1_rst@0 { + cko1_rst { + sirf,pins = "cko1_rstgrp"; + sirf,function = "cko1_rst"; + }; + }; }; pwm@b0130000 { -- cgit v1.2.1 From 067c182fb5b0db856b532427956b0ecd7a87c170 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 6 Sep 2012 11:40:42 +0200 Subject: ARM: LPC32xx: Adjust device tree node to new standard num-cs In spi-pl022.c, the new device tree binding is now "num-cs" for the number of chip selects. Further, pl022,hierarchy and pl022,slave-tx-disable isn't supported in favour of reasonable defaults in the driver. Adjusting phy3250.dts to it. Signed-off-by: Roland Stigge --- arch/arm/boot/dts/phy3250.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 802ec5b2fd00..a7ad85e4b8f9 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -135,13 +135,11 @@ ssp0: ssp@20084000 { #address-cells = <1>; #size-cells = <0>; - pl022,num-chipselects = <1>; + num-cs = <1>; cs-gpios = <&gpio 3 5 0>; eeprom: at25@0 { - pl022,hierarchy = <0>; pl022,interface = <0>; - pl022,slave-tx-disable = <0>; pl022,com-mode = <0>; pl022,rx-level-trig = <1>; pl022,tx-level-trig = <1>; -- cgit v1.2.1 From 25b3ab6c7e39e42245d98c27d25d9902baec7b65 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Thu, 6 Sep 2012 11:40:48 +0200 Subject: ARM: LPC32xx: Extend dts for EA3250 board This patch adds keys and leds to the EA3250 board's dts device tree file. Signed-off-by: Roland Stigge --- arch/arm/boot/dts/ea3250.dts | 109 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 108 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index d79b28d9c963..a4ba31b23c88 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -166,9 +166,116 @@ #size-cells = <0>; autorepeat; button@21 { - label = "GPIO Key UP"; + label = "Interrupt Key"; linux,code = <103>; gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; + key1 { + label = "KEY1"; + linux,code = <1>; + gpios = <&pca9532 0 0>; + }; + key2 { + label = "KEY2"; + linux,code = <2>; + gpios = <&pca9532 1 0>; + }; + key3 { + label = "KEY3"; + linux,code = <3>; + gpios = <&pca9532 2 0>; + }; + key4 { + label = "KEY4"; + linux,code = <4>; + gpios = <&pca9532 3 0>; + }; + joy0 { + label = "Joystick Key 0"; + linux,code = <10>; + gpios = <&gpio 2 0 0>; /* P2.0 */ + }; + joy1 { + label = "Joystick Key 1"; + linux,code = <11>; + gpios = <&gpio 2 1 0>; /* P2.1 */ + }; + joy2 { + label = "Joystick Key 2"; + linux,code = <12>; + gpios = <&gpio 2 2 0>; /* P2.2 */ + }; + joy3 { + label = "Joystick Key 3"; + linux,code = <13>; + gpios = <&gpio 2 3 0>; /* P2.3 */ + }; + joy4 { + label = "Joystick Key 4"; + linux,code = <14>; + gpios = <&gpio 2 4 0>; /* P2.4 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + /* LEDs on OEM Board */ + + led1 { + gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ + linux,default-trigger = "timer"; + default-state = "off"; + }; + + led2 { + gpios = <&gpio 2 10 1>; /* P2.10, active low */ + default-state = "off"; + }; + + led3 { + gpios = <&gpio 2 11 1>; /* P2.11, active low */ + default-state = "off"; + }; + + led4 { + gpios = <&gpio 2 12 1>; /* P2.12, active low */ + default-state = "off"; + }; + + /* LEDs on Base Board */ + + lede1 { + gpios = <&pca9532 8 0>; + default-state = "off"; + }; + lede2 { + gpios = <&pca9532 9 0>; + default-state = "off"; + }; + lede3 { + gpios = <&pca9532 10 0>; + default-state = "off"; + }; + lede4 { + gpios = <&pca9532 11 0>; + default-state = "off"; + }; + lede5 { + gpios = <&pca9532 12 0>; + default-state = "off"; + }; + lede6 { + gpios = <&pca9532 13 0>; + default-state = "off"; + }; + lede7 { + gpios = <&pca9532 14 0>; + default-state = "off"; + }; + lede8 { + gpios = <&pca9532 15 0>; + default-state = "off"; + }; }; }; -- cgit v1.2.1 From 167e62798ccd4172d02c8f10ca7010a301498aa3 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 9 Aug 2012 16:30:37 +0530 Subject: ARM: dt: tegra: cardhu: add entry for PMIC TPS65911. Tegra30 based platform "cardhu" have the power management IC TPS65911 for the regulator. Adding DT entry for this device. Data are chosen from downstream kernel and making the voltage output as require by default for device to operate. The default interrupt line is HIGH from PMIC device and so inverting the interrupt detection line of PMU interrupt through configuring PMC. In this patch, do not registering LDO5 because the input supply for this rail is different for different version of cardhu i..e A02 and A04. The registration will be done once the dts file for cardhu A02 and A04 are added in follow on patches. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-cardhu.dts | 134 +++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts index c169bced131e..6f9daaead5f9 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dts +++ b/arch/arm/boot/dts/tegra30-cardhu.dts @@ -126,6 +126,120 @@ ti,vsel0-state-high; ti,vsel1-state-high; }; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <0 86 0x4>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_ac_bat_reg>; + vcc2-supply = <&vdd_ac_bat_reg>; + vcc3-supply = <&vio_reg>; + vcc5-supply = <&vdd_ac_bat_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_ac_bat_reg>; + vccio-supply = <&vdd_ac_bat_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vdd1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "vdd1"; + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "vdd2"; + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: regulator@2 { + reg = <2>; + regulator-compatible = "vddctrl"; + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vio_reg: regulator@3 { + reg = <3>; + regulator-compatible = "vio"; + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo6_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; }; ahub { @@ -134,6 +248,11 @@ }; }; + pmc { + status = "okay"; + nvidia,invert-interrupt; + }; + sdhci@78000000 { status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ @@ -147,6 +266,21 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-cardhu", "nvidia,tegra-audio-wm8903"; -- cgit v1.2.1 From 640a7af58b4ac9ca2347a25410b364829bde1bb7 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 9 Aug 2012 16:30:38 +0530 Subject: ARM: dt: tegra: cardhu: split dts file for support multiple board versions There is multiple version of cardhu starting from A01 to A07. Cardhu A01 and A03 are not supported. Cardhu A02 will have different sets of GPIOs for fixed regulator compare to cardhu A04. The Cardhu A05, A06, A07 are compatibe with A04. Based on cardhu version, the related dts file need to be chosen like for cardhu A02, use tegra30-cardhu-a02.dts, cardhu A04 and more, use tegra30-cardhu-a04.dts. This patch create the DTS file A02 and A04 and convert tegra30-cardhu.dts as dts include file. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 11 ++ arch/arm/boot/dts/tegra30-cardhu-a04.dts | 10 + arch/arm/boot/dts/tegra30-cardhu.dts | 305 ----------------------------- arch/arm/boot/dts/tegra30-cardhu.dtsi | 326 +++++++++++++++++++++++++++++++ 4 files changed, 347 insertions(+), 305 deletions(-) create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a02.dts create mode 100644 arch/arm/boot/dts/tegra30-cardhu-a04.dts delete mode 100644 arch/arm/boot/dts/tegra30-cardhu.dts create mode 100644 arch/arm/boot/dts/tegra30-cardhu.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts new file mode 100644 index 000000000000..dd870b7f188b --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +/include/ "tegra30-cardhu.dtsi" + +/* This dts file support the cardhu A02 version of board */ + +/ { + model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; + compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; +}; + diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts new file mode 100644 index 000000000000..a4cae6c16ddf --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +/include/ "tegra30-cardhu.dtsi" + +/* This dts file support the cardhu A04 and later versions of board */ + +/ { + model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; + compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; +}; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts deleted file mode 100644 index 6f9daaead5f9..000000000000 --- a/arch/arm/boot/dts/tegra30-cardhu.dts +++ /dev/null @@ -1,305 +0,0 @@ -/dts-v1/; - -/include/ "tegra30.dtsi" - -/ { - model = "NVIDIA Tegra30 Cardhu evaluation board"; - compatible = "nvidia,cardhu", "nvidia,tegra30"; - - memory { - reg = <0x80000000 0x40000000>; - }; - - pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2", - "dap2_sclk_pa3", - "dap2_din_pa4", - "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - }; - }; - - serial@70006000 { - status = "okay"; - clock-frequency = <408000000>; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - - /* ALS and Proximity sensor */ - isl29028@44 { - compatible = "isil,isl29028"; - reg = <0x44>; - interrupt-parent = <&gpio>; - interrupts = <88 0x04>; /*gpio PL0 */ - }; - }; - - i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <100000>; - - wm8903: wm8903@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = <179 0x04>; /* gpio PW3 */ - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0>; - micdet-delay = <100>; - gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; - }; - - tps62361 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - - pmic: tps65911@2d { - compatible = "ti,tps65911"; - reg = <0x2d>; - - interrupts = <0 86 0x4>; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - vcc1-supply = <&vdd_ac_bat_reg>; - vcc2-supply = <&vdd_ac_bat_reg>; - vcc3-supply = <&vio_reg>; - vcc5-supply = <&vdd_ac_bat_reg>; - vcc6-supply = <&vdd2_reg>; - vcc7-supply = <&vdd_ac_bat_reg>; - vccio-supply = <&vdd_ac_bat_reg>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - vdd1_reg: regulator@0 { - reg = <0>; - regulator-compatible = "vdd1"; - regulator-name = "vddio_ddr_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd2_reg: regulator@1 { - reg = <1>; - regulator-compatible = "vdd2"; - regulator-name = "vdd_1v5_gen"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vddctrl_reg: regulator@2 { - reg = <2>; - regulator-compatible = "vddctrl"; - regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vio_reg: regulator@3 { - reg = <3>; - regulator-compatible = "vio"; - regulator-name = "vdd_1v8_gen"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo1_reg: regulator@4 { - reg = <4>; - regulator-compatible = "ldo1"; - regulator-name = "vdd_pexa,vdd_pexb"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo2_reg: regulator@5 { - reg = <5>; - regulator-compatible = "ldo2"; - regulator-name = "vdd_sata,avdd_plle"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* LDO3 is not connected to anything */ - - ldo4_reg: regulator@7 { - reg = <7>; - regulator-compatible = "ldo4"; - regulator-name = "vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo6_reg: regulator@9 { - reg = <9>; - regulator-compatible = "ldo6"; - regulator-name = "avdd_dsi_csi,pwrdet_mipi"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo7_reg: regulator@10 { - reg = <10>; - regulator-compatible = "ldo7"; - regulator-name = "vdd_pllm,x,u,a_p_c_s"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo8_reg: regulator@11 { - reg = <11>; - regulator-compatible = "ldo8"; - regulator-name = "vdd_ddr_hs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - }; - }; - - ahub { - i2s@70080400 { - status = "okay"; - }; - }; - - pmc { - status = "okay"; - nvidia,invert-interrupt; - }; - - sdhci@78000000 { - status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 155 0>; /* gpio PT3 */ - power-gpios = <&gpio 31 0>; /* gpio PD7 */ - bus-width = <4>; - }; - - sdhci@78000600 { - status = "okay"; - bus-width = <8>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-cardhu", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "NVIDIA Tegra Cardhu"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 0>; - nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - }; -}; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi new file mode 100644 index 000000000000..ba38527fcb7f --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -0,0 +1,326 @@ +/include/ "tegra30.dtsi" + +/** + * This file contains common DT entry for all fab version of Cardhu. + * There is multiple fab version of Cardhu starting from A01 to A07. + * Cardhu fab version A01 and A03 are not supported. Cardhu fab version + * A02 will have different sets of GPIOs for fixed regulator compare to + * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are + * compatible with fab version A04. Based on Cardhu fab version, the + * related dts file need to be chosen like for Cardhu fab version A02, + * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use + * tegra30-cardhu-a04.dts. + * The identification of board is done in two ways, by looking the sticker + * on PCB and by reading board id eeprom. + * The stciker will have number like 600-81291-1000-002 C.3. In this 4th + * number is the fab version like here it is 002 and hence fab version A02. + * The (downstream internal) U-Boot of Cardhu display the board-id as + * follows: + * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 + * In this Fab version is 02 i.e. A02. + * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). + * The location 0x8 of this eeprom contains the Fab version. It is 1 byte + * wide. + */ + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + }; + }; + + serial@70006000 { + status = "okay"; + clock-frequency = <408000000>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + + /* ALS and Proximity sensor */ + isl29028@44 { + compatible = "isil,isl29028"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <88 0x04>; /*gpio PL0 */ + }; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <179 0x04>; /* gpio PW3 */ + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + + tps62361 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + }; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <0 86 0x4>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_ac_bat_reg>; + vcc2-supply = <&vdd_ac_bat_reg>; + vcc3-supply = <&vio_reg>; + vcc5-supply = <&vdd_ac_bat_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_ac_bat_reg>; + vccio-supply = <&vdd_ac_bat_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vdd1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "vdd1"; + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "vdd2"; + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vddctrl_reg: regulator@2 { + reg = <2>; + regulator-compatible = "vddctrl"; + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vio_reg: regulator@3 { + reg = <3>; + regulator-compatible = "vio"; + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo2_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo6_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo7_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + }; + + ahub { + i2s@70080400 { + status = "okay"; + }; + }; + + pmc { + status = "okay"; + nvidia,invert-interrupt; + }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-cardhu", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Cardhu"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; -- cgit v1.2.1 From fa4a925230835eab27c9c97a0a6d72caa4fe2b67 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 9 Aug 2012 16:30:39 +0530 Subject: ARM: tegra: cardhu: add dt entry for fixed regulators Cadhu have multiple power rails which are controlled by GPIOs. Add support of these power rail control through fixed regulators. Add entry for all fixed regulators for cardhu-a02 and a04. The details are taken from downstream kernel. Some points on this change are: * Add the tps65910-LDO5 entry and make it always ON to supply power to SDMMC. Once the sd driver support regulator handling, this flag will be remove. * Dropping registration of rail vdd_sdmmc1 as the gpio is used by sdhci power-gpio. This need to fix in sdhci driver and then need to add the registration mechanism. Just removing power-gpio and adding fixed regulator with this gpio is causing the sd access to fail because first probe call of this regulator fails due to non-available of parent and so it calls gpio_free() which disable the pins in gpio mode make pin output to LOW causes power to OFF. In probe retry, it got success and it powered-on but it again need to do again numeration of card here. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 76 ++++++++++++++++ arch/arm/boot/dts/tegra30-cardhu-a04.dts | 88 ++++++++++++++++++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 147 +++++++++++++++++++++++++++++++ 3 files changed, 311 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index dd870b7f188b..dd4222f00eca 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -7,5 +7,81 @@ / { model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 0>; + }; + + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 0>; + }; + + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 68 0>; /* GPIO PI4 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 63 0>; /* GPIO PH7 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + reg = <104>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 2 0>; + }; + + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + reg = <105>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 83 0>; /* GPIO PK3 */ + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index a4cae6c16ddf..0828f097ca86 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -7,4 +7,92 @@ / { model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "ddr"; + reg = <100>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 0>; + }; + + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 0>; + }; + + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + reg = <102>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 238 0>; /* GPIO PDD6 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + reg = <103>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 236 0>; /* GPIO PDD4 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; + + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + reg = <104>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 8 0>; + }; + + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + reg = <105>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 234 0>; /* GPIO PDD2 */ + }; + + vdd_bl2_reg: regulator@106 { + compatible = "regulator-fixed"; + reg = <106>; + regulator-name = "vdd_bl2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 232 0>; /* GPIO PDD0 */ + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index ba38527fcb7f..47946939b49e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -162,6 +162,7 @@ vcc1-supply = <&vdd_ac_bat_reg>; vcc2-supply = <&vdd_ac_bat_reg>; vcc3-supply = <&vio_reg>; + vcc4-supply = <&vdd_5v0_reg>; vcc5-supply = <&vdd_ac_bat_reg>; vcc6-supply = <&vdd2_reg>; vcc7-supply = <&vdd_ac_bat_reg>; @@ -234,6 +235,15 @@ regulator-always-on; }; + ldo5_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + ldo6_reg: regulator@9 { reg = <9>; regulator-compatible = "ldo6"; @@ -300,6 +310,143 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + cam_1v8_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "cam_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio 220 0>; /* gpio PBB4 */ + vin-supply = <&vio_reg>; + }; + + cp_5v_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "cp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ + }; + + emmc_3v3_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "emmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 25 0>; /* gpio PD1 */ + vin-supply = <&sys_3v3_reg>; + }; + + modem_3v3_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "modem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 30 0>; /* gpio PD6 */ + }; + + pex_hvdd_3v3_reg: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "pex_hvdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 95 0>; /* gpio PL7 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam1_ldo_reg: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "vdd_cam1_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio 142 0>; /* gpio PR6 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam2_ldo_reg: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vdd_cam2_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio 143 0>; /* gpio PR7 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_cam3_ldo_reg: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "vdd_cam3_ldo"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 144 0>; /* gpio PS0 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_com_reg: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "vdd_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 24 0>; /* gpio PD0 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio 94 0>; /* gpio PL6 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_pnl1_reg: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "vdd_pnl1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio 92 0>; /* gpio PL4 */ + vin-supply = <&sys_3v3_reg>; + }; + + vdd_vid_reg: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio 152 0>; /* GPIO PT0 */ + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; }; sound { -- cgit v1.2.1 From 6529e638057d6591fb64f43a64820cce283c3536 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 20 Jun 2012 15:58:34 -0600 Subject: ARM: dt: tegra: seaboard: add regulators Seaboard uses a TPS6586x regulator. Instantiate this, and hook up a couple of fixed GPIO-controlled regulators too. Two data sources were used for the data encoded here: * The HW defaults, as extracted from real HW. * The schematic, which specifies a voltage for each LDO rail. In most cases these sources matched. The only differences is: ldo6: The HW default on Springbank is 2.85v. The HW default on Seaboard is 1.8v. The schematics for both Springbank and Seaboard match at 2.85v. However, internal research indicates that the schematics are incorrectly labelled, and 1.8v is correct. The ChromeOS kernel also uses 1.8v. Note that these settings don't entirely match those in the ChromeOS kernel found at the URL below. However, the selected values generally cause no behavior change in the kernel, and so were picked to avoid regressions. repo http://git.chromium.org/chromiumos/third_party/kernel.git branch chromeos-3.2 file arch/arm/mach-tegra/board-seaboard-power.c Portions based on work by Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-seaboard.dts | 184 +++++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 85e621ab2968..92deb36ae03c 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -374,6 +374,152 @@ status = "okay"; clock-frequency = <400000>; + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + temperature-sensor@4c { compatible = "nct1008"; reg = <0x4c>; @@ -387,6 +533,10 @@ }; }; + pmc { + nvidia,invert-interrupt; + }; + memory-controller@0x7000f400 { emc-table@190000 { reg = <190000>; @@ -473,6 +623,40 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-seaboard", "nvidia,tegra-audio-wm8903"; -- cgit v1.2.1 From 017a01045e5a2e6d1bf4394d6b895662522c25f3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 20 Jun 2012 16:53:41 -0600 Subject: ARM: dt: tegra: ventana: add regulators Ventana uses a TPS6586x regulator. Instantiate this, and hook up a couple of fixed GPIO-controlled regulators too. The data was chosen to match the PMIC HW defaults, with the following exception: ldo6: The HW default is 2.85v. The schematics are unlabelled. Internal research indicates that 1.8v is correct. Our downstream kernel also uses 1.8v. Portions based on work by Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-ventana.dts | 204 ++++++++++++++++++++++++++++++++++ 1 file changed, 204 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index be90544e6b59..4ec6b4cd9d52 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -289,6 +289,156 @@ i2c@7000d000 { status = "okay"; clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; }; usb@c5000000 { @@ -317,6 +467,60 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 22 0>; /* gpio PC6 */ + enable-active-high; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 176 0>; /* gpio PW0 */ + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-ventana", "nvidia,tegra-audio-wm8903"; -- cgit v1.2.1 From 217b8f0f357798270d9be396931e41e28ea2d00c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 21 Jun 2012 14:24:57 -0600 Subject: ARM: dt: tegra: paz00: add regulators The Toshiba AC100/PAZ00 uses a TPS6586x regulator. Instantiate this. Three data sources were used for the data encoded here: * The HW defaults, as extracted from real HW. * The schematic, which specifies a voltage for each rail in the signal names. * The AC100 kernel used by the Ubuntu port: repo git://gitorious.org/~marvin24/ac100/marvin24s-kernel.git branch chromeos-ac100-3.0 file arch/arm/mach-tegra/board-paz00-power.c For many rails, the constraints in that tree specified differing min and max voltages. In all cases, the min value was ignored, since there's no need currently to vary any of the voltages at run-time. DVFS might change this in the future. In most cases these sources all matched. Differences are: sm0: HW defaults and schematic match at 1.2v. marvin24's kernel had a max of 1.3v, but this higher voltage was only applied to HW by DVFS code, which isn't currently supported in mainline. sm1: HW defaults and schematic match at 1.0v. marvin24's kernel had a max of 1.125v, but this higher voltage was only applied to HW by DVFS code, which isn't currently supported in mainline. ldo3: The HW default is on. marvin24's kernel didn't specify always-on, but since the board wasn't marked as having fully constrained regulators, the rail was not turned off, so the difference had no effect. The rail is needed for USB. ldo6: The HW default is 2.85v. The schematics indicate 2.85v. However, since this regulator is used for the same purpose as on other boards that require 1.8v, this is set to 1.8v. Note that this regulator feeds the CRT VDAC on Tegra, and so in practice is unlikely to be used, even though it is actaully hooked up in HW. Portions based on work by Laxman Dewangan Signed-off-by: Stephen Warren Tested-by: Marc Dietrich # v2 Acked-by: Laxman Dewangan --- arch/arm/boot/dts/tegra20-paz00.dts | 173 ++++++++++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 684a9e1ff7e9..ddf287f52d49 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -272,12 +272,170 @@ status = "okay"; clock-frequency = <400000>; + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&p5valw_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "+1.2vs_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "+1.0vs_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "+3.7vs_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "+1.1vs_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "+1.2vs_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "+3.3vs_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "+2.85vs_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + /* + * Research indicates this should be + * 1.8v; other boards that use this + * rail for the same purpose need it + * set to 1.8v. The schematic signal + * name is incorrect; perhaps copied + * from an incorrect NVIDIA reference. + */ + regulator-name = "+2.85vs_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "+3.3vs_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "+2.85vs_ldo9,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "+3.3vs_rtc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + adt7461@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; }; + pmc { + nvidia,invert-interrupt; + }; + usb@c5000000 { status = "okay"; }; @@ -325,6 +483,21 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + p5valw_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+5valw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + sound { compatible = "nvidia,tegra-audio-alc5632-paz00", "nvidia,tegra-audio-alc5632"; -- cgit v1.2.1 From e7765b3746dcbd7bc3477c14217fcf0747043b4f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 25 Jun 2012 16:41:25 -0600 Subject: ARM: dt: tegra: whistler: add regulators Whistler uses a Maxim 8907 regulator. Instantiate this. The voltage settings were derived from the schematic. The only exception is the BBAT voltage; the schematic says 1.2v, but the HW can't go that low, so use the HW default of 2.4v instead. Almost all regulators list all driven supply signal names in their regulator-names property. The exception is nvvdd_sv3, which is in turn named 12 more different names on the schematic, so these were omitted for brevity. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-whistler.dts | 293 +++++++++++++++++++++++++++++++++ 1 file changed, 293 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 6916310bf58f..4ae1e5dcfa62 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -261,6 +261,284 @@ gpio-controller; #gpio-cells = <2>; }; + + max8907@3c { + compatible = "maxim,max8907"; + reg = <0x3c>; + interrupts = <0 86 0x4>; + + mbatt-supply = <&usb0_vbus_reg>; + in-v1-supply = <&mbatt_reg>; + in-v2-supply = <&mbatt_reg>; + in-v3-supply = <&mbatt_reg>; + in1-supply = <&mbatt_reg>; + in2-supply = <&nvvdd_sv3_reg>; + in3-supply = <&mbatt_reg>; + in4-supply = <&mbatt_reg>; + in5-supply = <&mbatt_reg>; + in6-supply = <&mbatt_reg>; + in7-supply = <&mbatt_reg>; + in8-supply = <&mbatt_reg>; + in9-supply = <&mbatt_reg>; + in10-supply = <&mbatt_reg>; + in11-supply = <&mbatt_reg>; + in12-supply = <&mbatt_reg>; + in13-supply = <&mbatt_reg>; + in14-supply = <&mbatt_reg>; + in15-supply = <&mbatt_reg>; + in16-supply = <&mbatt_reg>; + in17-supply = <&nvvdd_sv3_reg>; + in18-supply = <&nvvdd_sv3_reg>; + in19-supply = <&mbatt_reg>; + in20-supply = <&mbatt_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + mbatt_reg: regulator@0 { + reg = <0>; + regulator-compatible = "mbatt"; + regulator-name = "vbat_pmu"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sd1"; + regulator-name = "nvvdd_sv1,vdd_cpu_pmu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sd2"; + regulator-name = "nvvdd_sv2,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + nvvdd_sv3_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sd3"; + regulator-name = "nvvdd_sv3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; + regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; + regulator-name = "nvvdd_ldo2,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo3"; + regulator-name = "nvvdd_ldo3,vcom_1v8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; + regulator-name = "nvvdd_ldo4,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; + regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; + regulator-name = "nvvdd_ldo6,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; + regulator-name = "nvvdd_ldo7,avddio_audio"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; + regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo9"; + regulator-name = "nvvdd_ldo9,avdd_cam*"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo10"; + regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo11"; + regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@15 { + reg = <15>; + regulator-compatible = "ldo12"; + regulator-name = "nvvdd_ldo12,vddio_sdio"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + regulator@16 { + reg = <16>; + regulator-compatible = "ldo13"; + regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@17 { + reg = <17>; + regulator-compatible = "ldo14"; + regulator-name = "nvvdd_ldo14,avdd_vdac"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@18 { + reg = <18>; + regulator-compatible = "ldo15"; + regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@19 { + reg = <19>; + regulator-compatible = "ldo16"; + regulator-name = "nvvdd_ldo16,vdd_dbrtr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + regulator@20 { + reg = <20>; + regulator-compatible = "ldo17"; + regulator-name = "nvvdd_ldo17,vddio_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@21 { + reg = <21>; + regulator-compatible = "ldo18"; + regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@22 { + reg = <22>; + regulator-compatible = "ldo19"; + regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + regulator@23 { + reg = <23>; + regulator-compatible = "ldo20"; + regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@24 { + reg = <24>; + regulator-compatible = "out5v"; + regulator-name = "usb0_vbus_reg"; + }; + + regulator@25 { + reg = <25>; + regulator-compatible = "out33v"; + regulator-name = "pmu_out3v3"; + }; + + regulator@26 { + reg = <26>; + regulator-compatible = "bbat"; + regulator-name = "pmu_bbat"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2400000>; + regulator-always-on; + }; + + regulator@27 { + reg = <27>; + regulator-compatible = "sdby"; + regulator-name = "vdd_aon"; + regulator-always-on; + }; + + regulator@28 { + reg = <28>; + regulator-compatible = "vrtc"; + regulator-name = "vrtc,pmu_vccadc"; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; }; usb@c5000000 { @@ -284,6 +562,21 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb0_vbus_reg: regulator { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8753-whistler", "nvidia,tegra-audio-wm8753"; -- cgit v1.2.1 From 87711d8c7c70387e91d43d88e12983c4d3f9fbb0 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 7 Sep 2012 06:14:26 +0900 Subject: ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC Add pinctrl driver nodes for the three instances of pin controllers in SAMSUNG EXYNOS4210 SoC and add the pin group nodes available in the each of those three instances. Signed-off-by: Thomas Abraham Acked-by: Linus Walleij Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 457 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos4210.dtsi | 37 +++ 2 files changed, 494 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi new file mode 100644 index 000000000000..b12cf272ad0d --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -0,0 +1,457 @@ +/* + * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2011-2012 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl@11400000 { + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart_audio_a: uart-audio-a { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart_audio_b: uart-audio-b { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb-6", "gpb-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + ac97_bus: ac97-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@11000000 { + sd0_clk: sd0-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd4_clk: sd4-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd4_cmd: sd4-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd4_cd: sd4-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd4_bus1: sd4-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd4_bus4: sd4-bus-width4 { + samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd4_bus8: sd4-bus-width8 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <4>; + samsung,pin-drv = <0>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpk1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpk1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpk1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpk1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpk2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpk2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpk2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpk2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd2_bus8: sd2-bus-width8 { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd3_clk: sd3-clk { + samsung,pins = "gpk3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd3_cmd: sd3-cmd { + samsung,pins = "gpk3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd3_cd: sd3-cd { + samsung,pins = "gpk3-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd3_bus1: sd3-bus-width1 { + samsung,pins = "gpk3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + sd3_bus4: sd3-bus-width4 { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + eint0: ext-int0 { + samsung,pins = "gpx0-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + eint8: ext-int8 { + samsung,pins = "gpx1-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + eint15: ext-int15 { + samsung,pins = "gpx1-7"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + eint16: ext-int16 { + samsung,pins = "gpx2-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + eint31: ext-int31 { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@03860000 { + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm0_bus: pcm0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4"; + samsung,pin-function = <0x3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 02891fe876e4..a4bd0c9a206e 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -20,6 +20,7 @@ */ /include/ "skeleton.dtsi" +/include/ "exynos4210-pinctrl.dtsi" / { compatible = "samsung,exynos4210"; @@ -29,6 +30,9 @@ spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; }; gic:interrupt-controller@10490000 { @@ -50,6 +54,39 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; }; + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,pinctrl-exynos4210"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,pinctrl-exynos4210"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0>; + interrupt-controller; + #interrupt-cells = <2>; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>, + <0 32 0>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + compatible = "samsung,pinctrl-exynos4210"; + reg = <0x03860000 0x1000>; + }; + watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; -- cgit v1.2.1 From 1128658a0841dbfdc95dc2e3e8d573e4eb1f6a40 Mon Sep 17 00:00:00 2001 From: Shaik Ameer Basha Date: Fri, 7 Sep 2012 14:13:08 +0900 Subject: ARM: EXYNOS: Adds G-Scaler device from Device Tree This patch adds, - 4 G-Scaler devices to the DT device list - G-Scaler specific entries to the machine file - binding documentation for G-Scaler entries Signed-off-by: Abhilash Kesavan Signed-off-by: Leela Krishna Amudala Signed-off-by: Shaik Ameer Basha Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 004aaa8d123c..b55794b494b4 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -27,6 +27,10 @@ spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; + gsc0 = &gsc_0; + gsc1 = &gsc_1; + gsc2 = &gsc_2; + gsc3 = &gsc_3; }; gic:interrupt-controller@10481000 { @@ -460,4 +464,28 @@ #gpio-cells = <4>; }; }; + + gsc_0: gsc@0x13e00000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; + }; + + gsc_1: gsc@0x13e10000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = <0 86 0>; + }; + + gsc_2: gsc@0x13e20000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e20000 0x1000>; + interrupts = <0 87 0>; + }; + + gsc_3: gsc@0x13e30000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e30000 0x1000>; + interrupts = <0 88 0>; + }; }; -- cgit v1.2.1 From 6e6a9a504757e681e00d7212587950a925f66332 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Wed, 25 Jul 2012 10:57:58 +0530 Subject: ARM: dts: omap5-evm: Add I2C support Add I2C data nodes in omap5 device tree file. Signed-off-by: Sourav Poddar Acked-by: Santosh Shilimkar Acked-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 881d60cb12ae..424ad161aa44 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -145,6 +145,41 @@ #interrupt-cells = <1>; }; + i2c1: i2c@48070000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + + i2c4: i2c@4807A000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c4"; + }; + + i2c5: i2c@4807C000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c5"; + }; + uart1: serial@4806a000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart1"; -- cgit v1.2.1 From 08f3e21b81d4907e8ef513d97805d02df008f7d2 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Wed, 25 Jul 2012 11:02:43 +0530 Subject: ARM: dts: omap5-evm: Add tmp102 sensor support Add tmp102 temperature sensor data in omap5 evm dts file. Signed-off-by: Sourav Poddar Acked-by: Santosh Shilimkar Acked-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-evm.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index 7bb0c9dc5257..1790f41ca23e 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts @@ -49,3 +49,13 @@ &mmc5 { status = "disabled"; }; + +&i2c4 { + clock-frequency = <400000>; + + /* Temperature Sensor */ + tmp102@48{ + compatible = "ti,tmp102"; + reg = <0x48>; + }; +}; -- cgit v1.2.1 From 5449fbc27b27317526391409b7bcacd2104a6a2f Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Wed, 25 Jul 2012 11:03:27 +0530 Subject: ARM: dts: omap5-evm: Add keypad data Add keypad data node in omap5 device tree file. Also fill the device tree binding parameters with the required value in "omap5-evm" dts file. Signed-off-by: Sourav Poddar Acked-by: Santosh Shilimkar Acked-by: Felipe Balbi [b-cousson@ti.com: Fix merge issue with MMC patches, put node at the proper place, align entries and comments] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-evm.dts | 13 +++++++++++++ arch/arm/boot/dts/omap5.dtsi | 5 +++++ 2 files changed, 18 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index 1790f41ca23e..457d1ec7ed93 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts @@ -24,6 +24,7 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; + }; &mmc1 { @@ -59,3 +60,15 @@ reg = <0x48>; }; }; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x02020073 /* VOLUP */ + 0x02030072 /* VOLDOWM */ + 0x020400e7 /* SEND */ + 0x02050066 /* HOME */ + 0x0206006b /* END */ + 0x020700d9>; /* SEARCH */ + linux,input-no-autorepeat; +}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 424ad161aa44..4c11ae1975cc 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -246,5 +246,10 @@ ti,hwmods = "mmc5"; ti,needs-special-reset; }; + + keypad: keypad@4ae1c000 { + compatible = "ti,omap4-keypad"; + ti,hwmods = "kbd"; + }; }; }; -- cgit v1.2.1 From 288710151333ee2c730e9c9c26376c1dac83c292 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Wed, 25 Jul 2012 10:59:40 +0530 Subject: ARM: dts: omap5-evm: Add bmp085 sensor support Add bmp085 pressure sensor data in omap5 evm dts file. Signed-off-by: Sourav Poddar Acked-by: Santosh Shilimkar Acked-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5-evm.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts index 457d1ec7ed93..9c41a3f311aa 100644 --- a/arch/arm/boot/dts/omap5-evm.dts +++ b/arch/arm/boot/dts/omap5-evm.dts @@ -51,6 +51,16 @@ status = "disabled"; }; +&i2c2 { + clock-frequency = <400000>; + + /* Pressure Sensor */ + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + }; +}; + &i2c4 { clock-frequency = <400000>; -- cgit v1.2.1 From 61bc35445baacab98f500b3367d40e9b8cf41c43 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Tue, 14 Aug 2012 16:45:37 +0530 Subject: ARM: dts: omap4-sdp: Add keypad data Add keypad data node in omap4 device tree file. Also fill the device tree binding parameters with the required value in "omap4-sdp" dts file. Signed-off-by: Sourav Poddar Cc: Tony Lindgren Cc: Rob Herring Cc: Grant Likely Cc: Felipe Balbi Signed-off-by: Benoit Cousson [b-cousson@ti.com: Re-align the entries and the comments] --- arch/arm/boot/dts/omap4-sdp.dts | 70 +++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 5 +++ 2 files changed, 75 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index dbcdc4a79491..8869c1e209fe 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -226,3 +226,73 @@ bus-width = <4>; ti,non-removable; }; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x00000012 /* KEY_E */ + 0x00010013 /* KEY_R */ + 0x00020014 /* KEY_T */ + 0x00030066 /* KEY_HOME */ + 0x0004003f /* KEY_F5 */ + 0x000500f0 /* KEY_UNKNOWN */ + 0x00060017 /* KEY_I */ + 0x0007002a /* KEY_LEFTSHIFT */ + 0x01000020 /* KEY_D*/ + 0x01010021 /* KEY_F */ + 0x01020022 /* KEY_G */ + 0x010300e7 /* KEY_SEND */ + 0x01040040 /* KEY_F6 */ + 0x010500f0 /* KEY_UNKNOWN */ + 0x01060025 /* KEY_K */ + 0x0107001c /* KEY_ENTER */ + 0x0200002d /* KEY_X */ + 0x0201002e /* KEY_C */ + 0x0202002f /* KEY_V */ + 0x0203006b /* KEY_END */ + 0x02040041 /* KEY_F7 */ + 0x020500f0 /* KEY_UNKNOWN */ + 0x02060034 /* KEY_DOT */ + 0x0207003a /* KEY_CAPSLOCK */ + 0x0300002c /* KEY_Z */ + 0x0301004e /* KEY_KPLUS */ + 0x03020030 /* KEY_B */ + 0x0303003b /* KEY_F1 */ + 0x03040042 /* KEY_F8 */ + 0x030500f0 /* KEY_UNKNOWN */ + 0x03060018 /* KEY_O */ + 0x03070039 /* KEY_SPACE */ + 0x04000011 /* KEY_W */ + 0x04010015 /* KEY_Y */ + 0x04020016 /* KEY_U */ + 0x0403003c /* KEY_F2 */ + 0x04040073 /* KEY_VOLUMEUP */ + 0x040500f0 /* KEY_UNKNOWN */ + 0x04060026 /* KEY_L */ + 0x04070069 /* KEY_LEFT */ + 0x0500001f /* KEY_S */ + 0x05010023 /* KEY_H */ + 0x05020024 /* KEY_J */ + 0x0503003d /* KEY_F3 */ + 0x05040043 /* KEY_F9 */ + 0x05050072 /* KEY_VOLUMEDOWN */ + 0x05060032 /* KEY_M */ + 0x0507006a /* KEY_RIGHT */ + 0x06000010 /* KEY_Q */ + 0x0601001e /* KEY_A */ + 0x06020031 /* KEY_N */ + 0x0603009e /* KEY_BACK */ + 0x0604000e /* KEY_BACKSPACE */ + 0x060500f0 /* KEY_UNKNOWN */ + 0x06060019 /* KEY_P */ + 0x06070067 /* KEY_UP */ + 0x07000094 /* KEY_PROG1 */ + 0x07010095 /* KEY_PROG2 */ + 0x070200ca /* KEY_PROG3 */ + 0x070300cb /* KEY_PROG4 */ + 0x0704003e /* KEY_F4 */ + 0x070500f0 /* KEY_UNKNOWN */ + 0x07060160 /* KEY_OK */ + 0x0707006c>; /* KEY_DOWN */ + linux,input-no-autorepeat; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 04cbbcb6ff91..7fc45bb8a951 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -295,5 +295,10 @@ interrupt-parent = <&gic>; ti,hwmods = "dmic"; }; + + keypad: keypad@4a31c000 { + compatible = "ti,omap4-keypad"; + ti,hwmods = "kbd"; + }; }; }; -- cgit v1.2.1 From 11c27069cf963f7445a7b515bcb703d90ae0c162 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Fri, 20 Jan 2012 20:35:26 +0530 Subject: ARM: dts: EMIF and LPDDR2 device tree data for OMAP4 boards Device tree data for the EMIF sdram controllers in OMAP4 and LPDDR2 memory devices attached to OMAP4 boards. Reviewed-by: Grant Likely Tested-by: Lokesh Vutla Signed-off-by: Aneesh V [santosh.shilimkar@ti.com: Rebased against 3.6-rc] Signed-off-by: Santosh Shilimkar [b-cousson@ti.com: Use label in board to access EMIF nodes] Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/elpida_ecb240abacn.dtsi | 67 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap4-panda.dts | 11 +++++ arch/arm/boot/dts/omap4-sdp.dts | 11 +++++ arch/arm/boot/dts/omap4.dtsi | 18 +++++++++ 4 files changed, 107 insertions(+) create mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi new file mode 100644 index 000000000000..f97f70f83374 --- /dev/null +++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi @@ -0,0 +1,67 @@ +/* + * Common devices used in different OMAP boards + */ + +/ { + elpida_ECB240ABACN: lpddr2 { + compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; + density = <2048>; + io-width = <32>; + + tRPab-min-tck = <3>; + tRCD-min-tck = <3>; + tWR-min-tck = <3>; + tRASmin-min-tck = <3>; + tRRD-min-tck = <2>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tRTP-min-tck = <2>; + tCKE-min-tck = <3>; + tCKESR-min-tck = <3>; + tFAW-min-tck = <8>; + + timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <7500>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + + timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <200000000>; + tRPab = <21000>; + tRCD = <18000>; + tWR = <15000>; + tRAS-min = <42000>; + tRRD = <10000>; + tWTR = <10000>; + tXP = <7500>; + tRTP = <7500>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tZQCS = <90000>; + tZQCL = <360000>; + tZQinit = <1000000>; + tRAS-max-ns = <70000>; + tDQSCK-max-derated = <6000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 9880c12877b3..20b966ee1bb3 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -8,6 +8,7 @@ /dts-v1/; /include/ "omap4.dtsi" +/include/ "elpida_ecb240abacn.dtsi" / { model = "TI OMAP4 PandaBoard"; @@ -126,3 +127,13 @@ ti,non-removable; bus-width = <4>; }; + +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 8869c1e209fe..7e83a61de0b2 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -8,6 +8,7 @@ /dts-v1/; /include/ "omap4.dtsi" +/include/ "elpida_ecb240abacn.dtsi" / { model = "TI OMAP4 SDP board"; @@ -227,6 +228,16 @@ ti,non-removable; }; +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + &keypad { keypad,num-rows = <8>; keypad,num-columns = <8>; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 7fc45bb8a951..c7dc11feb9da 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -300,5 +300,23 @@ compatible = "ti,omap4-keypad"; ti,hwmods = "kbd"; }; + + emif1: emif@4c000000 { + compatible = "ti,emif-4d"; + ti,hwmods = "emif1"; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; + + emif2: emif@4d000000 { + compatible = "ti,emif-4d"; + ti,hwmods = "emif2"; + phy-type = <1>; + hw-caps-read-idle-ctrl; + hw-caps-ll-interface; + hw-caps-temp-alert; + }; }; }; -- cgit v1.2.1 From 926fd45ba9eeb4c3d0454b934161ee884dd82a22 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 4 Jul 2012 17:57:34 +0530 Subject: ARM: OMAP4: Add L2 Cache Controller in Device Tree Provide PL310 Level 2 Cache Controller Device Tree support for OMAP4 based devices. Signed-off-by: Santosh Shilimkar Acked-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index c7dc11feb9da..cb18d2a2971c 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -30,12 +30,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; cpu@1 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; }; + L2: l2-cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. -- cgit v1.2.1 From eed0de27726a55f145490619510c8ec58c9dc767 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 4 Jul 2012 18:32:32 +0530 Subject: ARM: OMAP4: Add local timer support for Device Tree Add cortex-a9 local timer support for all OMAP4 based SOCs using DT. Signed-off-by: Santosh Shilimkar Acked-by: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index cb18d2a2971c..2b670ab86eae 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -45,6 +45,12 @@ cache-level = <2>; }; + local-timer@0x48240600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x48240600 0x20>; + interrupts = <1 13 0x304>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. -- cgit v1.2.1 From 5635121edb18cda14a60e4702f3ae53add5df894 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Mon, 3 Sep 2012 17:56:32 +0200 Subject: ARM: dts: OMAP4: Cleanup and move GIC outside of the OCP Remove some useless comment and move GIC controller outside of the OCP node since it does use the MPU internal bus and not the OCP. This will not change the functionality but will reflect the reality more accurately. Signed-off-by: Benoit Cousson Acked-by: Santosh Shilimkar --- arch/arm/boot/dts/omap4.dtsi | 40 ++++++++-------------------------------- 1 file changed, 8 insertions(+), 32 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2b670ab86eae..1853dc73085b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -38,6 +38,14 @@ }; }; + gic: interrupt-controller@48241000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48241000 0x1000>, + <0x48240100 0x0100>; + }; + L2: l2-cache-controller@48242000 { compatible = "arm,pl310-cache"; reg = <0x48242000 0x1000>; @@ -76,30 +84,6 @@ /* * XXX: Use a flat representation of the OMAP4 interconnect. * The real OMAP interconnect network is quite complex. - * - * MPU -+-- MPU_PRIVATE - GIC, L2 - * | - * +----------------+----------+ - * | | | - * + +- EMIF - DDR | - * | | | - * | + +--------+ - * | | | - * | +- L4_ABE - AESS, MCBSP, TIMERs... - * | | - * +- L3_MAIN --+- L4_CORE - IPs... - * | - * +- L4_PER - IPs... - * | - * +- L4_CFG -+- L4_WKUP - IPs... - * | | - * | +- IPs... - * +- IPU ----+ - * | | - * +- DSP ----+ - * | | - * +- DSS ----+ - * * Since that will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. @@ -111,14 +95,6 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - gic: interrupt-controller@48241000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48241000 0x1000>, - <0x48240100 0x0100>; - }; - gpio1: gpio@4a310000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1"; -- cgit v1.2.1 From a60be2fe9735894b8e0e2de80d2bdb37d87cd0c5 Mon Sep 17 00:00:00 2001 From: Florian Vaussard Date: Wed, 5 Sep 2012 09:46:26 +0200 Subject: ARM: dts: omap3: Add gpio-twl4030 properties for BeagleBoard and omap3-EVM Add device tree properties for twl4030/gpio, according to the platform data of corresponding boards. This enables the led connected to LEDB output for both boards, as well as pullups/pulldowns on GPIO for the BeagleBoard. Signed-off-by: Florian Vaussard Acked-by: Linus Walleij Acked-by: Vaibhav Hiremath --- arch/arm/boot/dts/omap3-beagle.dts | 20 ++++++++++++++++++++ arch/arm/boot/dts/omap3-evm.dts | 13 +++++++++++++ 2 files changed, 33 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index e60cba0ed6f1..3fe35c27ce1c 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -17,6 +17,14 @@ device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; + + leds { + compatible = "gpio-leds"; + pmu_stat { + label = "beagleboard::pmu_stat"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + }; + }; }; &i2c1 { @@ -67,3 +75,15 @@ &mmc3 { status = "disabled"; }; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index f349ee9182ce..e8ba1c247a39 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -17,6 +17,15 @@ device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; + + leds { + compatible = "gpio-leds"; + ledb { + label = "omap3evm::ledb"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + linux,default-trigger = "default-on"; + }; + }; }; &i2c1 { @@ -46,3 +55,7 @@ reg = <0x5c>; }; }; + +&twl_gpio { + ti,use-leds; +}; -- cgit v1.2.1 From 1c1737e5635d902e125394d7f66bccaf0f8c772c Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 5 Sep 2012 16:42:04 +0200 Subject: ARM: dts: omap3-beagle: Add heartbeat and mmc LEDs support Add the support for D6 and D7 LEDs on Beagle board. - D6 will be used for heartbeat - D7 will be used for mmc0 Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-beagle.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 3fe35c27ce1c..ca46fb2b5803 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -24,6 +24,18 @@ label = "beagleboard::pmu_stat"; gpios = <&twl_gpio 19 0>; /* LEDB */ }; + + heartbeat { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; }; }; -- cgit v1.2.1 From 3f187f82948c236cfbc7df3783df50eedcf62d03 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 26 Jul 2012 17:01:32 +0300 Subject: ARM: dts: omap2: Add McBSP entries for OMAP2420 and OMAP2430 SoC The McBSP IP within OMAP2420 and 2430 is different we need to create separate dtsi files for them. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap2420.dtsi | 39 +++++++++++++++++++ arch/arm/boot/dts/omap2430.dtsi | 83 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm/boot/dts/omap2420.dtsi create mode 100644 arch/arm/boot/dts/omap2430.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi new file mode 100644 index 000000000000..6174d3d93b1f --- /dev/null +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -0,0 +1,39 @@ +/* + * Device Tree Source for OMAP2420 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap2.dtsi" + +/ { + compatible = "ti,omap2420", "ti,omap2"; + + ocp { + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + interrupt-parent = <&intc>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + interrupt-parent = <&intc>; + ti,hwmods = "mcbsp2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi new file mode 100644 index 000000000000..59a639a33794 --- /dev/null +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -0,0 +1,83 @@ +/* + * Device Tree Source for OMAP243x SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap2.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2"; + + ocp { + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <64>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>, /* RX interrupt */ + <61>; /* RX overflow interrupt */ + interrupt-names = "common", "tx", "rx", "rx_overflow"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@4808c000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808c000 0xff>; + reg-names = "mpu"; + interrupts = <17>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@4808e000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808e000 0xff>; + reg-names = "mpu"; + interrupts = <18>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <19>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + }; + }; +}; -- cgit v1.2.1 From 40c9e5cacfc186b537b402a59319cd6a88ce338b Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 8 Aug 2012 11:02:52 +0300 Subject: ARM: dts: omap2420-h4: Include omap2420.dtsi file instead the common omap2 Since the board is based on OMAP2420 we should include the dedicated dtsi file (which includes the common omap2 dtsi). Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap2420-h4.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 25b50b759dec..77b84e17c477 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap2.dtsi" +/include/ "omap2420.dtsi" / { model = "TI OMAP2420 H4 board"; -- cgit v1.2.1 From 0be484bf4d0e9a78520b9e576de03de89e9d5882 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 5 Sep 2012 14:21:22 +0300 Subject: ARM: dts: omap3: Add McBSP entries Create the needed sections to be able to probe McBSP ports via DT. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3.dtsi | 69 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 810947198208..f024bb3034a6 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -220,5 +220,74 @@ compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@49022000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49022000 0xff>, + <0x49028000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <17>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>, /* RX interrupt */ + <4>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + interrupt-parent = <&intc>; + ti,buffer-size = <1280>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@49024000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49024000 0xff>, + <0x4902a000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <22>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>, /* RX interrupt */ + <5>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@49026000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49026000 0xff>; + reg-names = "mpu"; + interrupts = <23>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <27>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + }; }; }; -- cgit v1.2.1 From 2995a10002e20b5acfbaf9553ca1f22d9575f032 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 26 Jul 2012 17:13:21 +0300 Subject: ARM: dts: omap4: Add McBSP entries Create the sections describing the McBSP ports to be able to use them via DT. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 1853dc73085b..5ed3b944965b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -287,6 +287,53 @@ ti,hwmods = "dmic"; }; + mcbsp1: mcbsp@40122000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40122000 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 17 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@40124000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40124000 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 22 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@40126000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40126000 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 23 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@48096000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x48096000 0xff>; /* L4 Interconnect */ + reg-names = "mpu"; + interrupts = <0 16 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + keypad: keypad@4a31c000 { compatible = "ti,omap4-keypad"; ti,hwmods = "kbd"; -- cgit v1.2.1 From 63467cf23284588901f2edfcaabbfdef489ffc9b Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 29 Aug 2012 16:31:06 +0300 Subject: ARM: dts: omap4: Add reg-names for McPDM and DMIC In order to get the memory areas by name when booted with DT. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 5ed3b944965b..9f851dfe7507 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -273,6 +273,7 @@ compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; interrupts = <0 112 0x4>; interrupt-parent = <&gic>; ti,hwmods = "mcpdm"; @@ -282,6 +283,7 @@ compatible = "ti,omap4-dmic"; reg = <0x4012e000 0x7f>, /* MPU private access */ <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; interrupts = <0 114 0x4>; interrupt-parent = <&gic>; ti,hwmods = "dmic"; -- cgit v1.2.1 From ffd5db24e7491135da12d73244d6974153f4765f Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 29 Aug 2012 16:31:04 +0300 Subject: ARM: dts: omap5: Add McBSP entries Create the sections describing the McBSP ports to be able to use them via DT. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 4c11ae1975cc..aa97e9318def 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -251,5 +251,41 @@ compatible = "ti,omap4-keypad"; ti,hwmods = "kbd"; }; + + mcbsp1: mcbsp@40122000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40122000 0xff>, /* MPU private access */ + <0x49022000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 17 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@40124000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40124000 0xff>, /* MPU private access */ + <0x49024000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 22 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@40126000 { + compatible = "ti,omap4-mcbsp"; + reg = <0x40126000 0xff>, /* MPU private access */ + <0x49026000 0xff>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 23 0x4>; + interrupt-names = "common"; + interrupt-parent = <&gic>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; }; }; -- cgit v1.2.1 From cbb57f071f4dbd7684e6b7280dbc2286fdcecf0b Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 29 Aug 2012 16:31:07 +0300 Subject: ARM: dts: omap5: Add McPDM and DMIC section to the dtsi file To be able to load the McPDM and DMIC driver when booted with device tree. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap5.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index aa97e9318def..9ac75b37c992 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -252,6 +252,26 @@ ti,hwmods = "kbd"; }; + mcpdm: mcpdm@40132000 { + compatible = "ti,omap4-mcpdm"; + reg = <0x40132000 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 112 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "mcpdm"; + }; + + dmic: dmic@4012e000 { + compatible = "ti,omap4-dmic"; + reg = <0x4012e000 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <0 114 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "dmic"; + }; + mcbsp1: mcbsp@40122000 { compatible = "ti,omap4-mcbsp"; reg = <0x40122000 0xff>, /* MPU private access */ -- cgit v1.2.1 From 2c195f9cebeb03f7fb10ede6aeca5ce3ce6ed350 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 29 Aug 2012 16:31:05 +0300 Subject: ARM: dts: omap3-beagle: Enable audio support Add the needed sections to enable audio support on BeagleBoard when booted with DT blob. Signed-off-by: Peter Ujfalusi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-beagle.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index ca46fb2b5803..a9d98d5ade9a 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -37,6 +37,14 @@ linux,default-trigger = "mmc0"; }; }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; }; &i2c1 { @@ -52,6 +60,12 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; }; }; -- cgit v1.2.1 From 5d83cb86227baf87ab04a646d60fb8b26b880743 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 27 Aug 2012 16:59:08 +0530 Subject: ARM: dts: AM33XX: Convert all hex numbers to lower-case To make it consistent, convert all hex number presentation to lower-case from all am33xx specific nodes. Signed-off-by: Vaibhav Hiremath Cc: Tony Lindgren Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am335x-bone.dts | 4 ++-- arch/arm/boot/dts/am335x-evm.dts | 8 ++++---- arch/arm/boot/dts/am33xx.dtsi | 20 ++++++++++---------- 3 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 917e7843bee7..c634f87e230e 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -19,11 +19,11 @@ }; ocp { - uart1: serial@44E09000 { + uart1: serial@44e09000 { status = "okay"; }; - i2c1: i2c@44E0B000 { + i2c1: i2c@44e0b000 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 9fcbacdb8f38..185d6325a458 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -19,16 +19,16 @@ }; ocp { - uart1: serial@44E09000 { + uart1: serial@44e09000 { status = "okay"; }; - i2c1: i2c@44E0B000 { + i2c1: i2c@44e0b000 { status = "okay"; clock-frequency = <400000>; - tps: tps@2D { - reg = <0x2D>; + tps: tps@2d { + reg = <0x2d>; }; }; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index dde76f7e81a8..be435117f5dd 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -71,7 +71,7 @@ #interrupt-cells = <1>; }; - gpio2: gpio@4804C000 { + gpio2: gpio@4804c000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio2"; gpio-controller; @@ -80,7 +80,7 @@ #interrupt-cells = <1>; }; - gpio3: gpio@481AC000 { + gpio3: gpio@481ac000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio3"; gpio-controller; @@ -89,7 +89,7 @@ #interrupt-cells = <1>; }; - gpio4: gpio@481AE000 { + gpio4: gpio@481ae000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio4"; gpio-controller; @@ -98,7 +98,7 @@ #interrupt-cells = <1>; }; - uart1: serial@44E09000 { + uart1: serial@44e09000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; @@ -119,28 +119,28 @@ status = "disabled"; }; - uart4: serial@481A6000 { + uart4: serial@481a6000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; }; - uart5: serial@481A8000 { + uart5: serial@481a8000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; }; - uart6: serial@481AA000 { + uart6: serial@481aa000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; }; - i2c1: i2c@44E0B000 { + i2c1: i2c@44e0b000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -148,7 +148,7 @@ status = "disabled"; }; - i2c2: i2c@4802A000 { + i2c2: i2c@4802a000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -156,7 +156,7 @@ status = "disabled"; }; - i2c3: i2c@4819C000 { + i2c3: i2c@4819c000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.1 From 4462b31cf416e74e54a37b57de7177cc4d244699 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 27 Aug 2012 17:21:01 +0530 Subject: ARM: dts: AM33XX: Specify reg and interrupt property for all nodes The device/node resources (like, IORESOURCE_MEM and IORESOURCE_IRQ) are overwritten by hwmod resources, due to all known reasons but that should not be the reason for not providing all the information in the DTS blob. Ideally we should use DTS resource and use HWMOD framework wherever required and for only specific things. Newer platforms like, OMAP5 and AM33XX, we only support DT boot mode, so this patch is preparation for the future where we supposed to get rid of hwmod dependency anyway. Signed-off-by: Vaibhav Hiremath Cc: Tony Lindgren Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/am33xx.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index be435117f5dd..bb31bff01998 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -69,6 +69,9 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x44e07000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <96>; }; gpio2: gpio@4804c000 { @@ -78,6 +81,9 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x4804c000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <98>; }; gpio3: gpio@481ac000 { @@ -87,6 +93,9 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x481ac000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <32>; }; gpio4: gpio@481ae000 { @@ -96,12 +105,18 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; + reg = <0x481ae000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <62>; }; uart1: serial@44e09000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; + reg = <0x44e09000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <72>; status = "disabled"; }; @@ -109,6 +124,9 @@ compatible = "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; + reg = <0x48022000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <73>; status = "disabled"; }; @@ -116,6 +134,9 @@ compatible = "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; + reg = <0x48024000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <74>; status = "disabled"; }; @@ -123,6 +144,9 @@ compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; + reg = <0x481a6000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <44>; status = "disabled"; }; @@ -130,6 +154,9 @@ compatible = "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; + reg = <0x481a8000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <45>; status = "disabled"; }; @@ -137,6 +164,9 @@ compatible = "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; + reg = <0x481aa000 0x2000>; + interrupt-parent = <&intc>; + interrupts = <46>; status = "disabled"; }; @@ -145,6 +175,9 @@ #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; + reg = <0x44e0b000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <70>; status = "disabled"; }; @@ -153,6 +186,9 @@ #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; + reg = <0x4802a000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <71>; status = "disabled"; }; @@ -161,12 +197,18 @@ #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; + reg = <0x4819c000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <30>; status = "disabled"; }; wdt2: wdt@44e35000 { compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; + reg = <0x44e35000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <91>; }; }; }; -- cgit v1.2.1 From 48420dbcf2168004f8a5ed9f1ecd2d877dc798da Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 5 Sep 2012 11:38:23 +0200 Subject: ARM: dts: OMAP4: Add reg and interrupts for every nodes Thanks to Vaibhav omap_device fix (ARM: OMAP: omap_device: Fix up resource names when booted with devicetre), we can now specify reg and interrupts using standard device tree attributes. Update the OMAP4 dtsi file with missing reg and interrupts attributes. Signed-off-by: Benoit Cousson Cc: Santosh Shilimkar Cc: Tony Lindgren Cc: Felipe Balbi Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap4.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 9f851dfe7507..75095e306d77 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -97,6 +97,8 @@ gpio1: gpio@4a310000 { compatible = "ti,omap4-gpio"; + reg = <0x4a310000 0x200>; + interrupts = <0 29 0x4>; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; @@ -106,6 +108,8 @@ gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; + reg = <0x48055000 0x200>; + interrupts = <0 30 0x4>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; @@ -115,6 +119,8 @@ gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; + reg = <0x48057000 0x200>; + interrupts = <0 31 0x4>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; @@ -124,6 +130,8 @@ gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; + reg = <0x48059000 0x200>; + interrupts = <0 32 0x4>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; @@ -133,6 +141,8 @@ gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; + reg = <0x4805b000 0x200>; + interrupts = <0 33 0x4>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; @@ -142,6 +152,8 @@ gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; + reg = <0x4805d000 0x200>; + interrupts = <0 34 0x4>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; @@ -151,30 +163,40 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; + reg = <0x4806a000 0x100>; + interrupts = <0 72 0x4>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; + reg = <0x4806c000 0x100>; + interrupts = <0 73 0x4>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; + reg = <0x48020000 0x100>; + interrupts = <0 74 0x4>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; + reg = <0x4806e000 0x100>; + interrupts = <0 70 0x4>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; + reg = <0x48070000 0x100>; + interrupts = <0 56 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -182,6 +204,8 @@ i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; + reg = <0x48072000 0x100>; + interrupts = <0 57 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -189,6 +213,8 @@ i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; + reg = <0x48060000 0x100>; + interrupts = <0 61 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -196,6 +222,8 @@ i2c4: i2c@48350000 { compatible = "ti,omap4-i2c"; + reg = <0x48350000 0x100>; + interrupts = <0 62 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; @@ -203,6 +231,8 @@ mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; + reg = <0x48098000 0x200>; + interrupts = <0 65 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; @@ -211,6 +241,8 @@ mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; + reg = <0x4809a000 0x200>; + interrupts = <0 66 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; @@ -219,6 +251,8 @@ mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; + reg = <0x480b8000 0x200>; + interrupts = <0 91 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; @@ -227,6 +261,8 @@ mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; + reg = <0x480ba000 0x200>; + interrupts = <0 48 0x4>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; @@ -235,6 +271,8 @@ mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; + reg = <0x4809c000 0x400>; + interrupts = <0 83 0x4>; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; @@ -242,30 +280,40 @@ mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480b4000 0x400>; + interrupts = <0 86 0x4>; ti,hwmods = "mmc2"; ti,needs-special-reset; }; mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480ad000 0x400>; + interrupts = <0 94 0x4>; ti,hwmods = "mmc3"; ti,needs-special-reset; }; mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d1000 0x400>; + interrupts = <0 96 0x4>; ti,hwmods = "mmc4"; ti,needs-special-reset; }; mmc5: mmc@480d5000 { compatible = "ti,omap4-hsmmc"; + reg = <0x480d5000 0x400>; + interrupts = <0 59 0x4>; ti,hwmods = "mmc5"; ti,needs-special-reset; }; wdt2: wdt@4a314000 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x4a314000 0x80>; + interrupts = <0 80 0x4>; ti,hwmods = "wd_timer2"; }; @@ -338,11 +386,16 @@ keypad: keypad@4a31c000 { compatible = "ti,omap4-keypad"; + reg = <0x4a31c000 0x80>; + interrupts = <0 120 0x4>; + reg-names = "mpu"; ti,hwmods = "kbd"; }; emif1: emif@4c000000 { compatible = "ti,emif-4d"; + reg = <0x4c000000 0x100>; + interrupts = <0 110 0x4>; ti,hwmods = "emif1"; phy-type = <1>; hw-caps-read-idle-ctrl; @@ -352,6 +405,8 @@ emif2: emif@4d000000 { compatible = "ti,emif-4d"; + reg = <0x4d000000 0x100>; + interrupts = <0 111 0x4>; ti,hwmods = "emif2"; phy-type = <1>; hw-caps-read-idle-ctrl; -- cgit v1.2.1 From aaca483f765e32325f2539333c628be68a34d893 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Sat, 8 Sep 2012 10:09:03 +0900 Subject: ARM: dts: Use active low flag for gpio-keys on Origen Commit f447ed8b31d ("gpio: samsung: add flags specifier to device-tree binding") adds a flag to represent active low state for gpio line. Since gpio-keys on Origen board are active low, using this flag to represent the same. Signed-off-by: Sachin Kamat Reviewed-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-origen.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 0c49caa09978..c37edf094adf 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -62,31 +62,31 @@ up { label = "Up"; - gpios = <&gpx2 0 0 0 2>; + gpios = <&gpx2 0 0 0x10000 2>; linux,code = <103>; }; down { label = "Down"; - gpios = <&gpx2 1 0 0 2>; + gpios = <&gpx2 1 0 0x10000 2>; linux,code = <108>; }; back { label = "Back"; - gpios = <&gpx1 7 0 0 2>; + gpios = <&gpx1 7 0 0x10000 2>; linux,code = <158>; }; home { label = "Home"; - gpios = <&gpx1 6 0 0 2>; + gpios = <&gpx1 6 0 0x10000 2>; linux,code = <102>; }; menu { label = "Menu"; - gpios = <&gpx1 5 0 0 2>; + gpios = <&gpx1 5 0 0x10000 2>; linux,code = <139>; }; }; -- cgit v1.2.1 From 162b172ddd7aacc754253f97b1b1ee75344bc22c Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Sat, 8 Sep 2012 10:09:03 +0900 Subject: ARM: dts: Add heartbeat gpio-leds support to Origen Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-origen.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index c37edf094adf..d69a7999a12b 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -91,6 +91,14 @@ }; }; + leds { + compatible = "gpio-leds"; + status { + gpios = <&gpx1 3 0 0x10000 2>; + linux,default-trigger = "heartbeat"; + }; + }; + keypad@100A0000 { status = "disabled"; }; -- cgit v1.2.1 From bc7fedad82deb398f440b875f54dc81f931a71e3 Mon Sep 17 00:00:00 2001 From: Florian Vaussard Date: Fri, 31 Aug 2012 18:06:11 +0200 Subject: ARM: dts: OMAP3: Add support for Gumstix Overo with Tobi expansion board The Gumstix Overo is a computer on module using an OMAP3 processor. This module must be plugged into an expansion board. This patch adds a first device tree support for the Overo, using the Tobi expansion board. The current support is able to boot and mount the rootfs from MMC. This patche also updates the omap3 dtb build target. Currently working: - mmc0 (on board microSD) - i2c0 and i2c2 (i2c1 not used) - led on GPIO Signed-off-by: Florian Vaussard Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-overo.dtsi | 42 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap3-tobi.dts | 35 +++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 arch/arm/boot/dts/omap3-overo.dtsi create mode 100644 arch/arm/boot/dts/omap3-tobi.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi new file mode 100644 index 000000000000..d6cc5e2671e7 --- /dev/null +++ b/arch/arm/boot/dts/omap3-overo.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * The Gumstix Overo must be combined with an expansion board. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/include/ "twl4030.dtsi" + +/* i2c2 pins are used for gpio */ +&i2c2 { + status = "disabled"; +}; + +/* on board microSD slot */ +&mmc1 { + vmmc-supply = <&vmmc1>; + bus-width = <4>; +}; + +/* optional on board WiFi */ +&mmc2 { + bus-width = <4>; +}; diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts new file mode 100644 index 000000000000..a13d12de77ff --- /dev/null +++ b/arch/arm/boot/dts/omap3-tobi.dts @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Tobi expansion board is manufactured by Gumstix Inc. + */ + +/include/ "omap3-overo.dtsi" + +/ { + model = "TI OMAP3 Gumstix Overo on Tobi"; + compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "overo:red:gpio21"; + gpios = <&gpio1 21 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&mmc3 { + status = "disabled"; +}; -- cgit v1.2.1 From a135f2f82c64fa779adbc19b41e21039a258a6a4 Mon Sep 17 00:00:00 2001 From: Florian Vaussard Date: Mon, 10 Sep 2012 15:16:36 +0200 Subject: ARM: dts: omap3-overo: Add support for the blue LED Support the blue LED connected to the LEDB pin of the TWL4030 on the Gumstix Overo. Signed-off-by: Florian Vaussard Signed-off-by: Benoit Cousson --- arch/arm/boot/dts/omap3-overo.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi index d6cc5e2671e7..89808ce01673 100644 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ b/arch/arm/boot/dts/omap3-overo.dtsi @@ -13,6 +13,17 @@ /include/ "omap3.dtsi" +/ { + leds { + compatible = "gpio-leds"; + overo { + label = "overo:blue:COM"; + gpios = <&twl_gpio 19 0>; + linux,default-trigger = "mmc0"; + }; + }; +}; + &i2c1 { clock-frequency = <2600000>; @@ -40,3 +51,7 @@ &mmc2 { bus-width = <4>; }; + +&twl_gpio { + ti,use-leds; +}; -- cgit v1.2.1 From 642f12b4c7505943a6f50101d5b087a74fd9ae72 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 10 Sep 2012 10:20:44 -0700 Subject: arm/dts: Add omap36xx.dtsi file and rename omap3-beagle to omap3-beagle-xm The extra serial port is not available on 34xx. And the current omap3-beagle.dts file is for omap3-beagle-xm.dts as it lists 512MB of memory. Please somebody submit a new omap3-beagle.dts for the original 34xx BeagleBoard after testing it properly. Cc: Benoit Cousson Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-beagle-xm.dts | 115 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap3-beagle.dts | 115 ---------------------------------- arch/arm/boot/dts/omap3.dtsi | 7 --- arch/arm/boot/dts/omap36xx.dtsi | 25 ++++++++ 4 files changed, 140 insertions(+), 122 deletions(-) create mode 100644 arch/arm/boot/dts/omap3-beagle-xm.dts delete mode 100644 arch/arm/boot/dts/omap3-beagle.dts create mode 100644 arch/arm/boot/dts/omap36xx.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts new file mode 100644 index 000000000000..c38cf76df81f --- /dev/null +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap36xx.dtsi" + +/ { + model = "TI OMAP3 BeagleBoard xM"; + compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + leds { + compatible = "gpio-leds"; + pmu_stat { + label = "beagleboard::pmu_stat"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + }; + + heartbeat { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + vsim: regulator-vsim { + compatible = "ti,twl4030-vsim"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +/include/ "twl4030.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <100000>; + + /* + * Display monitor features are burnt in the EEPROM + * as EDID data. + */ + eeprom@50 { + compatible = "ti,eeprom"; + reg = <0x50>; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts deleted file mode 100644 index a9d98d5ade9a..000000000000 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "omap3.dtsi" - -/ { - model = "TI OMAP3 BeagleBoard"; - compatible = "ti,omap3-beagle", "ti,omap3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - leds { - compatible = "gpio-leds"; - pmu_stat { - label = "beagleboard::pmu_stat"; - gpios = <&twl_gpio 19 0>; /* LEDB */ - }; - - heartbeat { - label = "beagleboard::usr0"; - gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "beagleboard::usr1"; - gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ - linux,default-trigger = "mmc0"; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - vsim: regulator-vsim { - compatible = "ti,twl4030-vsim"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -/include/ "twl4030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index f024bb3034a6..05c26c4f6606 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -17,7 +17,6 @@ serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; - serial3 = &uart4; }; cpus { @@ -141,12 +140,6 @@ clock-frequency = <48000000>; }; - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - i2c1: i2c@48070000 { compatible = "ti,omap3-i2c"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi new file mode 100644 index 000000000000..96bf0287cb9f --- /dev/null +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -0,0 +1,25 @@ +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap3.dtsi" + +/ { + aliases { + serial3 = &uart4; + }; + + ocp { + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + }; +}; -- cgit v1.2.1 From 679e33104dbf9b78d88b812fc3c1ac88536d24bf Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 10 Sep 2012 10:34:51 -0700 Subject: arm/dts: Add pinctrl driver entries for omap2/3/4 Add pinctrl driver entries for omap2+. These all use the generic pinctrl-single driver for the padconf registers. Cc: devicetree-discuss@lists.ozlabs.org Acked-by: Linus Walleij [tony@atomide.com: updated to drop omap2420.dtsi rename changes] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2420.dtsi | 9 +++++++++ arch/arm/boot/dts/omap2430.dtsi | 9 +++++++++ arch/arm/boot/dts/omap3.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/omap4.dtsi | 17 +++++++++++++++++ 4 files changed, 53 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 6174d3d93b1f..bfd76b4a0ddc 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -14,6 +14,15 @@ compatible = "ti,omap2420", "ti,omap2"; ocp { + omap2420_pmx: pinmux@48000030 { + compatible = "ti,omap2420-padconf", "pinctrl-single"; + reg = <0x48000030 0x0113>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + mcbsp1: mcbsp@48074000 { compatible = "ti,omap2420-mcbsp"; reg = <0x48074000 0xff>; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 59a639a33794..4565d9750f4d 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -14,6 +14,15 @@ compatible = "ti,omap2430", "ti,omap2"; ocp { + omap2430_pmx: pinmux@49002030 { + compatible = "ti,omap2430-padconf", "pinctrl-single"; + reg = <0x49002030 0x0154>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + mcbsp1: mcbsp@48074000 { compatible = "ti,omap2430-mcbsp"; reg = <0x48074000 0xff>; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 05c26c4f6606..f38ea8771b44 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -68,6 +68,24 @@ reg = <0x48200000 0x1000>; }; + omap3_pmx_core: pinmux@48002030 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x48002030 0x05cc>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap3_pmx_wkup: pinmux@0x48002a58 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x48002a58 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + gpio1: gpio@48310000 { compatible = "ti,omap3-gpio"; ti,hwmods = "gpio1"; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 75095e306d77..5d1c48459e6e 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -95,6 +95,23 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; + omap4_pmx_core: pinmux@4a100040 { + compatible = "ti,omap4-padconf", "pinctrl-single"; + reg = <0x4a100040 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + omap4_pmx_wkup: pinmux@4a31e040 { + compatible = "ti,omap4-padconf", "pinctrl-single"; + reg = <0x4a31e040 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + gpio1: gpio@4a310000 { compatible = "ti,omap4-gpio"; reg = <0x4a310000 0x200>; -- cgit v1.2.1 From 26638c667e645de368cd68cade716ed0faef6269 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 10 Sep 2012 10:34:52 -0700 Subject: arm/dts: Mux uart pins for omap4-sdp Mux uart pins for the serial ports. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-sdp.dts | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 7e83a61de0b2..94a23b39033d 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -116,6 +116,33 @@ }; }; +&omap4_pmx_core { + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */ + 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */ + 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */ + 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */ + 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */ + 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */ + 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */ + 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */ + >; + }; +}; + &i2c1 { clock-frequency = <400000>; @@ -307,3 +334,18 @@ 0x0707006c>; /* KEY_DOWN */ linux,input-no-autorepeat; }; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; +}; -- cgit v1.2.1 From 13b4569bbbcf58891727138b84b8db5ea4178d32 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 10 Sep 2012 22:35:41 +0200 Subject: ARM: dts: cfa10049: Add the 74HC595 gpio expanders Add the two daisy-chains of 74hc595s shift registers available on the CFA-10049. Signed-off-by: Maxime Ripard Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-cfa10049.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 1f7fa50414b6..05c892e931e3 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -27,6 +27,8 @@ fsl,pinmux-ids = < 0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */ 0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */ + 0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */ + 0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */ >; fsl,drive-strength = <1>; fsl,voltage = <1>; @@ -39,6 +41,25 @@ pinctrl-names = "default"; pinctrl-0 = <&spi3_pins_cfa10049>; status = "okay"; + + gpio5: gpio5@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <2>; + spi-max-frequency = <100000>; + }; + + gpio6: gpio6@1 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <1>; + registers-number = <4>; + spi-max-frequency = <100000>; + }; + }; }; -- cgit v1.2.1 From b598b9f311a604ca533033baa5afcf45beb037d9 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 22 Aug 2012 21:36:29 +0800 Subject: clk: mxs: replace imx28 clk_register_clkdev with clock DT lookup It really becomes a maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx28 client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 96fe74e4935c..03e0fef8e7a7 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -65,6 +65,7 @@ dma-apbh@80004000 { compatible = "fsl,imx28-dma-apbh"; reg = <0x80004000 0x2000>; + clocks = <&clks 25>; }; perfmon@80006000 { @@ -81,6 +82,7 @@ reg-names = "gpmi-nand", "bch"; interrupts = <88>, <41>; interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 50>; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -90,6 +92,7 @@ #size-cells = <0>; reg = <0x80010000 0x2000>; interrupts = <96 82>; + clocks = <&clks 46>; fsl,ssp-dma-channel = <0>; status = "disabled"; }; @@ -99,6 +102,7 @@ #size-cells = <0>; reg = <0x80012000 0x2000>; interrupts = <97 83>; + clocks = <&clks 47>; fsl,ssp-dma-channel = <1>; status = "disabled"; }; @@ -108,6 +112,7 @@ #size-cells = <0>; reg = <0x80014000 0x2000>; interrupts = <98 84>; + clocks = <&clks 48>; fsl,ssp-dma-channel = <2>; status = "disabled"; }; @@ -117,6 +122,7 @@ #size-cells = <0>; reg = <0x80016000 0x2000>; interrupts = <99 85>; + clocks = <&clks 49>; fsl,ssp-dma-channel = <3>; status = "disabled"; }; @@ -606,6 +612,7 @@ dma-apbx@80024000 { compatible = "fsl,imx28-dma-apbx"; reg = <0x80024000 0x2000>; + clocks = <&clks 26>; }; dcp@80028000 { @@ -634,6 +641,7 @@ compatible = "fsl,imx28-lcdif"; reg = <0x80030000 0x2000>; interrupts = <38 86>; + clocks = <&clks 55>; status = "disabled"; }; @@ -641,6 +649,8 @@ compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80032000 0x2000>; interrupts = <8>; + clocks = <&clks 58>, <&clks 58>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -648,6 +658,8 @@ compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80034000 0x2000>; interrupts = <9>; + clocks = <&clks 59>, <&clks 59>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -694,15 +706,17 @@ reg = <0x80040000 0x40000>; ranges; - clkctl@80040000 { + clks: clkctrl@80040000 { + compatible = "fsl,imx28-clkctrl"; reg = <0x80040000 0x2000>; - status = "disabled"; + #clock-cells = <1>; }; saif0: saif@80042000 { compatible = "fsl,imx28-saif"; reg = <0x80042000 0x2000>; interrupts = <59 80>; + clocks = <&clks 53>; fsl,saif-dma-channel = <4>; status = "disabled"; }; @@ -716,6 +730,7 @@ compatible = "fsl,imx28-saif"; reg = <0x80046000 0x2000>; interrupts = <58 81>; + clocks = <&clks 54>; fsl,saif-dma-channel = <5>; status = "disabled"; }; @@ -763,6 +778,7 @@ pwm: pwm@80064000 { compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; reg = <0x80064000 0x2000>; + clocks = <&clks 44>; #pwm-cells = <2>; fsl,pwm-number = <8>; status = "disabled"; @@ -777,6 +793,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; interrupts = <112 70 71>; + clocks = <&clks 45>; status = "disabled"; }; @@ -784,6 +801,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <113 72 73>; + clocks = <&clks 45>; status = "disabled"; }; @@ -791,6 +809,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <114 74 75>; + clocks = <&clks 45>; status = "disabled"; }; @@ -798,6 +817,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80070000 0x2000>; interrupts = <115 76 77>; + clocks = <&clks 45>; status = "disabled"; }; @@ -805,6 +825,7 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80072000 0x2000>; interrupts = <116 78 79>; + clocks = <&clks 45>; status = "disabled"; }; @@ -812,18 +833,22 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x80074000 0x1000>; interrupts = <47>; + clocks = <&clks 45>, <&clks 26>; + clock-names = "uart", "apb_pclk"; status = "disabled"; }; usbphy0: usbphy@8007c000 { compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007c000 0x2000>; + clocks = <&clks 62>; status = "disabled"; }; usbphy1: usbphy@8007e000 { compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007e000 0x2000>; + clocks = <&clks 63>; status = "disabled"; }; }; @@ -840,6 +865,7 @@ compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80080000 0x10000>; interrupts = <93>; + clocks = <&clks 60>; fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -848,6 +874,7 @@ compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80090000 0x10000>; interrupts = <92>; + clocks = <&clks 61>; fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -861,6 +888,8 @@ compatible = "fsl,imx28-fec"; reg = <0x800f0000 0x4000>; interrupts = <101>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; status = "disabled"; }; @@ -868,6 +897,8 @@ compatible = "fsl,imx28-fec"; reg = <0x800f4000 0x4000>; interrupts = <102>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; status = "disabled"; }; -- cgit v1.2.1 From 53f9443da63db38212e784b0aa205881168757aa Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 22 Aug 2012 21:36:30 +0800 Subject: clk: mxs: replace imx23 clk_register_clkdev with clock DT lookup It really becomes a maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx23 client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index b00f3cfb3bf8..9d0e803e3eca 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -52,6 +52,7 @@ dma-apbh@80004000 { compatible = "fsl,imx23-dma-apbh"; reg = <0x80004000 0x2000>; + clocks = <&clks 15>; }; ecc@80008000 { @@ -67,6 +68,7 @@ reg-names = "gpmi-nand", "bch"; interrupts = <13>, <56>; interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 34>; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -74,6 +76,7 @@ ssp0: ssp@80010000 { reg = <0x80010000 0x2000>; interrupts = <15 14>; + clocks = <&clks 33>; fsl,ssp-dma-channel = <1>; status = "disabled"; }; @@ -290,6 +293,7 @@ dma-apbx@80024000 { compatible = "fsl,imx23-dma-apbx"; reg = <0x80024000 0x2000>; + clocks = <&clks 16>; }; dcp@80028000 { @@ -316,12 +320,14 @@ compatible = "fsl,imx23-lcdif"; reg = <0x80030000 2000>; interrupts = <46 45>; + clocks = <&clks 38>; status = "disabled"; }; ssp1: ssp@80034000 { reg = <0x80034000 0x2000>; interrupts = <2 20>; + clocks = <&clks 33>; fsl,ssp-dma-channel = <2>; status = "disabled"; }; @@ -339,9 +345,10 @@ reg = <0x80040000 0x40000>; ranges; - clkctl@80040000 { + clks: clkctrl@80040000 { + compatible = "fsl,imx23-clkctrl"; reg = <0x80040000 0x2000>; - status = "disabled"; + #clock-cells = <1>; }; saif0: saif@80042000 { @@ -393,6 +400,7 @@ pwm: pwm@80064000 { compatible = "fsl,imx23-pwm"; reg = <0x80064000 0x2000>; + clocks = <&clks 30>; #pwm-cells = <2>; fsl,pwm-number = <5>; status = "disabled"; @@ -407,6 +415,7 @@ compatible = "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <24 25 23>; + clocks = <&clks 32>; status = "disabled"; }; @@ -414,6 +423,7 @@ compatible = "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <59 60 58>; + clocks = <&clks 32>; status = "disabled"; }; @@ -421,6 +431,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x80070000 0x2000>; interrupts = <0>; + clocks = <&clks 32>, <&clks 16>; + clock-names = "uart", "apb_pclk"; status = "disabled"; }; -- cgit v1.2.1 From 44a509fc4794c8a072c83be030579024beb037c9 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 10 Aug 2012 17:17:56 +0800 Subject: ARM: dts: imx6q: improve indentation for fsl,pins Change the indentation for property fsl,pins a little bit, so that the first and the last line get the same indentation with all other lines. Then it will be easier to copy and past any of these lines. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 8 +-- arch/arm/boot/dts/imx6q.dtsi | 114 +++++++++++++++++++--------------- 2 files changed, 68 insertions(+), 54 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 72f30f3e6171..505235fcfd58 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -51,10 +51,10 @@ gpios { pinctrl_gpio_hog: gpiohog { fsl,pins = < - 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ - 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ - 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ - >; + 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ + 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ + >; }; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index a8cd96eed298..e12c27f93795 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -513,86 +513,100 @@ /* shared pinctrl settings */ audmux { pinctrl_audmux_1: audmux-1 { - fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ - 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ - 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ - 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ + fsl,pins = < + 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ + 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ + 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ + 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ + >; }; }; gpmi-nand { pinctrl_gpmi_nand_1: gpmi-nand-1 { - fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ - 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ - 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ - 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ - 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ - 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ - 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ - 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ - 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ - 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ - 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ - 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ - 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ - 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ - 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ - 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ - 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ - 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ - 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + fsl,pins = < + 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + >; }; }; i2c1 { pinctrl_i2c1_1: i2c1grp-1 { - fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ - 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */ + fsl,pins = < + 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ + 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ + >; }; }; serial2 { pinctrl_serial2_1: serial2grp-1 { - fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ - 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */ + fsl,pins = < + 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ + 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ + >; }; }; usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { - fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ - 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ - 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ - 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ - 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ - 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ - 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ - 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ - 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ - 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ + fsl,pins = < + 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ + 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ + 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ + 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ + 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ + >; }; }; usdhc4 { pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ + fsl,pins = < + 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ + 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ + 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ + 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ + 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ + >; }; }; ecspi1 { pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ - 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ - 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + fsl,pins = < + 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + >; }; }; }; -- cgit v1.2.1 From e30ba89fdf3891c3ff32d25a73fbffd37e893572 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 11 Aug 2012 12:33:51 +0800 Subject: ARM: dts: imx6q: name iomuxc sub-nodes following pin function Name iomuxc sub-nodes following pin function and hardware manual. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 2 +- arch/arm/boot/dts/imx6q.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 505235fcfd58..dc1933c73067 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -99,7 +99,7 @@ uart2: serial@021e8000 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial2_1>; + pinctrl-0 = <&pinctrl_uart2_1>; }; i2c@021a0000 { /* I2C1 */ diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e12c27f93795..d5ced4614016 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -557,8 +557,8 @@ }; }; - serial2 { - pinctrl_serial2_1: serial2grp-1 { + uart2 { + pinctrl_uart2_1: uart2grp-1 { fsl,pins = < 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ -- cgit v1.2.1 From 52ccd4920301b9fecbac577ad4283995730ecf76 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 11 Aug 2012 11:17:42 +0800 Subject: ARM: dts: imx6q: sort iomuxc sub-nodes in name Sort iomuxc sub-nodes in name so that the node can be located a little bit easier. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index d5ced4614016..5612ccf2a563 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -522,6 +522,16 @@ }; }; + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + >; + }; + }; + gpmi-nand { pinctrl_gpmi_nand_1: gpmi-nand-1 { fsl,pins = < @@ -599,16 +609,6 @@ >; }; }; - - ecspi1 { - pinctrl_ecspi1_1: ecspi1grp-1 { - fsl,pins = < - 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ - 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ - 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ - >; - }; - }; }; dcic@020e4000 { /* DCIC1 */ -- cgit v1.2.1 From 99d5f0cc17c0c7191e1bb9dc40849a1711a77439 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 11 Aug 2012 10:47:14 +0800 Subject: ARM: dts: imx6q-sabrelite: add pinctrl for usdhc and enet Add missing pinctrl of usdhc and enet for imx6q-sabrelite board. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 13 ++++++++++- arch/arm/boot/dts/imx6q.dtsi | 44 +++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index dc1933c73067..e34ace784ea3 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -51,8 +51,13 @@ gpios { pinctrl_gpio_hog: gpiohog { fsl,pins = < - 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ + 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ + 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ + 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ + 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ >; }; @@ -71,12 +76,16 @@ }; ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 0>; status = "okay"; }; usdhc@02198000 { /* uSDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_2>; cd-gpios = <&gpio7 0 0>; wp-gpios = <&gpio7 1 0>; vmmc-supply = <®_3p3v>; @@ -84,6 +93,8 @@ }; usdhc@0219c000 { /* uSDHC4 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_2>; cd-gpios = <&gpio2 6 0>; wp-gpios = <&gpio2 7 0>; vmmc-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 5612ccf2a563..9d180220212a 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -532,6 +532,28 @@ }; }; + enet { + pinctrl_enet_1: enetgrp-1 { + fsl,pins = < + 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ + 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ + 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + >; + }; + }; + gpmi-nand { pinctrl_gpmi_nand_1: gpmi-nand-1 { fsl,pins = < @@ -591,6 +613,17 @@ 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ >; }; + + pinctrl_usdhc3_2: usdhc3grp-2 { + fsl,pins = < + 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ + >; + }; }; usdhc4 { @@ -608,6 +641,17 @@ 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ >; }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ + >; + }; }; }; -- cgit v1.2.1 From 9e3c00665d915c4f5645d43aec5a943b5eee55de Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 11 Aug 2012 12:49:11 +0800 Subject: ARM: dts: imx6q-arm2: add pinctrl for uart and enet Add missing pinctrl of uart and enet for imx6q-arm2 board. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-arm2.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 29 +++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index d792581672cc..15df4c105e89 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -28,8 +28,27 @@ status = "disabled"; /* gpmi nand conflicts with SD */ }; + aips-bus@02000000 { /* AIPS1 */ + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ + 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ + 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ + >; + }; + }; + }; + }; + aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_2>; phy-mode = "rgmii"; status = "okay"; }; @@ -52,6 +71,8 @@ }; uart4: serial@021f0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_1>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 9d180220212a..f6c99f722f4c 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -552,6 +552,26 @@ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ >; }; + + pinctrl_enet_2: enetgrp-2 { + fsl,pins = < + 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ + 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ + 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + >; + }; }; gpmi-nand { @@ -598,6 +618,15 @@ }; }; + uart4 { + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ + 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ + >; + }; + }; + usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { fsl,pins = < -- cgit v1.2.1 From 497ae1747b8c52fde4ab7e9987326ca43886b652 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sat, 11 Aug 2012 22:06:26 +0800 Subject: ARM: dts: imx6q-sabresd: add pinctrl settings Add pinctrl settings for existing devices in imx6q-sabresd.dts. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabresd.dts | 25 ++++++++++++++++++++++++- arch/arm/boot/dts/imx6q.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 07509a181178..e596c28c214d 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts @@ -22,28 +22,51 @@ }; soc { - aips-bus@02000000 { /* AIPS1 */ spba-bus@02000000 { uart1: serial@02020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; + + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ + 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ + 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ + 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ + >; + }; + }; + }; }; aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; phy-mode = "rgmii"; status = "okay"; }; usdhc@02194000 { /* uSDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; cd-gpios = <&gpio2 2 0>; wp-gpios = <&gpio2 3 0>; status = "okay"; }; usdhc@02198000 { /* uSDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; cd-gpios = <&gpio2 0 0>; wp-gpios = <&gpio2 1 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index f6c99f722f4c..1d07be2530b5 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -609,6 +609,15 @@ }; }; + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ + 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ + >; + }; + }; + uart2 { pinctrl_uart2_1: uart2grp-1 { fsl,pins = < @@ -627,6 +636,23 @@ }; }; + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ + 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ + 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ + 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ + 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ + 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ + 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ + 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ + 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ + 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ + >; + }; + }; + usdhc3 { pinctrl_usdhc3_1: usdhc3grp-1 { fsl,pins = < -- cgit v1.2.1 From 5be03a7bdb0f7411465eb90b3b670e99e1aefbe5 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 12 Aug 2012 20:02:10 +0800 Subject: ARM: dts: imx53-qsb: add pinctrl settings Add pinctrl settings for existing devices in imx53-qsb.dts. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-qsb.dts | 34 +++++++++++++++- arch/arm/boot/dts/imx53.dtsi | 90 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index a0e816f2182b..08948af86d1a 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts @@ -25,6 +25,8 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; status = "okay"; }; @@ -35,6 +37,8 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; cd-gpios = <&gpio3 11 0>; wp-gpios = <&gpio3 12 0>; status = "okay"; @@ -42,17 +46,37 @@ }; iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-qsb"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */ + 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */ + 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ + 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ + 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ + 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; sgtl5000: codec@0a { @@ -64,6 +88,8 @@ }; i2c@63fc8000 { /* I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; status = "okay"; accelerometer: mma8450@1c { @@ -150,10 +176,14 @@ }; audmux@63fd0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; status = "okay"; }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 776ce410d057..01fa49abab6d 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -216,6 +216,96 @@ status = "disabled"; }; + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ + 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ + 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ + 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ + 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ + 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ + 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ + 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ + 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ + 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ + 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ + 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ + 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ + 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ + 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ + 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ + 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ + 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ + >; + }; + }; + + esdhc3 { + pinctrl_esdhc3_1: esdhc3grp-1 { + fsl,pins = < + 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ + 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ + 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ + 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ + 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ + 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ + 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ + 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ + 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ + 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ + 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ + 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ + 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ + >; + }; + }; + }; + uart1: serial@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; -- cgit v1.2.1 From 4bb6143cbee3c66c23a3f259b5e479608bed0831 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Thu, 2 Aug 2012 22:48:39 +0800 Subject: ARM: dts: imx53-ard: add pinctrl settings Add pinctrl settings for the exsiting devices in imx53-ard.dts. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ard.dts | 49 +++++++++++++++++++++++++++++++++++++++-- arch/arm/boot/dts/imx53.dtsi | 22 ++++++++++++++++++ 2 files changed, 69 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index e6a189096017..4be76f223526 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -25,6 +25,8 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_2>; cd-gpios = <&gpio1 1 0>; wp-gpios = <&gpio1 9 0>; status = "okay"; @@ -32,11 +34,54 @@ }; iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-ard"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */ + 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */ + 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */ + 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */ + 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */ + 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */ + 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */ + 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */ + 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */ + 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */ + 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */ + 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */ + 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */ + 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */ + 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */ + 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */ + 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */ + 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */ + 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */ + 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */ + 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */ + 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */ + 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */ + 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */ + 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */ + 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */ + 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */ + 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */ + 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */ + 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */ + 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */ + 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */ + 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */ + 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 01fa49abab6d..20b67bc5f70b 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -259,6 +259,21 @@ 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ >; }; + + pinctrl_esdhc1_2: esdhc1grp-2 { + fsl,pins = < + 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ + 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ + 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ + 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ + 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ + 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ + 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ + 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ + 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ + 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ + >; + }; }; esdhc3 { @@ -303,6 +318,13 @@ 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ >; }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ + 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ + >; + }; }; }; -- cgit v1.2.1 From 327a79c01e45e269da33af1500cd7da8a24c3ba4 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 12 Aug 2012 21:47:36 +0800 Subject: ARM: dts: imx53-evk: add pinctrl settings Add pinctrl settings for the exsiting devices in imx53-evk.dts. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-evk.dts | 31 +++++++++++++++++++++++++++++-- arch/arm/boot/dts/imx53.dtsi | 10 ++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts index 86aebc5b4091..a124d1e25258 100644 --- a/arch/arm/boot/dts/imx53-evk.dts +++ b/arch/arm/boot/dts/imx53-evk.dts @@ -25,12 +25,16 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; wp-gpios = <&gpio3 14 0>; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; @@ -56,6 +60,8 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; cd-gpios = <&gpio3 11 0>; wp-gpios = <&gpio3 12 0>; status = "okay"; @@ -63,17 +69,36 @@ }; iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-evk"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ + 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ + 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */ + 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; pmic: mc13892@08 { @@ -88,6 +113,8 @@ }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 20b67bc5f70b..c08bec5a8400 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -248,6 +248,16 @@ }; }; + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ + 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ + 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ + >; + }; + }; + esdhc1 { pinctrl_esdhc1_1: esdhc1grp-1 { fsl,pins = < -- cgit v1.2.1 From 072480426ba9b5a0d68d91006fdb07fd568ef6ad Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 12 Aug 2012 22:22:33 +0800 Subject: ARM: dts: imx53-smd: add pinctrl settings Add pinctrl settings for the exsiting devices in imx53-smd.dts. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-smd.dts | 38 ++++++++++++++++++++++++++++++++++++-- arch/arm/boot/dts/imx53.dtsi | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 8cdf0a2b0ff3..06c68580c842 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -25,22 +25,30 @@ aips@50000000 { /* AIPS1 */ spba@50000000 { esdhc@50004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; cd-gpios = <&gpio3 13 0>; wp-gpios = <&gpio4 11 0>; status = "okay"; }; esdhc@50008000 { /* ESDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2_1>; non-removable; status = "okay"; }; uart3: serial@5000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; status = "okay"; }; ecspi@50010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; status = "okay"; @@ -72,27 +80,49 @@ }; esdhc@50020000 { /* ESDHC3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3_1>; non-removable; status = "okay"; }; }; iomuxc@53fa8000 { - compatible = "fsl,imx53-iomuxc-smd"; - reg = <0x53fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */ + 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */ + 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */ + 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */ + 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */ + 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */ + 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */ + >; + }; + }; }; uart1: serial@53fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; status = "okay"; }; uart2: serial@53fc0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; status = "okay"; }; }; aips@60000000 { /* AIPS2 */ i2c@63fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; codec: sgtl5000@0a { @@ -112,6 +142,8 @@ }; i2c@63fc8000 { /* I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1>; status = "okay"; accelerometer: mma8450@1c { @@ -131,6 +163,8 @@ }; ethernet@63fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 0>; status = "okay"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index c08bec5a8400..221cf3321b0a 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -286,6 +286,19 @@ }; }; + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ + 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ + 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ + 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ + 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ + 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ + >; + }; + }; + esdhc3 { pinctrl_esdhc3_1: esdhc3grp-1 { fsl,pins = < @@ -336,6 +349,26 @@ >; }; }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ + 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ + 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ + 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ + 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ + >; + }; + }; }; uart1: serial@53fbc000 { -- cgit v1.2.1 From b72cf10578651411143b0ef21bfe0b6ffc921aa2 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 13 Aug 2012 19:45:19 +0800 Subject: ARM: dts: imx51-babbage: add pinctrl settings Add pinctrl settings for the exsiting devices in imx51-babbage.dts. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 36 ++++++++++- arch/arm/boot/dts/imx51.dtsi | 116 ++++++++++++++++++++++++++++++++++++ 2 files changed, 150 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 68460008f662..6f4c80e26c57 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -25,23 +25,31 @@ aips@70000000 { /* aips-1 */ spba@70000000 { esdhc@70004000 { /* ESDHC1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1_1>; fsl,cd-internal; fsl,wp-internal; status = "okay"; }; esdhc@70008000 { /* ESDHC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2_1>; cd-gpios = <&gpio1 6 0>; wp-gpios = <&gpio1 5 0>; status = "okay"; }; uart3: serial@7000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; fsl,uart-has-rtscts; status = "okay"; }; ecspi@70010000 { /* ECSPI1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; status = "okay"; @@ -170,22 +178,42 @@ }; iomuxc@73fa8000 { - compatible = "fsl,imx51-iomuxc-babbage"; - reg = <0x73fa8000 0x4000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + hog { + pinctrl_hog: hoggrp { + fsl,pins = < + 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */ + 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */ + 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */ + 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */ + 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */ + 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */ + 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */ + >; + }; + }; }; uart1: serial@73fbc000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; fsl,uart-has-rtscts; status = "okay"; }; uart2: serial@73fc0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; status = "okay"; }; }; aips@80000000 { /* aips-2 */ i2c@83fc4000 { /* I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_1>; status = "okay"; sgtl5000: codec@0a { @@ -198,10 +226,14 @@ }; audmux@83fd0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; status = "okay"; }; ethernet@83fec000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; phy-mode = "mii"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 6aedb323f184..2f71a91ca98e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -211,6 +211,122 @@ status = "disabled"; }; + iomuxc@73fa8000 { + compatible = "fsl,imx51-iomuxc"; + reg = <0x73fa8000 0x4000>; + + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ + 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ + 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ + 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ + 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ + 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ + 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ + 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ + 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ + 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ + 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ + 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ + 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ + 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ + 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ + 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ + 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ + 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ + 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ + 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ + 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ + 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ + 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ + 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ + 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ + 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ + 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ + >; + }; + }; + + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ + 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ + 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ + 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ + 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ + 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ + 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ + 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ + 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ + 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ + 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ + 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ + 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ + 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ + >; + }; + }; + }; + uart1: serial@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; -- cgit v1.2.1 From f8135a74df53ba7010a162dddd112b73ee5652e3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 24 Aug 2012 12:24:50 -0300 Subject: ARM: imx6q-sabrelite: Rename 'pinctrl_gpio_hog' 'pinctrl_gpio_hog' is used to setup the pin functions, and it is not neccesarily used only for GPIO pins, so remove 'gpio' from its name to describe a more generic term. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index e34ace784ea3..1c57e19e8a8a 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -46,10 +46,10 @@ iomuxc@020e0000 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_hog>; + pinctrl-0 = <&pinctrl_hog>; - gpios { - pinctrl_gpio_hog: gpiohog { + hog { + pinctrl_hog: hoggrp { fsl,pins = < 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ -- cgit v1.2.1 From 0e87e0436c0cc3954eb62181a96d7217ca955a4f Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 22 Aug 2012 21:36:28 +0800 Subject: ARM: imx6q: replace clk_register_clkdev with clock DT lookup It really becomes an maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx6q client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 1 + arch/arm/boot/dts/imx6q.dtsi | 73 ++++++++++++++++++++++++++++++----- 2 files changed, 64 insertions(+), 10 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 72f30f3e6171..cfdbe539c43e 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -111,6 +111,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + clocks = <&clks 169>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index fd57079f71a9..925da33420e2 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -97,18 +97,23 @@ dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; + clocks = <&clks 106>; }; gpmi-nand@00112000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x00112000 0x2000>, <0x00114000 0x2000>; - reg-names = "gpmi-nand", "bch"; - interrupts = <0 13 0x04>, <0 15 0x04>; - interrupt-names = "gpmi-dma", "bch"; - fsl,gpmi-dma-channel = <0>; - status = "disabled"; + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 13 0x04>, <0 15 0x04>; + interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 152>, <&clks 153>, <&clks 151>, + <&clks 150>, <&clks 149>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + fsl,gpmi-dma-channel = <0>; + status = "disabled"; }; timer@00a00600 { @@ -150,6 +155,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02008000 0x4000>; interrupts = <0 31 0x04>; + clocks = <&clks 112>, <&clks 112>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -159,6 +166,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x0200c000 0x4000>; interrupts = <0 32 0x04>; + clocks = <&clks 113>, <&clks 113>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -168,6 +177,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02010000 0x4000>; interrupts = <0 33 0x04>; + clocks = <&clks 114>, <&clks 114>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -177,6 +188,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02014000 0x4000>; interrupts = <0 34 0x04>; + clocks = <&clks 115>, <&clks 115>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -186,6 +199,8 @@ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; reg = <0x02018000 0x4000>; interrupts = <0 35 0x04>; + clocks = <&clks 116>, <&clks 116>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -193,6 +208,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = <0 26 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -205,6 +222,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 0x04>; + clocks = <&clks 178>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <38 37>; status = "disabled"; @@ -214,6 +232,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 0x04>; + clocks = <&clks 179>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <42 41>; status = "disabled"; @@ -223,6 +242,7 @@ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 0x04>; + clocks = <&clks 180>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <46 45>; status = "disabled"; @@ -362,6 +382,7 @@ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 0x04>; + clocks = <&clks 0>; status = "disabled"; }; @@ -369,13 +390,15 @@ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 0x04>; + clocks = <&clks 0>; status = "disabled"; }; - ccm@020c4000 { + clks: ccm@020c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 0x04 0 88 0x04>; + #clock-cells = <1>; }; anatop@020c8000 { @@ -472,12 +495,14 @@ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; + clocks = <&clks 182>; }; usbphy2: usbphy@020ca000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 0x04>; + clocks = <&clks 183>; }; snvs@020cc000 { @@ -612,6 +637,9 @@ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 0x04>; + clocks = <&clks 155>, <&clks 155>; + clock-names = "ipg", "ahb"; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin"; }; }; @@ -635,6 +663,7 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 0x04>; + clocks = <&clks 162>; fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -643,6 +672,7 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = <0 40 0x04>; + clocks = <&clks 162>; fsl,usbphy = <&usbphy2>; status = "disabled"; }; @@ -651,6 +681,7 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = <0 41 0x04>; + clocks = <&clks 162>; status = "disabled"; }; @@ -658,6 +689,7 @@ compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184600 0x200>; interrupts = <0 42 0x04>; + clocks = <&clks 162>; status = "disabled"; }; @@ -665,6 +697,8 @@ compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupts = <0 118 0x04 0 119 0x04>; + clocks = <&clks 117>, <&clks 117>; + clock-names = "ipg", "ahb"; status = "disabled"; }; @@ -677,6 +711,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 0x04>; + clocks = <&clks 163>, <&clks 163>, <&clks 163>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -684,6 +720,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 0x04>; + clocks = <&clks 164>, <&clks 164>, <&clks 164>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -691,6 +729,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 0x04>; + clocks = <&clks 165>, <&clks 165>, <&clks 165>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -698,6 +738,8 @@ compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 0x04>; + clocks = <&clks 166>, <&clks 166>, <&clks 166>; + clock-names = "ipg", "ahb", "per"; status = "disabled"; }; @@ -707,6 +749,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a0000 0x4000>; interrupts = <0 36 0x04>; + clocks = <&clks 125>; status = "disabled"; }; @@ -716,6 +759,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a4000 0x4000>; interrupts = <0 37 0x04>; + clocks = <&clks 126>; status = "disabled"; }; @@ -725,6 +769,7 @@ compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c"; reg = <0x021a8000 0x4000>; interrupts = <0 38 0x04>; + clocks = <&clks 127>; status = "disabled"; }; @@ -788,6 +833,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = <0 27 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -795,6 +842,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = <0 28 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -802,6 +851,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = <0 29 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; @@ -809,6 +860,8 @@ compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = <0 30 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; status = "disabled"; }; }; -- cgit v1.2.1 From 44b12ef78106141574f038852d013fd3207acb23 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 11 Sep 2012 11:42:26 -0600 Subject: ARM: dt: tegra: configure power off for some boards For Seaboard, Ventana, and Cardhu, add DT property to tell the regulator that it should provide the pm_power_off() implementation. This allows "shutdown" to work. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-seaboard.dts | 2 ++ arch/arm/boot/dts/tegra20-ventana.dts | 2 ++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 ++ 3 files changed, 6 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 92deb36ae03c..e60dc7124e92 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -379,6 +379,8 @@ reg = <0x34>; interrupts = <0 86 0x4>; + ti,system-power-controller; + #gpio-cells = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 4ec6b4cd9d52..3e5952fcfbc5 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -295,6 +295,8 @@ reg = <0x34>; interrupts = <0 86 0x4>; + ti,system-power-controller; + #gpio-cells = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 47946939b49e..d10c9c5a3606 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -156,6 +156,8 @@ #interrupt-cells = <2>; interrupt-controller; + ti,system-power-controller; + #gpio-cells = <2>; gpio-controller; -- cgit v1.2.1 From 8996b89d6bc98ae2f6d6e6e624a42a3f89d06949 Mon Sep 17 00:00:00 2001 From: Mark Langsdorf Date: Thu, 6 Sep 2012 16:03:30 -0500 Subject: ata: add platform driver for Calxeda AHCI controller Calxeda highbank SATA phy has intermittent problems bringing up a link with Gen3 drives. Retrying the phy hard reset can work-around this issue, but each reset also disables spread spectrum support. The reset function also needs to reprogram the phy to enable spread spectrum support. Create a new driver based on ahci_platform to support the Calxeda Highbank SATA controller. Signed-off-by: Mark Langsdorf Signed-off-by: Rob Herring Signed-off-by: Jeff Garzik --- arch/arm/boot/dts/highbank.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 9fecf1ae777b..5204cf73c2d8 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -121,6 +121,9 @@ compatible = "calxeda,hb-ahci"; reg = <0xffe08000 0x10000>; interrupts = <0 83 4>; + calxeda,port-phys = <&combophy5 0 &combophy0 0 + &combophy0 1 &combophy0 2 + &combophy0 3>; }; sdhci@ffe0e000 { @@ -306,5 +309,19 @@ reg = <0xfff51000 0x1000>; interrupts = <0 80 4 0 81 4 0 82 4>; }; + + combophy0: combo-phy@fff58000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff58000 0x1000>; + phydev = <5>; + }; + + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; }; }; -- cgit v1.2.1 From 8407116075eca1d8d22a466759c3d38678b9dd12 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 5 Sep 2012 12:28:54 -0700 Subject: ARM: msm: Move 8660 to DT timer Add the timer entry and point the machine descriptor to the device tree based msm timer. Signed-off-by: Stephen Boyd [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown --- arch/arm/boot/dts/msm8660-surf.dts | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts index 45bc4bb04e57..31f2157cd7d7 100644 --- a/arch/arm/boot/dts/msm8660-surf.dts +++ b/arch/arm/boot/dts/msm8660-surf.dts @@ -7,7 +7,7 @@ compatible = "qcom,msm8660-surf", "qcom,msm8660"; interrupt-parent = <&intc>; - intc: interrupt-controller@02080000 { + intc: interrupt-controller@2080000 { compatible = "qcom,msm-8660-qgic"; interrupt-controller; #interrupt-cells = <3>; @@ -15,6 +15,23 @@ < 0x02081000 0x1000 >; }; + timer@2000004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 1 0x301>; + reg = <0x02000004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x40000>; + }; + + timer@2000024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 0 0x301>; + reg = <0x02000024 0x10>, + <0x02000034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x40000>; + }; + serial@19c400000 { compatible = "qcom,msm-hsuart", "qcom,msm-uart"; reg = <0x19c40000 0x1000>, -- cgit v1.2.1 From c446407c09ce0b339a84931f3d45f3dabb9f0b17 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 5 Sep 2012 12:28:58 -0700 Subject: ARM: msm: Add DT support for 8960 Add basic support to boot 8960 with device tree. For now just support a basic machine with a uart device. Signed-off-by: Stephen Boyd [davidb@codeaurora.org: Remove leading zeros] Signed-off-by: David Brown --- arch/arm/boot/dts/msm8960-cdp.dts | 41 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 arch/arm/boot/dts/msm8960-cdp.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts new file mode 100644 index 000000000000..9e621b5ad3dd --- /dev/null +++ b/arch/arm/boot/dts/msm8960-cdp.dts @@ -0,0 +1,41 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + model = "Qualcomm MSM8960 CDP"; + compatible = "qcom,msm8960-cdp", "qcom,msm8960"; + interrupt-parent = <&intc>; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02000000 0x1000 >, + < 0x02002000 0x1000 >; + }; + + timer@200a004 { + compatible = "qcom,msm-gpt", "qcom,msm-timer"; + interrupts = <1 2 0x301>; + reg = <0x0200a004 0x10>; + clock-frequency = <32768>; + cpu-offset = <0x80000>; + }; + + timer@200a024 { + compatible = "qcom,msm-dgt", "qcom,msm-timer"; + interrupts = <1 1 0x301>; + reg = <0x0200a024 0x10>, + <0x0200a034 0x4>; + clock-frequency = <6750000>; + cpu-offset = <0x80000>; + }; + + serial@19c400000 { + compatible = "qcom,msm-hsuart", "qcom,msm-uart"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <0 154 0x0>; + }; +}; -- cgit v1.2.1 From 360a0cab50414ee30924917159066e69ee4b38d3 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 6 Sep 2012 13:32:38 -0500 Subject: ARM: move all dtb targets out of Makefile.boot In preparation to support multi-platform kernels, move all the dtb targets out of the mach Makefile.boot and into the arch/arm/boot/dts/Makefile which is closer to the sources. DTBs are only built when CONFIG_OF is enabled and now use top level CONFIG_ARCH_xxx instead of chip or board specific config options. Signed-off-by: Rob Herring Cc: Russell King Cc: Andrew Victor Cc: Nicolas Ferre Cc: Jean-Christophe Plagniol-Villard Cc: Kukjin Kim Cc: Sascha Hauer Cc: Jason Cooper Cc: Andrew Lunn Cc: Gregory Clement Acked-by: Shawn Guo Cc: Viresh Kumar Cc: Shiraz Hashim Cc: Rajeev Kumar Cc: Stephen Warren Cc: Srinidhi Kasagar Cc: Linus Walleij --- arch/arm/boot/Makefile | 2 ++ arch/arm/boot/dts/Makefile | 71 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 arch/arm/boot/dts/Makefile (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index c877087d2000..3fdab016aa5c 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -15,6 +15,8 @@ ifneq ($(MACHINE),) include $(srctree)/$(MACHINE)/Makefile.boot endif +include $(srctree)/arch/arm/boot/dts/Makefile + # Note: the following conditions must always be true: # ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET) # PARAMS_PHYS must be within 4MB of ZRELADDR diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile new file mode 100644 index 000000000000..d081e6a55db2 --- /dev/null +++ b/arch/arm/boot/dts/Makefile @@ -0,0 +1,71 @@ +ifeq ($(CONFIG_OF),y) + +dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ + at91sam9263ek.dtb \ + at91sam9g20ek_2mmc.dtb \ + at91sam9g20ek.dtb \ + at91sam9g25ek.dtb \ + at91sam9m10g45ek.dtb \ + at91sam9n12ek.dtb \ + ethernut5.dtb \ + evk-pro3.dtb \ + kizbox.dtb \ + tny_a9260.dtb \ + tny_a9263.dtb \ + tny_a9g20.dtb \ + usb_a9260.dtb \ + usb_a9263.dtb \ + usb_a9g20.dtb +dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ + exynos5250-smdk5250.dtb +dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb +dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb +dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \ + kirkwood-dns325.dtb \ + kirkwood-dreamplug.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-ib62x0.dtb \ + kirkwood-iconnect.dtb \ + kirkwood-lschlv2.dtb \ + kirkwood-lsxhl.dtb \ + kirkwood-ts219-6281.dtb \ + kirkwood-ts219-6282.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ + armada-xp-db.dtb +dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ + imx53-ard.dtb \ + imx53-evk.dtb \ + imx53-qsb.dtb \ + imx53-smd.dtb \ + imx6q-arm2.dtb \ + imx6q-sabrelite.dtb \ + imx6q-sabresd.dtb +dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ + imx23-olinuxino.dtb \ + imx23-stmp378x_devb.dtb \ + imx28-apx4devkit.dtb \ + imx28-cfa10036.dtb \ + imx28-evk.dtb \ + imx28-m28evk.dtb \ + imx28-tx28.dtb +dtb-$(CONFIG_ARCH_U8500) += snowball.dtb +dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ + spear1340-evb.dtb +dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ + spear310-evb.dtb \ + spear320-evb.dtb +dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb +dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ + tegra20-paz00.dtb \ + tegra20-seaboard.dtb \ + tegra20-trimslice.dtb \ + tegra20-ventana.dtb \ + tegra20-whistler.dtb \ + tegra30-cardhu.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ + vexpress-v2p-ca9.dtb \ + vexpress-v2p-ca15-tc1.dtb \ + vexpress-v2p-ca15_a7.dtb + +endif -- cgit v1.2.1 From 387798b37c8dd0ae24c0ac12ba456dd76865bca3 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 6 Sep 2012 13:41:12 -0500 Subject: ARM: initial multiplatform support This lets us build a multiplatform kernel for experimental purposes. However, it will not be useful for any real work, because it relies on a number of useful things to be disabled for now: * SMP support must be turned off because of conflicting symbols. Marc Zyngier has proposed a solution by adding a new SOC operations structure to hold indirect function pointers for these, but that work is currently stalled * We turn on SPARSE_IRQ unconditionally, which is not supported on most platforms. Each of them is currently in a different state, but most are being worked on. * A common clock framework is in place since v3.4 but not yet being used. Work on this is on its way. * DEBUG_LL for early debugging is currently disabled. * THUMB2_KERNEL does not work with allyesconfig because the kernel gets too big [Rob Herring]: Rebased to not be dependent on the mass mach header rename. As a result, omap2plus, imx, mxs and ux500 are not converted. Highbank, picoxcell, mvebu, and socfpga are converted. Signed-off-by: Arnd Bergmann Signed-off-by: Rob Herring Cc: Russell King Cc: Jason Cooper Cc: Andrew Lunn Acked-by: Jamie Iles Cc: Dinh Nguyen --- arch/arm/boot/compressed/misc.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 8e2a8fca5ed2..df899834d84e 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -25,7 +25,13 @@ unsigned int __machine_arch_type; static void putstr(const char *ptr); extern void error(char *x); +#ifdef CONFIG_ARCH_MULTIPLATFORM +static inline void putc(int c) {} +static inline void flush(void) {} +static inline void arch_decomp_setup(void) {} +#else #include +#endif #ifdef CONFIG_DEBUG_ICEDCC -- cgit v1.2.1 From 3cc404de243f5cc3cfe8036c6e84232c1401137b Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 16 Aug 2012 20:59:59 +0000 Subject: ARM: dt: tegra: harmony: add regulators Harmony uses a TPS6586x regulator. Instantiate this, and hook up a couple of fixed GPIO-controlled regulators too. Based on Ventana regulator patch by Stephen Warren and converted to Harmony. swarren made the following changes: * Added ldo0 regulator configuration to device tree, and updated board-harmony-pcie.c for the new regulator name. * Fixed vdd_1v05's voltage from 10.5V to 1.05V. * Modified board-harmony-pcie.c to obtain the en_vdd_1v05 GPIO number at run-time from device tree instead of hard-coding it. * Removed board-harmony{-power.c,.h} now that they're unused. * Disabled vdd_1v05 regulator; the code in board-harmony-pcie.c hijacks this GPIO for now. This will be fixed when the PCIe driver is re- written as a driver. The code can't regulator_get("vdd_1v05") right now, because the vdd_1v05 regulator's probe gets deferred due to its supply being the PMIC, which gets probed after the regulator the first time around, and this dependency is only resolved by repeated probing, which happens when deferred_probe_initcall() is called, which happens in a late initcall, whose runtime order relative to harmony_pcie_init() is undefined, since that's also called from a late initcall. * Removed unused harmony_pcie_initcall(). Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-harmony.dts | 218 ++++++++++++++++++++++++++++++++++ 1 file changed, 218 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index f146dbf6f7f8..0eca40d2be02 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -275,6 +275,158 @@ i2c@7000d000 { status = "okay"; clock-frequency = <400000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo0"; + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; }; pmc { @@ -310,6 +462,72 @@ bus-width = <8>; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 0>; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 0>; + enable-active-high; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 0>; + enable-active-high; + /* Hack until board-harmony-pcie.c is removed */ + status = "disabled"; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 22 0>; /* gpio PC6 */ + enable-active-high; + }; + + regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 176 0>; /* gpio PW0 */ + enable-active-high; + }; + }; + sound { compatible = "nvidia,tegra-audio-wm8903-harmony", "nvidia,tegra-audio-wm8903"; -- cgit v1.2.1 From be972c3272c354b323afcb7e9552a9b04e675a8b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 11 Sep 2012 11:40:04 -0600 Subject: ARM: dt: tegra: harmony: configure power off Add DT property to tell the TPS6586x that it should provide the pm_power_off() implementation. This allows "shutdown" to work. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-harmony.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 0eca40d2be02..b98a1b36e694 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -281,6 +281,8 @@ reg = <0x34>; interrupts = <0 86 0x4>; + ti,system-power-controller; + #gpio-cells = <2>; gpio-controller; -- cgit v1.2.1 From 8c41d57395ff5b9b16724786c7c4b4c4081510cc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 13 Sep 2012 13:23:22 +0200 Subject: ARM: dts: mxs: Add ethernetX to macX aliases Add ethernet0 and ethernet1 aliases into the imx28.dtsi file, as that is what most bootloaders use to pass MAC address. The bootloader seeks for this alias and adds "mac-address" and "local-mac-address" properties to the aliased node. This fixes issues with FEC having NULL MAC address when update_fec_mac_prop() wasn't called. And not all boards call update_fec_mac_prop() . Signed-off-by: Marek Vasut Cc: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 03e0fef8e7a7..724147eab84b 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -27,6 +27,8 @@ serial2 = &auart2; serial3 = &auart3; serial4 = &auart4; + ethernet0 = &mac0; + ethernet1 = &mac1; }; cpus { -- cgit v1.2.1 From d6475317b569d531730c07bbc27b29257c348fd0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 13 Sep 2012 14:33:38 -0300 Subject: ARM: dts: mx23: Add USB resources Add USB resources for mx23. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 9d0e803e3eca..3f3b6fc229b3 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -436,8 +436,10 @@ status = "disabled"; }; - usbphy@8007c000 { + usbphy0: usbphy@8007c000 { + compatible = "fsl,imx23-usbphy"; reg = <0x8007c000 0x2000>; + clocks = <&clks 41>; status = "disabled"; }; }; @@ -450,8 +452,12 @@ reg = <0x80080000 0x80000>; ranges; - usbctrl@80080000 { + usb0: usb@80080000 { + compatible = "fsl,imx23-usb", "fsl,imx27-usb"; reg = <0x80080000 0x40000>; + interrupts = <11>; + fsl,usbphy = <&usbphy0>; + clocks = <&clks 40>; status = "disabled"; }; }; -- cgit v1.2.1 From 28342c6113dcfb1c730dff71c7ac0feab5ee2e6a Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 14 Sep 2012 14:42:45 +0800 Subject: ARM: dts: imx6q-sabrelite: add usbmisc device - add usbmisc device - set property fsl,usbmisc for usb controllers - set disable-over-current for imx6q-sabrelite usb otg Signed-off-by: Richard Zhao Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 1 + arch/arm/boot/dts/imx6q.dtsi | 11 +++++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 0fb29ca7a9e1..0cb7dcd63c9e 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -68,6 +68,7 @@ aips-bus@02100000 { /* AIPS2 */ usb@02184000 { /* USB OTG */ vbus-supply = <®_usb_otg_vbus>; + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e45476dc6d32..b40c0ddd2648 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -777,6 +777,7 @@ interrupts = <0 43 0x04>; clocks = <&clks 162>; fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -786,6 +787,7 @@ interrupts = <0 40 0x04>; clocks = <&clks 162>; fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -794,6 +796,7 @@ reg = <0x02184400 0x200>; interrupts = <0 41 0x04>; clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 2>; status = "disabled"; }; @@ -802,9 +805,17 @@ reg = <0x02184600 0x200>; interrupts = <0 42 0x04>; clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 3>; status = "disabled"; }; + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks 162>; + }; + ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; -- cgit v1.2.1 From df37e0c0931ceeb159c8e017445c6d4799b7f345 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Wed, 5 Sep 2012 10:57:14 +0800 Subject: ARM: imx6q: Add iomuxc gpr support into syscon Include headfile for easy using. Acked-by: Stephen Warren Signed-off-by: Dong Aisheng Signed-off-by: Samuel Ortiz --- arch/arm/boot/dts/imx6q.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index fd57079f71a9..bea21bc1aadd 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -507,6 +507,11 @@ interrupts = <0 89 0x04 0 90 0x04>; }; + gpr: iomuxc-gpr@020e0000 { + compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e0000 0x38>; + }; + iomuxc@020e0000 { compatible = "fsl,imx6q-iomuxc"; reg = <0x020e0000 0x4000>; -- cgit v1.2.1 From baa64151aecccedbafae1bbc0c167c8b2a711752 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Wed, 5 Sep 2012 10:57:15 +0800 Subject: regulator: anatop-regulator: Convert to use syscon to access anatop register Using syscon to access anatop register. Acked-by: Mark Brown Acked-by: Stephen Warren Signed-off-by: Dong Aisheng Signed-off-by: Samuel Ortiz --- arch/arm/boot/dts/imx6q.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index bea21bc1aadd..52ed4d1ff4ed 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -378,8 +378,8 @@ interrupts = <0 87 0x04 0 88 0x04>; }; - anatop@020c8000 { - compatible = "fsl,imx6q-anatop"; + anatop: anatop@020c8000 { + compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; -- cgit v1.2.1 From 4980f9bc2cec0f8ff0e0f2b021d46c7606ae1849 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 6 Sep 2012 09:08:24 +0100 Subject: ARM: 7517/1: integrator: initial device tree support This is initial device tree support for the ARM Integrator family, we create a very basic device tree, #ifdef out the non-DT machines when compiling for device tree. Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/boot/dts/integrator.dtsi | 33 +++++++++++++++++++++++ arch/arm/boot/dts/integratorap.dts | 36 +++++++++++++++++++++++++ arch/arm/boot/dts/integratorcp.dts | 54 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 123 insertions(+) create mode 100644 arch/arm/boot/dts/integrator.dtsi create mode 100644 arch/arm/boot/dts/integratorap.dts create mode 100644 arch/arm/boot/dts/integratorcp.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi new file mode 100644 index 000000000000..b464abadd10b --- /dev/null +++ b/arch/arm/boot/dts/integrator.dtsi @@ -0,0 +1,33 @@ +/* + * SoC core Device Tree for the ARM Integrator platforms + */ + +/include/ "skeleton.dtsi" + +/ { + timer@13000000 { + reg = <0x13000000 0x100>; + interrupt-parent = <&pic>; + interrupts = <5>; + }; + + timer@13000100 { + reg = <0x13000100 0x100>; + interrupt-parent = <&pic>; + interrupts = <6>; + }; + + timer@13000200 { + reg = <0x13000200 0x100>; + interrupt-parent = <&pic>; + interrupts = <7>; + }; + + pic@14000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x14000000 0x100>; + clear-mask = <0xffffffff>; + }; +}; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts new file mode 100644 index 000000000000..083ff395de0f --- /dev/null +++ b/arch/arm/boot/dts/integratorap.dts @@ -0,0 +1,36 @@ +/* + * Device Tree for the ARM Integrator/AP platform + */ + +/dts-v1/; +/include/ "integrator.dtsi" + +/ { + model = "ARM Integrator/AP"; + compatible = "arm,integrator-ap"; + + aliases { + arm,timer-primary = &timer2; + arm,timer-secondary = &timer1; + }; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; + }; + + timer0: timer@13000000 { + compatible = "arm,integrator-timer"; + }; + + timer1: timer@13000100 { + compatible = "arm,integrator-timer"; + }; + + timer2: timer@13000200 { + compatible = "arm,integrator-timer"; + }; + + pic: pic@14000000 { + valid-mask = <0x003fffff>; + }; +}; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts new file mode 100644 index 000000000000..63033144442a --- /dev/null +++ b/arch/arm/boot/dts/integratorcp.dts @@ -0,0 +1,54 @@ +/* + * Device Tree for the ARM Integrator/CP platform + */ + +/dts-v1/; +/include/ "integrator.dtsi" + +/ { + model = "ARM Integrator/CP"; + compatible = "arm,integrator-cp"; + + aliases { + arm,timer-primary = &timer2; + arm,timer-secondary = &timer1; + }; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; + }; + + timer0: timer@13000000 { + compatible = "arm,sp804", "arm,primecell"; + }; + + timer1: timer@13000100 { + compatible = "arm,sp804", "arm,primecell"; + }; + + timer2: timer@13000200 { + compatible = "arm,sp804", "arm,primecell"; + }; + + pic: pic@14000000 { + valid-mask = <0x1fc003ff>; + }; + + cic: cic@10000040 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0x10000040 0x100>; + clear-mask = <0xffffffff>; + valid-mask = <0x00000007>; + }; + + sic: sic@ca000000 { + compatible = "arm,versatile-fpga-irq"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xca000000 0x100>; + clear-mask = <0x00000fff>; + valid-mask = <0x00000fff>; + }; +}; -- cgit v1.2.1 From 4672cddff21f6edde857aa4b523bbc1bfc741cf8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 6 Sep 2012 09:08:47 +0100 Subject: ARM: 7518/1: integrator: convert AMBA devices to device tree This converts the AMBA (PrimeCell) devices on the Integrator/AP and Integrator/CP over to probing from the Device Tree if the kernel is compiled for Device Tree support. We continue to #ifdef out all non-DT code and vice versa on respective boot type to get a clean cut. We need to add a bunch of auxdata (compare to the Versatile) to handle bus names and callbacks alike. Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/boot/dts/integrator.dtsi | 38 +++++++++++++++++++++++++++++ arch/arm/boot/dts/integratorap.dts | 32 +++++++++++++++++++++++++ arch/arm/boot/dts/integratorcp.dts | 49 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index b464abadd10b..9bcc09d54457 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -30,4 +30,42 @@ reg = <0x14000000 0x100>; clear-mask = <0xffffffff>; }; + + fpga { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&pic>; + + /* + * These PrimeCells are in the same locations and using the + * same interrupts in all Integrators, however the silicon + * version deployed is different. + */ + rtc@15000000 { + reg = <0x15000000 0x1000>; + interrupts = <8>; + }; + + uart@16000000 { + reg = <0x16000000 0x1000>; + interrupts = <1>; + }; + + uart@17000000 { + reg = <0x17000000 0x1000>; + interrupts = <2>; + }; + + kmi@18000000 { + reg = <0x18000000 0x1000>; + interrupts = <3>; + }; + + kmi@19000000 { + reg = <0x19000000 0x1000>; + interrupts = <4>; + }; + }; }; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 083ff395de0f..61767757b50a 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -33,4 +33,36 @@ pic: pic@14000000 { valid-mask = <0x003fffff>; }; + + fpga { + /* + * The Integator/AP predates the idea to have magic numbers + * identifying the PrimeCell in hardware, thus we have to + * supply these from the device tree. + */ + rtc: rtc@15000000 { + compatible = "arm,pl030", "arm,primecell"; + arm,primecell-periphid = <0x00041030>; + }; + + uart0: uart@16000000 { + compatible = "arm,pl010", "arm,primecell"; + arm,primecell-periphid = <0x00041010>; + }; + + uart1: uart@17000000 { + compatible = "arm,pl010", "arm,primecell"; + arm,primecell-periphid = <0x00041010>; + }; + + kmi0: kmi@18000000 { + compatible = "arm,pl050", "arm,primecell"; + arm,primecell-periphid = <0x00041050>; + }; + + kmi1: kmi@19000000 { + compatible = "arm,pl050", "arm,primecell"; + arm,primecell-periphid = <0x00041050>; + }; + }; }; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 63033144442a..7bd49466cb0d 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -51,4 +51,53 @@ clear-mask = <0x00000fff>; valid-mask = <0x00000fff>; }; + + fpga { + /* + * These PrimeCells are at the same location and using + * the same interrupts in all Integrators, but in the CP + * slightly newer versions are deployed. + */ + rtc@15000000 { + compatible = "arm,pl031", "arm,primecell"; + }; + + uart@16000000 { + compatible = "arm,pl011", "arm,primecell"; + }; + + uart@17000000 { + compatible = "arm,pl011", "arm,primecell"; + }; + + kmi@18000000 { + compatible = "arm,pl050", "arm,primecell"; + }; + + kmi@19000000 { + compatible = "arm,pl050", "arm,primecell"; + }; + + /* + * These PrimeCells are only available on the Integrator/CP + */ + mmc@1c000000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x1c000000 0x1000>; + interrupts = <23 24>; + max-frequency = <515633>; + }; + + aaci@1d000000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x1d000000 0x1000>; + interrupts = <25>; + }; + + clcd@c0000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0xC0000000 0x1000>; + interrupts = <22>; + }; + }; }; -- cgit v1.2.1 From 73efd53012af7775a4504da46ebf4145528d50e7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 6 Sep 2012 09:09:11 +0100 Subject: ARM: 7519/1: integrator: convert platform devices to Device Tree This moves the physmap flash and SMSC91x ethernet devices over to the device tree, moving the static board code down into the #ifndef CONFIG_OF section. Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/boot/dts/integrator.dtsi | 5 +++++ arch/arm/boot/dts/integratorcp.dts | 7 +++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 9bcc09d54457..813b91d7bea2 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -31,6 +31,11 @@ clear-mask = <0xffffffff>; }; + flash@24000000 { + compatible = "cfi-flash"; + reg = <0x24000000 0x02000000>; + }; + fpga { compatible = "arm,amba-bus", "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 7bd49466cb0d..2dd5e4e48481 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -52,6 +52,13 @@ valid-mask = <0x00000fff>; }; + ethernet@c8000000 { + compatible = "smsc,lan91c111"; + reg = <0xc8000000 0x10>; + interrupt-parent = <&pic>; + interrupts = <27>; + }; + fpga { /* * These PrimeCells are at the same location and using -- cgit v1.2.1 From b493129482851ad34c43db3369b2750fc59aa249 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 17 Sep 2012 10:01:45 -0300 Subject: ARM: dts: imx23-olinuxino: Add USB host support Add USB host support. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-olinuxino.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 711dcf5742b6..384d8b66f337 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -40,6 +40,7 @@ reg = <0>; fsl,pinmux-ids = < 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ + 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ >; fsl,drive-strength = <0>; fsl,voltage = <1>; @@ -60,6 +61,31 @@ pinctrl-0 = <&auart0_2pins_a>; status = "okay"; }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ + gpio = <&gpio0 17 0>; }; }; -- cgit v1.2.1 From 97a53092a148e6c70aabf13835143cc3dd4b524c Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Wed, 19 Sep 2012 11:25:16 +0800 Subject: ARM: dts: imx6q-sabrelite: add usbotg pinctrl support Signed-off-by: Richard Zhao Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-sabrelite.dts | 2 ++ arch/arm/boot/dts/imx6q.dtsi | 8 ++++++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 0cb7dcd63c9e..d152328285a1 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -68,6 +68,8 @@ aips-bus@02100000 { /* AIPS2 */ usb@02184000 { /* USB OTG */ vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_1>; disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index b40c0ddd2648..35e5895ba3df 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -661,6 +661,14 @@ }; }; + usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < + 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ + >; + }; + }; + usdhc2 { pinctrl_usdhc2_1: usdhc2grp-1 { fsl,pins = < -- cgit v1.2.1 From 3c7c5dab44d6c8861bc86dab924353d8d40344f8 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 13 Aug 2012 14:39:03 +0530 Subject: ARM: OMAP5: Enable arch timer support Enable Cortex A15 generic timer support for OMAP5 based SOCs. The CPU local timers run on the free running real time counter clock. Acked-by: Benoit Cousson Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/omap5.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 57e527083746..7b986eddd0b9 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -33,9 +33,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; cpu@1 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; }; -- cgit v1.2.1 From b37ed4a3e561db09549ce16e9f572e6f204315f7 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 11 Sep 2012 13:13:05 -0600 Subject: ARM: dt: tegra: whistler: configure power off Add DT property to tell the MAX8907 that it should provide the pm_power_off() implementation. This allows "shutdown" to work. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-whistler.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 4ae1e5dcfa62..c636d002d6d8 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -267,6 +267,8 @@ reg = <0x3c>; interrupts = <0 86 0x4>; + maxim,system-power-controller; + mbatt-supply = <&usb0_vbus_reg>; in-v1-supply = <&mbatt_reg>; in-v2-supply = <&mbatt_reg>; -- cgit v1.2.1 From ec9653b8476bf526dde7bdefbc2be6b7aaa34db7 Mon Sep 17 00:00:00 2001 From: Simon Arlott Date: Sat, 26 May 2012 01:04:43 -0600 Subject: ARM: add infra-structure for BCM2835 and Raspberry Pi The BCM2835 is an ARM SoC from Broadcom. This patch adds very basic support for this SoC. http://www.broadcom.com/products/BCM2835 http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf Note that the documentation in the latter .pdf assumes the MMU setup that's used on the "VideoCore" companion processor, and does not document physical peripheral addresses. Subtract 0x5e000000 to obtain the physical addresses. This is accounted for by the ranges property in the /soc node in the device tree. The BCM2835 SoC is used in the Raspberry Pi. This patch also adds a minimal device tree for this board; enough to see some very early kernel boot messages through earlyprintk. However, this patch does not yet provide a useful booting system. http://www.raspberrypi.org/. This patch was extracted from git://github.com/lp0/linux.git branch rpi-split from 3-4 months ago, and significantly stripped down and modified since. Signed-off-by: Chris Boot Signed-off-by: Simon Arlott Signed-off-by: Dom Cobley Signed-off-by: Dom Cobley Signed-off-by: Stephen Warren Acked-by: Arnd Bergmann --- arch/arm/boot/dts/bcm2835-rpi-b.dts | 12 ++++++++++++ arch/arm/boot/dts/bcm2835.dtsi | 17 +++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm/boot/dts/bcm2835-rpi-b.dts create mode 100644 arch/arm/boot/dts/bcm2835.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts new file mode 100644 index 000000000000..7dd860f83f96 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/memreserve/ 0x0c000000 0x04000000; +/include/ "bcm2835.dtsi" + +/ { + compatible = "raspberrypi,model-b", "brcm,bcm2835"; + model = "Raspberry Pi Model B"; + + memory { + reg = <0 0x10000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi new file mode 100644 index 000000000000..a31cb40ef684 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -0,0 +1,17 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "brcm,bcm2835"; + model = "BCM2835"; + + chosen { + bootargs = "earlyprintk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x7e000000 0x20000000 0x02000000>; + }; +}; -- cgit v1.2.1 From 89214f009c1d38568456dcf997d93977928fe2c3 Mon Sep 17 00:00:00 2001 From: Simon Arlott Date: Wed, 12 Sep 2012 19:57:26 -0600 Subject: ARM: bcm2835: add interrupt controller driver The BCM2835 contains a custom interrupt controller, which supports 72 interrupt sources using a 2-level register scheme. The interrupt controller, or the HW block containing it, is referred to occasionally as "armctrl" in the SoC documentation, hence the symbol naming in the code. This patch was extracted from git://github.com/lp0/linux.git branch rpi-split as of 2012/09/08, and modified as follows: * s/bcm2708/bcm2835/. * Modified device tree vendor prefix. * Moved implementation to drivers/irchip/. * Added devicetree documentation, and hence removed list of IRQs from bcm2835.dtsi. * Changed shift in MAKE_HWIRQ() and HWIRQ_BANK() from 8 to 5 to reduce the size of the hwirq space, and pass the total size of the hwirq space to irq_domain_add_linear(), rather than just the number of valid hwirqs; the two are different due to the hwirq space being sparse. * Added the interrupt controller DT node to the top-level of the DT, rather than nesting it inside a /axi node. Hence, changed the reg value since /axi had a ranges property. This seems simpler to me, but I'm not sure if everyone will like this change or not. * Don't set struct irq_domain_ops.map = irq_domain_simple_map, hence removing the need to patch include/linux/irqdomain.h or kernel/irq/irqdomain.c. * Simplified armctrl_of_init() using of_iomap(). * Removed unused IS_VALID_BANK()/IS_VALID_IRQ() macros. * Renamed armctrl_handle_irq() to prevent possible symbol clashes. * Made armctrl_of_init() static. * Removed comment "Each bank is registered as a separate interrupt controller" since this is no longer true. * Removed FSF address from license header. * Added my name to copyright header. Signed-off-by: Chris Boot Signed-off-by: Simon Arlott Signed-off-by: Dom Cobley Signed-off-by: Dom Cobley Signed-off-by: Stephen Warren Acked-by: Arnd Bergmann --- arch/arm/boot/dts/bcm2835.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index a31cb40ef684..8842d751d7dd 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -3,6 +3,7 @@ / { compatible = "brcm,bcm2835"; model = "BCM2835"; + interrupt-parent = <&intc>; chosen { bootargs = "earlyprintk"; @@ -13,5 +14,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x7e000000 0x20000000 0x02000000>; + + intc: interrupt-controller { + compatible = "brcm,bcm2835-armctrl-ic"; + reg = <0x7e00b200 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; }; -- cgit v1.2.1 From ee4af5696720bb5b9de2e3b18be42089bed1e638 Mon Sep 17 00:00:00 2001 From: Simon Arlott Date: Mon, 10 Sep 2012 22:38:35 -0600 Subject: ARM: bcm2835: add system timer The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter. Each channel has an output compare register, which is compared against the 32 least significant bits of the free running counter values, and generates an interrupt. Timer 3 is used as the Linux timer. The BCM2835 also contains an SP804-based timer module. However, it apparently has significant differences from the standard SP804 IP block, and Broadcom's documentation recommends using the system timer instead. This patch was extracted from git://github.com/lp0/linux.git branch rpi-split as of 2012/09/08, and modified as follows: * s/bcm2708/bcm2835/. * Modified device tree vendor prefix. * Moved to drivers/clocksource/. This looks like the desired location for such code now. * Added DT binding docs. * Moved struct sys_timer bcm2835_timer into time.c to encapsulate it more. * Simplified bcm2835_time_init() to find one matching node and operate on it, rather than looping over all matching nodes. This seems more consistent with other clocksource code. * Simplified bcm2835_time_init() using of_iomap(). * Renamed struct bcm2835_timer.index to match_mask to better represent its purpose. * s/printk(PR_INFO/pr_info(/ Signed-off-by: Chris Boot Signed-off-by: Simon Arlott Signed-off-by: Dom Cobley Signed-off-by: Dom Cobley Signed-off-by: Stephen Warren Acked-by: Arnd Bergmann --- arch/arm/boot/dts/bcm2835.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 8842d751d7dd..e7471d271e0f 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -15,6 +15,13 @@ #size-cells = <1>; ranges = <0x7e000000 0x20000000 0x02000000>; + timer { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7e003000 0x1000>; + interrupts = <1 0>, <1 1>, <1 2>, <1 3>; + clock-frequency = <1000000>; + }; + intc: interrupt-controller { compatible = "brcm,bcm2835-armctrl-ic"; reg = <0x7e00b200 0x200>; -- cgit v1.2.1 From 407f9be4544538674fb83a2d064a25428595c7ff Mon Sep 17 00:00:00 2001 From: Simon Arlott Date: Mon, 10 Sep 2012 23:29:17 -0600 Subject: ARM: bcm2835: instantiate console UART This patch was extracted from git://github.com/lp0/linux.git branch rpi-split as of 2012/09/08, and modified as follows: * s/bcm2708/bcm2835/. * Modified device tree vendor prefix. * Modified UART DT node to use a unit-address to create unique UART node names, rather than using non-type names "uart0" and "uart1". Note that UART 1 (the Broadcom "mini UART") is not yet present, but I'm naming the DT node in anticipation that it will be added. Signed-off-by: Chris Boot Signed-off-by: Simon Arlott Signed-off-by: Dom Cobley Signed-off-by: Dom Cobley Signed-off-by: Stephen Warren Acked-by: Arnd Bergmann --- arch/arm/boot/dts/bcm2835.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index e7471d271e0f..0b619398532c 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -6,7 +6,7 @@ interrupt-parent = <&intc>; chosen { - bootargs = "earlyprintk"; + bootargs = "earlyprintk console=ttyAMA0"; }; soc { @@ -28,5 +28,12 @@ interrupt-controller; #interrupt-cells = <2>; }; + + uart@20201000 { + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x1000>; + interrupts = <2 25>; + clock-frequency = <3000000>; + }; }; }; -- cgit v1.2.1 From d582cb0bef9d9556ba2a06b2fb9c3ebb5274668c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 30 Jul 2012 09:34:46 +0100 Subject: ARM: ux500: Rename db8500.dtsi to dbx5x0.dtsi to encompass the u9500, u8540 and u9540 Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/db8500.dtsi | 592 ----------------------------------------- arch/arm/boot/dts/dbx5x0.dtsi | 592 +++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/snowball.dts | 2 +- 3 files changed, 593 insertions(+), 593 deletions(-) delete mode 100644 arch/arm/boot/dts/db8500.dtsi create mode 100644 arch/arm/boot/dts/dbx5x0.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi deleted file mode 100644 index 3180a9c588b9..000000000000 --- a/arch/arm/boot/dts/db8500.dtsi +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Copyright 2012 Linaro Ltd - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/include/ "skeleton.dtsi" - -/ { - soc-u9500 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "stericsson,db8500"; - interrupt-parent = <&intc>; - ranges; - - intc: interrupt-controller@a0411000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0xa0411000 0x1000>, - <0xa0410100 0x100>; - }; - - L2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xa0412000 0x1000>; - interrupts = <0 13 4>; - cache-unified; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 7 0x4>; - }; - - timer@a0410600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xa0410600 0x20>; - interrupts = <1 13 0x304>; - }; - - rtc@80154000 { - compatible = "arm,rtc-pl031", "arm,primecell"; - reg = <0x80154000 0x1000>; - interrupts = <0 18 0x4>; - }; - - gpio0: gpio@8012e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8012e000 0x80>; - interrupts = <0 119 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <0>; - }; - - gpio1: gpio@8012e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8012e080 0x80>; - interrupts = <0 120 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <1>; - }; - - gpio2: gpio@8000e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e000 0x80>; - interrupts = <0 121 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <2>; - }; - - gpio3: gpio@8000e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e080 0x80>; - interrupts = <0 122 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <3>; - }; - - gpio4: gpio@8000e100 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e100 0x80>; - interrupts = <0 123 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <4>; - }; - - gpio5: gpio@8000e180 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8000e180 0x80>; - interrupts = <0 124 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <5>; - }; - - gpio6: gpio@8011e000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8011e000 0x80>; - interrupts = <0 125 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <6>; - }; - - gpio7: gpio@8011e080 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0x8011e080 0x80>; - interrupts = <0 126 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <7>; - }; - - gpio8: gpio@a03fe000 { - compatible = "stericsson,db8500-gpio", - "st,nomadik-gpio"; - reg = <0xa03fe000 0x80>; - interrupts = <0 127 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - st,supports-sleepmode; - gpio-controller; - #gpio-cells = <2>; - gpio-bank = <8>; - }; - - pinctrl { - compatible = "stericsson,nmk_pinctrl"; - }; - - usb@a03e0000 { - compatible = "stericsson,db8500-musb", - "mentor,musb"; - reg = <0xa03e0000 0x10000>; - interrupts = <0 23 0x4>; - }; - - dma-controller@801C0000 { - compatible = "stericsson,db8500-dma40", - "stericsson,dma40"; - reg = <0x801C0000 0x1000 0x40010000 0x800>; - interrupts = <0 25 0x4>; - }; - - prcmu@80157000 { - compatible = "stericsson,db8500-prcmu"; - reg = <0x80157000 0x1000>; - interrupts = <0 47 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - prcmu-timer-4@80157450 { - compatible = "stericsson,db8500-prcmu-timer-4"; - reg = <0x80157450 0xC>; - }; - - db8500-prcmu-regulators { - compatible = "stericsson,db8500-prcmu-regulator"; - - // DB8500_REGULATOR_VAPE - db8500_vape_reg: db8500_vape { - regulator-compatible = "db8500_vape"; - regulator-name = "db8500-vape"; - regulator-always-on; - }; - - // DB8500_REGULATOR_VARM - db8500_varm_reg: db8500_varm { - regulator-compatible = "db8500_varm"; - regulator-name = "db8500-varm"; - }; - - // DB8500_REGULATOR_VMODEM - db8500_vmodem_reg: db8500_vmodem { - regulator-compatible = "db8500_vmodem"; - regulator-name = "db8500-vmodem"; - }; - - // DB8500_REGULATOR_VPLL - db8500_vpll_reg: db8500_vpll { - regulator-compatible = "db8500_vpll"; - regulator-name = "db8500-vpll"; - }; - - // DB8500_REGULATOR_VSMPS1 - db8500_vsmps1_reg: db8500_vsmps1 { - regulator-compatible = "db8500_vsmps1"; - regulator-name = "db8500-vsmps1"; - }; - - // DB8500_REGULATOR_VSMPS2 - db8500_vsmps2_reg: db8500_vsmps2 { - regulator-compatible = "db8500_vsmps2"; - regulator-name = "db8500-vsmps2"; - }; - - // DB8500_REGULATOR_VSMPS3 - db8500_vsmps3_reg: db8500_vsmps3 { - regulator-compatible = "db8500_vsmps3"; - regulator-name = "db8500-vsmps3"; - }; - - // DB8500_REGULATOR_VRF1 - db8500_vrf1_reg: db8500_vrf1 { - regulator-compatible = "db8500_vrf1"; - regulator-name = "db8500-vrf1"; - }; - - // DB8500_REGULATOR_SWITCH_SVAMMDSP - db8500_sva_mmdsp_reg: db8500_sva_mmdsp { - regulator-compatible = "db8500_sva_mmdsp"; - regulator-name = "db8500-sva-mmdsp"; - }; - - // DB8500_REGULATOR_SWITCH_SVAMMDSPRET - db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { - regulator-compatible = "db8500_sva_mmdsp_ret"; - regulator-name = "db8500-sva-mmdsp-ret"; - }; - - // DB8500_REGULATOR_SWITCH_SVAPIPE - db8500_sva_pipe_reg: db8500_sva_pipe { - regulator-compatible = "db8500_sva_pipe"; - regulator-name = "db8500_sva_pipe"; - }; - - // DB8500_REGULATOR_SWITCH_SIAMMDSP - db8500_sia_mmdsp_reg: db8500_sia_mmdsp { - regulator-compatible = "db8500_sia_mmdsp"; - regulator-name = "db8500_sia_mmdsp"; - }; - - // DB8500_REGULATOR_SWITCH_SIAMMDSPRET - db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { - regulator-name = "db8500-sia-mmdsp-ret"; - }; - - // DB8500_REGULATOR_SWITCH_SIAPIPE - db8500_sia_pipe_reg: db8500_sia_pipe { - regulator-compatible = "db8500_sia_pipe"; - regulator-name = "db8500-sia-pipe"; - }; - - // DB8500_REGULATOR_SWITCH_SGA - db8500_sga_reg: db8500_sga { - regulator-compatible = "db8500_sga"; - regulator-name = "db8500-sga"; - vin-supply = <&db8500_vape_reg>; - }; - - // DB8500_REGULATOR_SWITCH_B2R2_MCDE - db8500_b2r2_mcde_reg: db8500_b2r2_mcde { - regulator-compatible = "db8500_b2r2_mcde"; - regulator-name = "db8500-b2r2-mcde"; - vin-supply = <&db8500_vape_reg>; - }; - - // DB8500_REGULATOR_SWITCH_ESRAM12 - db8500_esram12_reg: db8500_esram12 { - regulator-compatible = "db8500_esram12"; - regulator-name = "db8500-esram12"; - }; - - // DB8500_REGULATOR_SWITCH_ESRAM12RET - db8500_esram12_ret_reg: db8500_esram12_ret { - regulator-compatible = "db8500_esram12_ret"; - regulator-name = "db8500-esram12-ret"; - }; - - // DB8500_REGULATOR_SWITCH_ESRAM34 - db8500_esram34_reg: db8500_esram34 { - regulator-compatible = "db8500_esram34"; - regulator-name = "db8500-esram34"; - }; - - // DB8500_REGULATOR_SWITCH_ESRAM34RET - db8500_esram34_ret_reg: db8500_esram34_ret { - regulator-compatible = "db8500_esram34_ret"; - regulator-name = "db8500-esram34-ret"; - }; - }; - - ab8500@5 { - compatible = "stericsson,ab8500"; - reg = <5>; /* mailbox 5 is i2c */ - interrupts = <0 40 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - - ab8500-rtc { - compatible = "stericsson,ab8500-rtc"; - interrupts = <17 0x4 - 18 0x4>; - interrupt-names = "60S", "ALARM"; - }; - - ab8500-gpadc { - compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 0x4 - 39 0x4>; - interrupt-names = "HW_CONV_END", "SW_CONV_END"; - vddadc-supply = <&ab8500_ldo_tvout_reg>; - }; - - ab8500-usb { - compatible = "stericsson,ab8500-usb"; - interrupts = < 90 0x4 - 96 0x4 - 14 0x4 - 15 0x4 - 79 0x4 - 74 0x4 - 75 0x4>; - interrupt-names = "ID_WAKEUP_R", - "ID_WAKEUP_F", - "VBUS_DET_F", - "VBUS_DET_R", - "USB_LINK_STATUS", - "USB_ADP_PROBE_PLUG", - "USB_ADP_PROBE_UNPLUG"; - vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; - v-ape-supply = <&db8500_vape_reg>; - musb_1v8-supply = <&db8500_vsmps2_reg>; - }; - - ab8500-ponkey { - compatible = "stericsson,ab8500-ponkey"; - interrupts = <6 0x4 - 7 0x4>; - interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; - }; - - ab8500-sysctrl { - compatible = "stericsson,ab8500-sysctrl"; - }; - - ab8500-pwm { - compatible = "stericsson,ab8500-pwm"; - }; - - ab8500-debugfs { - compatible = "stericsson,ab8500-debug"; - }; - - ab8500-regulators { - compatible = "stericsson,ab8500-regulator"; - - // supplies to the display/camera - ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-compatible = "ab8500_ldo_aux1"; - regulator-name = "V-DISPLAY"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - /* BUG: If turned off MMC will be affected. */ - regulator-always-on; - }; - - // supplies to the on-board eMMC - ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { - regulator-compatible = "ab8500_ldo_aux2"; - regulator-name = "V-eMMC1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - // supply for VAUX3; SDcard slots - ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { - regulator-compatible = "ab8500_ldo_aux3"; - regulator-name = "V-MMC-SD"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <3300000>; - }; - - // supply for v-intcore12; VINTCORE12 LDO - ab8500_ldo_initcore_reg: ab8500_ldo_initcore { - regulator-compatible = "ab8500_ldo_initcore"; - regulator-name = "V-INTCORE"; - }; - - // supply for tvout; gpadc; TVOUT LDO - ab8500_ldo_tvout_reg: ab8500_ldo_tvout { - regulator-compatible = "ab8500_ldo_tvout"; - regulator-name = "V-TVOUT"; - }; - - // supply for ab8500-usb; USB LDO - ab8500_ldo_usb_reg: ab8500_ldo_usb { - regulator-compatible = "ab8500_ldo_usb"; - regulator-name = "dummy"; - }; - - // supply for ab8500-vaudio; VAUDIO LDO - ab8500_ldo_audio_reg: ab8500_ldo_audio { - regulator-compatible = "ab8500_ldo_audio"; - regulator-name = "V-AUD"; - }; - - // supply for v-anamic1 VAMic1-LDO - ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { - regulator-compatible = "ab8500_ldo_anamic1"; - regulator-name = "V-AMIC1"; - }; - - // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { - regulator-compatible = "ab8500_ldo_amamic2"; - regulator-name = "V-AMIC2"; - }; - - // supply for v-dmic; VDMIC LDO - ab8500_ldo_dmic_reg: ab8500_ldo_dmic { - regulator-compatible = "ab8500_ldo_dmic"; - regulator-name = "V-DMIC"; - }; - - // supply for U8500 CSI/DSI; VANA LDO - ab8500_ldo_ana_reg: ab8500_ldo_ana { - regulator-compatible = "ab8500_ldo_ana"; - regulator-name = "V-CSI/DSI"; - }; - }; - }; - }; - - i2c@80004000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; - reg = <0x80004000 0x1000>; - interrupts = <0 21 0x4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@80122000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; - reg = <0x80122000 0x1000>; - interrupts = <0 22 0x4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@80128000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; - reg = <0x80128000 0x1000>; - interrupts = <0 55 0x4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@80110000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; - reg = <0x80110000 0x1000>; - interrupts = <0 12 0x4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@8012a000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; - reg = <0x8012a000 0x1000>; - interrupts = <0 51 0x4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ssp@80002000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <80002000 0x1000>; - interrupts = <0 14 0x4>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - // Add one of these for each child device - cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4 - &gpio6 22 0x4 &gpio7 0 0x4>; - - }; - - uart@80120000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80120000 0x1000>; - interrupts = <0 11 0x4>; - status = "disabled"; - }; - uart@80121000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80121000 0x1000>; - interrupts = <0 19 0x4>; - status = "disabled"; - }; - uart@80007000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x80007000 0x1000>; - interrupts = <0 26 0x4>; - status = "disabled"; - }; - - sdi@80126000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80126000 0x1000>; - interrupts = <0 60 0x4>; - status = "disabled"; - }; - sdi@80118000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80118000 0x1000>; - interrupts = <0 50 0x4>; - status = "disabled"; - }; - sdi@80005000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80005000 0x1000>; - interrupts = <0 41 0x4>; - status = "disabled"; - }; - sdi@80119000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80119000 0x1000>; - interrupts = <0 59 0x4>; - status = "disabled"; - }; - sdi@80114000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80114000 0x1000>; - interrupts = <0 99 0x4>; - status = "disabled"; - }; - sdi@80008000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x80114000 0x1000>; - interrupts = <0 100 0x4>; - status = "disabled"; - }; - - external-bus@50000000 { - compatible = "simple-bus"; - reg = <0x50000000 0x4000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50000000 0x4000000>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi new file mode 100644 index 000000000000..3180a9c588b9 --- /dev/null +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -0,0 +1,592 @@ +/* + * Copyright 2012 Linaro Ltd + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + soc-u9500 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "stericsson,db8500"; + interrupt-parent = <&intc>; + ranges; + + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xa0412000 0x1000>; + interrupts = <0 13 4>; + cache-unified; + cache-level = <2>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 7 0x4>; + }; + + timer@a0410600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xa0410600 0x20>; + interrupts = <1 13 0x304>; + }; + + rtc@80154000 { + compatible = "arm,rtc-pl031", "arm,primecell"; + reg = <0x80154000 0x1000>; + interrupts = <0 18 0x4>; + }; + + gpio0: gpio@8012e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8012e000 0x80>; + interrupts = <0 119 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <0>; + }; + + gpio1: gpio@8012e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8012e080 0x80>; + interrupts = <0 120 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <1>; + }; + + gpio2: gpio@8000e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e000 0x80>; + interrupts = <0 121 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <2>; + }; + + gpio3: gpio@8000e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e080 0x80>; + interrupts = <0 122 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <3>; + }; + + gpio4: gpio@8000e100 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e100 0x80>; + interrupts = <0 123 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <4>; + }; + + gpio5: gpio@8000e180 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8000e180 0x80>; + interrupts = <0 124 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <5>; + }; + + gpio6: gpio@8011e000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8011e000 0x80>; + interrupts = <0 125 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <6>; + }; + + gpio7: gpio@8011e080 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0x8011e080 0x80>; + interrupts = <0 126 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <7>; + }; + + gpio8: gpio@a03fe000 { + compatible = "stericsson,db8500-gpio", + "st,nomadik-gpio"; + reg = <0xa03fe000 0x80>; + interrupts = <0 127 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + st,supports-sleepmode; + gpio-controller; + #gpio-cells = <2>; + gpio-bank = <8>; + }; + + pinctrl { + compatible = "stericsson,nmk_pinctrl"; + }; + + usb@a03e0000 { + compatible = "stericsson,db8500-musb", + "mentor,musb"; + reg = <0xa03e0000 0x10000>; + interrupts = <0 23 0x4>; + }; + + dma-controller@801C0000 { + compatible = "stericsson,db8500-dma40", + "stericsson,dma40"; + reg = <0x801C0000 0x1000 0x40010000 0x800>; + interrupts = <0 25 0x4>; + }; + + prcmu@80157000 { + compatible = "stericsson,db8500-prcmu"; + reg = <0x80157000 0x1000>; + interrupts = <0 47 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + prcmu-timer-4@80157450 { + compatible = "stericsson,db8500-prcmu-timer-4"; + reg = <0x80157450 0xC>; + }; + + db8500-prcmu-regulators { + compatible = "stericsson,db8500-prcmu-regulator"; + + // DB8500_REGULATOR_VAPE + db8500_vape_reg: db8500_vape { + regulator-compatible = "db8500_vape"; + regulator-name = "db8500-vape"; + regulator-always-on; + }; + + // DB8500_REGULATOR_VARM + db8500_varm_reg: db8500_varm { + regulator-compatible = "db8500_varm"; + regulator-name = "db8500-varm"; + }; + + // DB8500_REGULATOR_VMODEM + db8500_vmodem_reg: db8500_vmodem { + regulator-compatible = "db8500_vmodem"; + regulator-name = "db8500-vmodem"; + }; + + // DB8500_REGULATOR_VPLL + db8500_vpll_reg: db8500_vpll { + regulator-compatible = "db8500_vpll"; + regulator-name = "db8500-vpll"; + }; + + // DB8500_REGULATOR_VSMPS1 + db8500_vsmps1_reg: db8500_vsmps1 { + regulator-compatible = "db8500_vsmps1"; + regulator-name = "db8500-vsmps1"; + }; + + // DB8500_REGULATOR_VSMPS2 + db8500_vsmps2_reg: db8500_vsmps2 { + regulator-compatible = "db8500_vsmps2"; + regulator-name = "db8500-vsmps2"; + }; + + // DB8500_REGULATOR_VSMPS3 + db8500_vsmps3_reg: db8500_vsmps3 { + regulator-compatible = "db8500_vsmps3"; + regulator-name = "db8500-vsmps3"; + }; + + // DB8500_REGULATOR_VRF1 + db8500_vrf1_reg: db8500_vrf1 { + regulator-compatible = "db8500_vrf1"; + regulator-name = "db8500-vrf1"; + }; + + // DB8500_REGULATOR_SWITCH_SVAMMDSP + db8500_sva_mmdsp_reg: db8500_sva_mmdsp { + regulator-compatible = "db8500_sva_mmdsp"; + regulator-name = "db8500-sva-mmdsp"; + }; + + // DB8500_REGULATOR_SWITCH_SVAMMDSPRET + db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { + regulator-compatible = "db8500_sva_mmdsp_ret"; + regulator-name = "db8500-sva-mmdsp-ret"; + }; + + // DB8500_REGULATOR_SWITCH_SVAPIPE + db8500_sva_pipe_reg: db8500_sva_pipe { + regulator-compatible = "db8500_sva_pipe"; + regulator-name = "db8500_sva_pipe"; + }; + + // DB8500_REGULATOR_SWITCH_SIAMMDSP + db8500_sia_mmdsp_reg: db8500_sia_mmdsp { + regulator-compatible = "db8500_sia_mmdsp"; + regulator-name = "db8500_sia_mmdsp"; + }; + + // DB8500_REGULATOR_SWITCH_SIAMMDSPRET + db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { + regulator-name = "db8500-sia-mmdsp-ret"; + }; + + // DB8500_REGULATOR_SWITCH_SIAPIPE + db8500_sia_pipe_reg: db8500_sia_pipe { + regulator-compatible = "db8500_sia_pipe"; + regulator-name = "db8500-sia-pipe"; + }; + + // DB8500_REGULATOR_SWITCH_SGA + db8500_sga_reg: db8500_sga { + regulator-compatible = "db8500_sga"; + regulator-name = "db8500-sga"; + vin-supply = <&db8500_vape_reg>; + }; + + // DB8500_REGULATOR_SWITCH_B2R2_MCDE + db8500_b2r2_mcde_reg: db8500_b2r2_mcde { + regulator-compatible = "db8500_b2r2_mcde"; + regulator-name = "db8500-b2r2-mcde"; + vin-supply = <&db8500_vape_reg>; + }; + + // DB8500_REGULATOR_SWITCH_ESRAM12 + db8500_esram12_reg: db8500_esram12 { + regulator-compatible = "db8500_esram12"; + regulator-name = "db8500-esram12"; + }; + + // DB8500_REGULATOR_SWITCH_ESRAM12RET + db8500_esram12_ret_reg: db8500_esram12_ret { + regulator-compatible = "db8500_esram12_ret"; + regulator-name = "db8500-esram12-ret"; + }; + + // DB8500_REGULATOR_SWITCH_ESRAM34 + db8500_esram34_reg: db8500_esram34 { + regulator-compatible = "db8500_esram34"; + regulator-name = "db8500-esram34"; + }; + + // DB8500_REGULATOR_SWITCH_ESRAM34RET + db8500_esram34_ret_reg: db8500_esram34_ret { + regulator-compatible = "db8500_esram34_ret"; + regulator-name = "db8500-esram34-ret"; + }; + }; + + ab8500@5 { + compatible = "stericsson,ab8500"; + reg = <5>; /* mailbox 5 is i2c */ + interrupts = <0 40 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 0x4 + 18 0x4>; + interrupt-names = "60S", "ALARM"; + }; + + ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <32 0x4 + 39 0x4>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + }; + + ab8500-usb { + compatible = "stericsson,ab8500-usb"; + interrupts = < 90 0x4 + 96 0x4 + 14 0x4 + 15 0x4 + 79 0x4 + 74 0x4 + 75 0x4>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + }; + + ab8500-ponkey { + compatible = "stericsson,ab8500-ponkey"; + interrupts = <6 0x4 + 7 0x4>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + + ab8500-pwm { + compatible = "stericsson,ab8500-pwm"; + }; + + ab8500-debugfs { + compatible = "stericsson,ab8500-debug"; + }; + + ab8500-regulators { + compatible = "stericsson,ab8500-regulator"; + + // supplies to the display/camera + ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { + regulator-compatible = "ab8500_ldo_aux1"; + regulator-name = "V-DISPLAY"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + /* BUG: If turned off MMC will be affected. */ + regulator-always-on; + }; + + // supplies to the on-board eMMC + ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { + regulator-compatible = "ab8500_ldo_aux2"; + regulator-name = "V-eMMC1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + // supply for VAUX3; SDcard slots + ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { + regulator-compatible = "ab8500_ldo_aux3"; + regulator-name = "V-MMC-SD"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + // supply for v-intcore12; VINTCORE12 LDO + ab8500_ldo_initcore_reg: ab8500_ldo_initcore { + regulator-compatible = "ab8500_ldo_initcore"; + regulator-name = "V-INTCORE"; + }; + + // supply for tvout; gpadc; TVOUT LDO + ab8500_ldo_tvout_reg: ab8500_ldo_tvout { + regulator-compatible = "ab8500_ldo_tvout"; + regulator-name = "V-TVOUT"; + }; + + // supply for ab8500-usb; USB LDO + ab8500_ldo_usb_reg: ab8500_ldo_usb { + regulator-compatible = "ab8500_ldo_usb"; + regulator-name = "dummy"; + }; + + // supply for ab8500-vaudio; VAUDIO LDO + ab8500_ldo_audio_reg: ab8500_ldo_audio { + regulator-compatible = "ab8500_ldo_audio"; + regulator-name = "V-AUD"; + }; + + // supply for v-anamic1 VAMic1-LDO + ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { + regulator-compatible = "ab8500_ldo_anamic1"; + regulator-name = "V-AMIC1"; + }; + + // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 + ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + regulator-compatible = "ab8500_ldo_amamic2"; + regulator-name = "V-AMIC2"; + }; + + // supply for v-dmic; VDMIC LDO + ab8500_ldo_dmic_reg: ab8500_ldo_dmic { + regulator-compatible = "ab8500_ldo_dmic"; + regulator-name = "V-DMIC"; + }; + + // supply for U8500 CSI/DSI; VANA LDO + ab8500_ldo_ana_reg: ab8500_ldo_ana { + regulator-compatible = "ab8500_ldo_ana"; + regulator-name = "V-CSI/DSI"; + }; + }; + }; + }; + + i2c@80004000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + reg = <0x80004000 0x1000>; + interrupts = <0 21 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80122000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + reg = <0x80122000 0x1000>; + interrupts = <0 22 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80128000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + reg = <0x80128000 0x1000>; + interrupts = <0 55 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@80110000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + reg = <0x80110000 0x1000>; + interrupts = <0 12 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@8012a000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + reg = <0x8012a000 0x1000>; + interrupts = <0 51 0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + ssp@80002000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <80002000 0x1000>; + interrupts = <0 14 0x4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + // Add one of these for each child device + cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4 + &gpio6 22 0x4 &gpio7 0 0x4>; + + }; + + uart@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <0 11 0x4>; + status = "disabled"; + }; + uart@80121000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80121000 0x1000>; + interrupts = <0 19 0x4>; + status = "disabled"; + }; + uart@80007000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80007000 0x1000>; + interrupts = <0 26 0x4>; + status = "disabled"; + }; + + sdi@80126000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80126000 0x1000>; + interrupts = <0 60 0x4>; + status = "disabled"; + }; + sdi@80118000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80118000 0x1000>; + interrupts = <0 50 0x4>; + status = "disabled"; + }; + sdi@80005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80005000 0x1000>; + interrupts = <0 41 0x4>; + status = "disabled"; + }; + sdi@80119000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80119000 0x1000>; + interrupts = <0 59 0x4>; + status = "disabled"; + }; + sdi@80114000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = <0 99 0x4>; + status = "disabled"; + }; + sdi@80008000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x80114000 0x1000>; + interrupts = <0 100 0x4>; + status = "disabled"; + }; + + external-bus@50000000 { + compatible = "simple-bus"; + reg = <0x50000000 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000000>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 7e334d4cae21..df6fc577f0d6 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "db8500.dtsi" +/include/ "dbx5x0.dtsi" / { model = "Calao Systems Snowball platform with device tree"; -- cgit v1.2.1 From c09090bb2fa557a697636c1a5484f5b695e2f89d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 3 Aug 2012 15:42:25 +0100 Subject: ARM: ux500: Identify the PRCMU as an interrupt controller We're just about to provide the DB8500-PRCMU with its own IRQ domain, so that its subordinate drivers can use it as an interrupt controller. It's obligatory for all IRQ controllers to reference themselves as such from its own node in Device Tree. This patch does just that. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/dbx5x0.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 3180a9c588b9..04cd525eb870 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -194,6 +194,8 @@ interrupts = <0 47 0x4>; #address-cells = <1>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; ranges; prcmu-timer-4@80157450 { -- cgit v1.2.1 From 8d4c6d45bcdde7e9294ead322c5348873430003d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 3 Aug 2012 20:37:35 +0100 Subject: ARM: ux500: Force AB8500 to use the GIC as its interrupt controller It's understood that the AB8500 should be subordinate to the DB8500; however, the AB8500 uses the GIC as it's interrupt controller. If we do not specify which IRQ controller to use the default is to use the next encountered IRQ controller as we climb the tree. This would be the DB8500. This patch ensures the AB8500 makes use of the correct interrupt controller. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/dbx5x0.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 04cd525eb870..daedefe23eab 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -332,6 +332,7 @@ ab8500@5 { compatible = "stericsson,ab8500"; reg = <5>; /* mailbox 5 is i2c */ + interrupt-parent = <&intc>; interrupts = <0 40 0x4>; interrupt-controller; #interrupt-cells = <2>; -- cgit v1.2.1 From 746307061dd8ed1c31bff94183e018be7fa03b68 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 9 Aug 2012 13:00:12 +0100 Subject: ARM: ux500: Match Power-On-Key MFD and DTS compatible strings The compatible string found in the Power-On-Key's MFD cell matches the device name provided in the driver. Keeping this naming convention seems like a good idea, so we're changing the one found in the DTS file to match. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/dbx5x0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index daedefe23eab..dc290d0b72f8 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -374,7 +374,7 @@ }; ab8500-ponkey { - compatible = "stericsson,ab8500-ponkey"; + compatible = "stericsson,ab8500-poweron-key"; interrupts = <6 0x4 7 0x4>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; -- cgit v1.2.1 From d524fa7ff674e834607fe9d6d6284a5e129762c7 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 18 Jun 2012 09:55:44 +0100 Subject: ARM: ux500: Add i2c configurations to the Device Tree for DB8500 based devices Since initial support was provided for the Nomadik I2C driver, it has been converted to an AMBA device. AMBA devices are probed in a slightly different way to other devices, so we have to identify them using an "arm,primecell" compatible string. As well as doing just that, this patch specifies which regulators the controller should use and requests a clock-speed. The latter is provided as more of an example, as it's the same as the recently changed default configuration. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/dbx5x0.dtsi | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index dc290d0b72f8..cbef6abbf907 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -474,43 +474,58 @@ }; i2c@80004000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80004000 0x1000>; interrupts = <0 21 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; i2c@80122000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80122000 0x1000>; interrupts = <0 22 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; i2c@80128000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80128000 0x1000>; interrupts = <0 55 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; i2c@80110000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80110000 0x1000>; interrupts = <0 12 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; i2c@8012a000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x8012a000 0x1000>; interrupts = <0 51 0x4>; #address-cells = <1>; #size-cells = <0>; + v-i2c-supply = <&db8500_vape_reg>; + + clock-frequency = <400000>; }; ssp@80002000 { -- cgit v1.2.1 From 6af7fd88fff48553b3afc01a75fa588cae5b8420 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 30 Aug 2012 15:53:39 +0100 Subject: ARM: ux500: Add skeleton Device Tree for the HREF reference board First commit applying the new Device Tree for ST-Ericsson's u8500 based hardware reference board. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/hrefv60plus.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/hrefv60plus.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts new file mode 100644 index 000000000000..96bf8a3af70c --- /dev/null +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -0,0 +1,26 @@ +/* + * Copyright 2012 ST-Ericsson AB + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "dbx5x0.dtsi" + +/ { + model = "ST-Ericsson HREF platform with Device Tree"; + compatible = "st-ericsson,hrefv60+"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + soc-u9500 { + + }; +}; -- cgit v1.2.1 From 9905f7c1dbfb53fe9537b0da722d1be1e956f66b Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 30 Aug 2012 15:57:31 +0100 Subject: ARM: ux500: Add UART support to the HREF Device Tree Here we add three nodes enabling UART support on the HREF hardware reference board. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/hrefv60plus.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 96bf8a3af70c..32cd7a03817d 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -21,6 +21,16 @@ }; soc-u9500 { + uart@80120000 { + status = "okay"; + }; + uart@80121000 { + status = "okay"; + }; + + uart@80007000 { + status = "okay"; + }; }; }; -- cgit v1.2.1 From 9c06af30207276a0a4bcaf8aa57521095f440383 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 25 Jul 2012 12:50:13 +0100 Subject: ARM: ux500: Add AB8500 CODEC node to DB8500 Device Tree Ensure correct probing and pass though important configuration options to the AB8500 CODEC driver when DT is enabled Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/dbx5x0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index cbef6abbf907..f055902a9b7d 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -392,6 +392,12 @@ compatible = "stericsson,ab8500-debug"; }; + codec: ab8500-codec { + compatible = "stericsson,ab8500-codec"; + + stericsson,earpeice-cmv = <950>; /* Units in mV. */ + }; + ab8500-regulators { compatible = "stericsson,ab8500-regulator"; -- cgit v1.2.1 From fe1645290872300f87bca17e90b3068fcb264089 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 31 Jul 2012 12:37:16 +0100 Subject: ARM: ux500: Add nodes for the MSP into Device Tree This patch inserts all known MSP devices into the DBx5x0 Device Tree disabled and enables the two important ones for the Snowball low-cost development board. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/dbx5x0.dtsi | 33 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/snowball.dts | 8 ++++++++ 2 files changed, 41 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index f055902a9b7d..3708a6ba7ed3 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -604,6 +604,39 @@ status = "disabled"; }; + msp0: msp@80123000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80123000 0x1000>; + interrupts = <0 31 0x4>; + v-ape-supply = <&db8500_vape_reg>; + status = "disabled"; + }; + + msp1: msp@80124000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80124000 0x1000>; + interrupts = <0 62 0x4>; + v-ape-supply = <&db8500_vape_reg>; + status = "disabled"; + }; + + // HDMI sound + msp2: msp@80117000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80117000 0x1000>; + interrupts = <0 98 0x4>; + v-ape-supply = <&db8500_vape_reg>; + status = "disabled"; + }; + + msp3: msp@80125000 { + compatible = "stericsson,ux500-msp-i2s"; + reg = <0x80125000 0x1000>; + interrupts = <0 62 0x4>; + v-ape-supply = <&db8500_vape_reg>; + status = "disabled"; + }; + external-bus@50000000 { compatible = "simple-bus"; reg = <0x50000000 0x4000000>; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index df6fc577f0d6..fce4a0067a74 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -83,6 +83,14 @@ }; soc-u9500 { + msp1: msp@80124000 { + status = "okay"; + }; + + msp3: msp@80125000 { + status = "okay"; + }; + external-bus@50000000 { status = "okay"; -- cgit v1.2.1 From e6488065cdee7ef7051e754960ba22943464b37d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 31 Jul 2012 13:31:50 +0100 Subject: ARM: ux500: Add all encompassing sound node to the Snowball Device Tree This is where we link together all of the SoC sound components for a given platform. This all encompassing sound node is only found in the very lowest hierarchical DTS file, since the component mix may well change from board variant to board variant. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/snowball.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index fce4a0067a74..29699971b5b3 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -83,6 +83,14 @@ }; soc-u9500 { + + sound { + compatible = "stericsson,snd-soc-mop500"; + + stericsson,cpu-dai = <&msp1 &msp3>; + stericsson,audio-codec = <&codec>; + }; + msp1: msp@80124000 { status = "okay"; }; -- cgit v1.2.1 From 71e8118fe722827365376a4d80faa40d939973c1 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 18 Sep 2012 17:17:38 +0200 Subject: ARM: ux500: Add all known I2C sub-device nodes to the HREF DT Here we add the skeleton nodes for each of the known I2C sub-devices currently registered on ST-Ericsson's HREF Development Platform. We will fill these nodes in turn as the drivers are enabled for Device Tree. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/hrefv60plus.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 32cd7a03817d..1d2c642fece0 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -32,5 +32,34 @@ uart@80007000 { status = "okay"; }; + + i2c@80004000 { + tc3589x@42 { + compatible = "tc3589x"; + reg = <0x42>; + }; + + tps61052@33 { + compatible = "tps61052"; + reg = <0x33>; + }; + }; + + i2c@80128000 { + lp5521@0x33 { + compatible = "lp5521"; + reg = <0x33>; + }; + + lp5521@0x34 { + compatible = "lp5521"; + reg = <0x34>; + }; + + bh1780@0x29 { + compatible = "rohm,bh1780gli"; + reg = <0x33>; + }; + }; }; }; -- cgit v1.2.1 From 301c38590d1d437dc5d3c709145998676487d2d1 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 18 Sep 2012 17:21:00 +0200 Subject: ARM: ux500: Add nodes for the MSP into the HREF Device Tree This patch enables the two important MSP devices for ST-Ericsson's hardware reference development board. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/hrefv60plus.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 1d2c642fece0..62ba5e80123d 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -61,5 +61,13 @@ reg = <0x33>; }; }; + + msp1: msp@80124000 { + status = "okay"; + }; + + msp3: msp@80125000 { + status = "okay"; + }; }; }; -- cgit v1.2.1 From 73faf2b07feeabd874790baabe80f2f59b630ee9 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 18 Sep 2012 17:22:23 +0200 Subject: ARM: ux500: Add all encompassing sound node to the HREF Device Tree This is where we link together all of the SoC sound components for a given platform. This all encompassing sound node is only found in the very lowest hierarchical DTS file, since the component mix may well change from board variant to board variant. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/hrefv60plus.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 62ba5e80123d..e853882921ec 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -62,6 +62,13 @@ }; }; + sound { + compatible = "stericsson,snd-soc-mop500"; + + stericsson,cpu-dai = <&msp1 &msp3>; + stericsson,audio-codec = <&codec>; + }; + msp1: msp@80124000 { status = "okay"; }; -- cgit v1.2.1 From 0ce89380ded57d96a9496c100e92acf55283011c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 18 Sep 2012 17:26:48 +0200 Subject: ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT This property has no place here as the populated node is not related to a GPIO controller. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/snowball.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 29699971b5b3..702c0baa6004 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -127,7 +127,6 @@ mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; - #gpio-cells = <1>; cd-gpios = <&gpio6 26 0x4>; // 218 cd-inverted; -- cgit v1.2.1 From 3cb920a15126be91de38d22d902e9cb18d3fbe49 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 19 Sep 2012 16:25:32 +0200 Subject: ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT This patch ensures the tc3589x and tc3598x-gpio devices are rightfully given interrupt controller status. We also describe the tc3598x-gpio GPIO expander in full and specify it as a GPIO controller. Finally we reference that the external MMC slot's Card Detection GPIO on the HREF is located on the tc3598x-gpio expander. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/hrefv60plus.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index e853882921ec..2131d77dc9c9 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -37,6 +37,21 @@ tc3589x@42 { compatible = "tc3589x"; reg = <0x42>; + interrupt-parent = <&gpio6>; + interrupts = <25 0x1>; + + interrupt-controller; + #interrupt-cells = <2>; + + tc3589x_gpio: tc3589x_gpio { + compatible = "tc3589x-gpio"; + interrupts = <0 0x1>; + + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; }; tps61052@33 { -- cgit v1.2.1 From c164fa62b93782165f12c0e8366f7b46507edb4d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 7 Sep 2012 12:09:34 +0100 Subject: ARM: ux500: Fix SSP register address format SSP won't probe unless the specified register address format is correct i.e. we have to specify that the address is in hex. After this patch has been applied, the SSP (SPI) driver probes as expected. Acked-by: Linus Walleij Signed-off-by: Lee Jones --- arch/arm/boot/dts/dbx5x0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 3708a6ba7ed3..748ba7aa746c 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -536,7 +536,7 @@ ssp@80002000 { compatible = "arm,pl022", "arm,primecell"; - reg = <80002000 0x1000>; + reg = <0x80002000 0x1000>; interrupts = <0 14 0x4>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.1 From 2b8b15da668be78cd80eb2ee302f777423a82f7b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Sep 2012 17:06:05 +0200 Subject: ARM: tegra: dts: Add pwm label PWM devices can be referenced in the DT by phandle and per-chip index. In order for this to work properly, the PWM controller needs to have a label attached to it. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 405d1673904e..67a6cd910b96 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -123,7 +123,7 @@ status = "disabled"; }; - pwm { + pwm: pwm { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 3e4334d14efb..b1497c7d7d68 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -117,7 +117,7 @@ status = "disabled"; }; - pwm { + pwm: pwm { compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; -- cgit v1.2.1 From 307e28ee374addbc59f0929d98a0b0d811e3323e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Sep 2012 17:06:06 +0200 Subject: ARM: tegra: Add Avionic Design Tamonten support The Tamonten is an NVIDIA Tegra2 based system-on-module (SOM) that is designed to cover a broad range of applications. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-tamonten.dtsi | 449 ++++++++++++++++++++++++++++++++ 1 file changed, 449 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-tamonten.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi new file mode 100644 index 000000000000..f18cec9f6a77 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -0,0 +1,449 @@ +/include/ "tegra20.dtsi" + +/ { + model = "Avionic Design Tamonten SOM"; + compatible = "ad,tamonten", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <0>; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = <1>; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <2>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = <0>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + status = "okay"; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + status = "okay"; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sys_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sys"; + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + regulator@1 { + reg = <1>; + regulator-compatible = "sm0"; + regulator-name = "vdd_sys_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + regulator@2 { + reg = <2>; + regulator-compatible = "sm1"; + regulator-name = "vdd_sys_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: regulator@3 { + reg = <3>; + regulator-compatible = "sm2"; + regulator-name = "vdd_sys_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + regulator@4 { + reg = <4>; + regulator-compatible = "ldo0"; + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@5 { + reg = <5>; + regulator-compatible = "ldo1"; + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + regulator@6 { + reg = <6>; + regulator-compatible = "ldo2"; + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + regulator@7 { + reg = <7>; + regulator-compatible = "ldo3"; + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator@8 { + reg = <8>; + regulator-compatible = "ldo4"; + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + regulator@9 { + reg = <9>; + regulator-compatible = "ldo5"; + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + regulator@10 { + reg = <10>; + regulator-compatible = "ldo6"; + regulator-name = "vdd_ldo6,avdd_vdac"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + regulator@11 { + reg = <11>; + regulator-compatible = "ldo7"; + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator@12 { + reg = <12>; + regulator-compatible = "ldo8"; + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + regulator@13 { + reg = <13>; + regulator-compatible = "ldo9"; + regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; + /* + * According to the Tegra 2 Automotive + * DataSheet, a typical value for this + * would be 2.8V, but the PMIC only + * supports 2.85V. + */ + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + regulator@14 { + reg = <14>; + regulator-compatible = "ldo_rtc"; + regulator-name = "vdd_rtc_out"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; + }; + + usb@c5008000 { + status = "okay"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + bus-width = <4>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; -- cgit v1.2.1 From a3ee1293b1bec15e179b5a4c99fe07157de35202 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Sep 2012 17:06:07 +0200 Subject: ARM: tegra: Add Avionic Design Plutux support The Plutux is a set-top box device based on the Tamonten SOM and can be connected to a display via HDMI. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-plutux.dts | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-plutux.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts new file mode 100644 index 000000000000..331a3ef24d59 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -0,0 +1,50 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Plutux board"; + compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + sound { + compatible = "ad,tegra-audio-plutux", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Plutux"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; -- cgit v1.2.1 From 731fb450ae029c1579dc45e559c1a778ff2f62d0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Sep 2012 17:06:08 +0200 Subject: ARM: tegra: Add Avionic Design Medcom-Wide support The Medcom is a 16:9 15" terminal that is used for patient infotainment in hospitals. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-medcom-wide.dts | 58 +++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-medcom-wide.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts new file mode 100644 index 000000000000..a2d6d6541f83 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Medcom-Wide board"; + compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + sound { + compatible = "ad,tegra-audio-wm8903-medcom-wide", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Medcom-Wide"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; -- cgit v1.2.1 From 175f16fa38977dfed9f9fe247279516ce892fb15 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Sep 2012 17:06:09 +0200 Subject: ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support The Tamonten Evaluation Carrier is an evaluation board for the Tamonten SOM. More information is available here: http://www.avionic-design.de/en/products/nvidia-tegra-tamonten-system-en/nvidia-tegra-tamonten-evboard-en.html Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-tec.dts | 53 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-tec.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts new file mode 100644 index 000000000000..9aff31b0fe4a --- /dev/null +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -0,0 +1,53 @@ +/dts-v1/; + +/include/ "tegra20-tamonten.dtsi" + +/ { + model = "Avionic Design Tamonten Evaluation Carrier"; + compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + sound { + compatible = "ad,tegra-audio-wm8903-tec", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design TEC"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + }; +}; -- cgit v1.2.1 From b571abb3b60eed1a191fd776a08d1eab71a3a428 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Fri, 21 Sep 2012 10:12:59 +0900 Subject: ARM: dts: Move parts common to EXYNOS4 from exynos4210.dtsi to exynos4.dtsi Most definitions from exynos4210.dtsi can be applied for other SoCs from EXYNOS4 line as well, so move the common part into separate file that can be included by dtsi files of other EXYNOS4 SoCs (as well as current exynos4210.dtsi). Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Acked-by: Thomas Abraham [kgene.kim@samsung.com: Dongjin Kim submitted a similar patch 'Add DTS files derived from common EXYNOS4' before this but I picked this up because of included exynos4x12 stuff] Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4.dtsi | 210 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos4210.dtsi | 181 +------------------------------- 2 files changed, 211 insertions(+), 180 deletions(-) create mode 100644 arch/arm/boot/dts/exynos4.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi new file mode 100644 index 000000000000..042fe9b8ef0c --- /dev/null +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -0,0 +1,210 @@ +/* + * Samsung's Exynos4 SoC series common device tree source + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2010-2011 Linaro Ltd. + * www.linaro.org + * + * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular + * SoCs from Exynos4 series can include this file and provide values for SoCs + * specfic bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + }; + + gic:interrupt-controller@10490000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10490000 0x1000>, <0x10480000 0x100>; + }; + + combiner:interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x10440000 0x1000>; + }; + + watchdog@10060000 { + compatible = "samsung,s3c2410-wdt"; + reg = <0x10060000 0x100>; + interrupts = <0 43 0>; + }; + + rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 44 0>, <0 45 0>; + }; + + keypad@100A0000 { + compatible = "samsung,s5pv210-keypad"; + reg = <0x100A0000 0x100>; + interrupts = <0 109 0>; + }; + + sdhci@12510000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12510000 0x100>; + interrupts = <0 73 0>; + }; + + sdhci@12520000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12520000 0x100>; + interrupts = <0 74 0>; + }; + + sdhci@12530000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12530000 0x100>; + interrupts = <0 75 0>; + }; + + sdhci@12540000 { + compatible = "samsung,exynos4210-sdhci"; + reg = <0x12540000 0x100>; + interrupts = <0 76 0>; + }; + + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 52 0>; + }; + + serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 53 0>; + }; + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 54 0>; + }; + + serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = <0 55 0>; + }; + + i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 58 0>; + }; + + i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 59 0>; + }; + + i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@138A0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@138B0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@138C0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 64 0>; + }; + + i2c@138D0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 65 0>; + }; + + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = <0 66 0>; + tx-dma-channel = <&pdma0 7>; /* preliminary */ + rx-dma-channel = <&pdma0 6>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = <0 67 0>; + tx-dma-channel = <&pdma1 7>; /* preliminary */ + rx-dma-channel = <&pdma1 6>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_2: spi@13940000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13940000 0x100>; + interrupts = <0 68 0>; + tx-dma-channel = <&pdma0 9>; /* preliminary */ + rx-dma-channel = <&pdma0 8>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 35 0>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 36 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 02891fe876e4..c71db9ccf0cd 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -19,201 +19,22 @@ * published by the Free Software Foundation. */ -/include/ "skeleton.dtsi" +/include/ "exynos4.dtsi" / { compatible = "samsung,exynos4210"; - interrupt-parent = <&gic>; - - aliases { - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - }; gic:interrupt-controller@10490000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; cpu-offset = <0x8000>; - reg = <0x10490000 0x1000>, <0x10480000 0x100>; }; combiner:interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x10440000 0x1000>; interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; }; - watchdog@10060000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x10060000 0x100>; - interrupts = <0 43 0>; - }; - - rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10070000 0x100>; - interrupts = <0 44 0>, <0 45 0>; - }; - - keypad@100A0000 { - compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; - interrupts = <0 109 0>; - }; - - sdhci@12510000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12510000 0x100>; - interrupts = <0 73 0>; - }; - - sdhci@12520000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12520000 0x100>; - interrupts = <0 74 0>; - }; - - sdhci@12530000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12530000 0x100>; - interrupts = <0 75 0>; - }; - - sdhci@12540000 { - compatible = "samsung,exynos4210-sdhci"; - reg = <0x12540000 0x100>; - interrupts = <0 76 0>; - }; - - serial@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 52 0>; - }; - - serial@13810000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13810000 0x100>; - interrupts = <0 53 0>; - }; - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - }; - - serial@13830000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13830000 0x100>; - interrupts = <0 55 0>; - }; - - i2c@13860000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x13860000 0x100>; - interrupts = <0 58 0>; - }; - - i2c@13870000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x13870000 0x100>; - interrupts = <0 59 0>; - }; - - i2c@13880000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x13880000 0x100>; - interrupts = <0 60 0>; - }; - - i2c@13890000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x13890000 0x100>; - interrupts = <0 61 0>; - }; - - i2c@138A0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; - interrupts = <0 62 0>; - }; - - i2c@138B0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; - interrupts = <0 63 0>; - }; - - i2c@138C0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; - interrupts = <0 64 0>; - }; - - i2c@138D0000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; - interrupts = <0 65 0>; - }; - - spi_0: spi@13920000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13920000 0x100>; - interrupts = <0 66 0>; - tx-dma-channel = <&pdma0 7>; /* preliminary */ - rx-dma-channel = <&pdma0 6>; /* preliminary */ - #address-cells = <1>; - #size-cells = <0>; - }; - - spi_1: spi@13930000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13930000 0x100>; - interrupts = <0 67 0>; - tx-dma-channel = <&pdma1 7>; /* preliminary */ - rx-dma-channel = <&pdma1 6>; /* preliminary */ - #address-cells = <1>; - #size-cells = <0>; - }; - - spi_2: spi@13940000 { - compatible = "samsung,exynos4210-spi"; - reg = <0x13940000 0x100>; - interrupts = <0 68 0>; - tx-dma-channel = <&pdma0 9>; /* preliminary */ - rx-dma-channel = <&pdma0 8>; /* preliminary */ - #address-cells = <1>; - #size-cells = <0>; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,amba-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma0: pdma@12680000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12680000 0x1000>; - interrupts = <0 35 0>; - }; - - pdma1: pdma@12690000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x12690000 0x1000>; - interrupts = <0 36 0>; - }; - }; - gpio-controllers { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.1 From c9e23f00cdd1b18955a50ff9fa3d51b5a28498d0 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Fri, 21 Sep 2012 10:13:31 +0900 Subject: ARM: dts: Assume status of all optional nodes as disabled for exynos4 Currently all boards must explicitly disable all unused device tree nodes of unused components (e.g. i2c, sdhci, etc...). This makes it necessary to all boards to be aware of all components on the SoC, which in turns makes board dts files longer and more difficult to maintain (e.g. adding new components to SoC-level tree requires adding nodes with status="disabled" to every board). This patch changes "status" of all optional components in SoC-level dts file to "disabled", adds status="okay" to respective nodes of used components in dts of all boards and removes all nodes with only status="disabled" from boards dts. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Acked-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4.dtsi | 22 ++++++++++++ arch/arm/boot/dts/exynos4210-origen.dts | 58 ++----------------------------- arch/arm/boot/dts/exynos4210-smdkv310.dts | 52 +++------------------------ 3 files changed, 28 insertions(+), 104 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 042fe9b8ef0c..9a19691a51fe 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -48,114 +48,133 @@ compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; interrupts = <0 43 0>; + status = "disabled"; }; rtc@10070000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 44 0>, <0 45 0>; + status = "disabled"; }; keypad@100A0000 { compatible = "samsung,s5pv210-keypad"; reg = <0x100A0000 0x100>; interrupts = <0 109 0>; + status = "disabled"; }; sdhci@12510000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; interrupts = <0 73 0>; + status = "disabled"; }; sdhci@12520000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; interrupts = <0 74 0>; + status = "disabled"; }; sdhci@12530000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; interrupts = <0 75 0>; + status = "disabled"; }; sdhci@12540000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; interrupts = <0 76 0>; + status = "disabled"; }; serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; interrupts = <0 52 0>; + status = "disabled"; }; serial@13810000 { compatible = "samsung,exynos4210-uart"; reg = <0x13810000 0x100>; interrupts = <0 53 0>; + status = "disabled"; }; serial@13820000 { compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; interrupts = <0 54 0>; + status = "disabled"; }; serial@13830000 { compatible = "samsung,exynos4210-uart"; reg = <0x13830000 0x100>; interrupts = <0 55 0>; + status = "disabled"; }; i2c@13860000 { compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; interrupts = <0 58 0>; + status = "disabled"; }; i2c@13870000 { compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; interrupts = <0 59 0>; + status = "disabled"; }; i2c@13880000 { compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; interrupts = <0 60 0>; + status = "disabled"; }; i2c@13890000 { compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; interrupts = <0 61 0>; + status = "disabled"; }; i2c@138A0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; interrupts = <0 62 0>; + status = "disabled"; }; i2c@138B0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; interrupts = <0 63 0>; + status = "disabled"; }; i2c@138C0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; interrupts = <0 64 0>; + status = "disabled"; }; i2c@138D0000 { compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; interrupts = <0 65 0>; + status = "disabled"; }; spi_0: spi@13920000 { @@ -166,6 +185,7 @@ rx-dma-channel = <&pdma0 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; spi_1: spi@13930000 { @@ -176,6 +196,7 @@ rx-dma-channel = <&pdma1 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; spi_2: spi@13940000 { @@ -186,6 +207,7 @@ rx-dma-channel = <&pdma0 8>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; amba { diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 0c49caa09978..d1a1101fd96e 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -40,6 +40,7 @@ <&gpk2 4 2 3 3>, <&gpk2 5 2 3 3>, <&gpk2 6 2 3 3>; + status = "okay"; }; sdhci@12510000 { @@ -53,6 +54,7 @@ <&gpk0 4 2 3 3>, <&gpk0 5 2 3 3>, <&gpk0 6 2 3 3>; + status = "okay"; }; gpio_keys { @@ -90,60 +92,4 @@ linux,code = <139>; }; }; - - keypad@100A0000 { - status = "disabled"; - }; - - sdhci@12520000 { - status = "disabled"; - }; - - sdhci@12540000 { - status = "disabled"; - }; - - i2c@13860000 { - status = "disabled"; - }; - - i2c@13870000 { - status = "disabled"; - }; - - i2c@13880000 { - status = "disabled"; - }; - - i2c@13890000 { - status = "disabled"; - }; - - i2c@138A0000 { - status = "disabled"; - }; - - i2c@138B0000 { - status = "disabled"; - }; - - i2c@138C0000 { - status = "disabled"; - }; - - i2c@138D0000 { - status = "disabled"; - }; - - spi_0: spi@13920000 { - status = "disabled"; - }; - - spi_1: spi@13930000 { - status = "disabled"; - }; - - spi_2: spi@13940000 { - status = "disabled"; - }; }; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 1beccc8f14ff..b87cca2fca74 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -40,6 +40,7 @@ <&gpk2 4 2 3 3>, <&gpk2 5 2 3 3>, <&gpk2 6 2 3 3>; + status = "okay"; }; keypad@100A0000 { @@ -47,6 +48,7 @@ samsung,keypad-num-columns = <8>; linux,keypad-no-autorepeat; linux,keypad-wakeup; + status = "okay"; row-gpios = <&gpx2 0 3 3 0>, <&gpx2 1 3 3 0>; @@ -128,6 +130,7 @@ samsung,i2c-max-bus-freq = <20000>; gpios = <&gpd1 0 2 3 0>, <&gpd1 1 2 3 0>; + status = "okay"; eeprom@50 { compatible = "samsung,24ad0xd1"; @@ -140,58 +143,11 @@ }; }; - sdhci@12510000 { - status = "disabled"; - }; - - sdhci@12520000 { - status = "disabled"; - }; - - sdhci@12540000 { - status = "disabled"; - }; - - i2c@13870000 { - status = "disabled"; - }; - - i2c@13880000 { - status = "disabled"; - }; - - i2c@13890000 { - status = "disabled"; - }; - - i2c@138A0000 { - status = "disabled"; - }; - - i2c@138B0000 { - status = "disabled"; - }; - - i2c@138C0000 { - status = "disabled"; - }; - - i2c@138D0000 { - status = "disabled"; - }; - - spi_0: spi@13920000 { - status = "disabled"; - }; - - spi_1: spi@13930000 { - status = "disabled"; - }; - spi_2: spi@13940000 { gpios = <&gpc1 1 5 3 0>, <&gpc1 3 5 3 0>, <&gpc1 4 5 3 0>; + status = "okay"; w25x80@0 { #address-cells = <1>; -- cgit v1.2.1 From 1b198d56d3263a15922fc3cf28af37921777ad40 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Fri, 21 Sep 2012 10:20:10 +0900 Subject: ARM: dts: Specify address and size cells for i2c controllers for EXYNOS4 Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Acked-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 9a19691a51fe..a26c3dd58269 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -122,6 +122,8 @@ }; i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; interrupts = <0 58 0>; @@ -129,6 +131,8 @@ }; i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; interrupts = <0 59 0>; @@ -136,6 +140,8 @@ }; i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; interrupts = <0 60 0>; @@ -143,6 +149,8 @@ }; i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; interrupts = <0 61 0>; @@ -150,6 +158,8 @@ }; i2c@138A0000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; interrupts = <0 62 0>; @@ -157,6 +167,8 @@ }; i2c@138B0000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; interrupts = <0 63 0>; @@ -164,6 +176,8 @@ }; i2c@138C0000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; interrupts = <0 64 0>; @@ -171,6 +185,8 @@ }; i2c@138D0000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; interrupts = <0 65 0>; -- cgit v1.2.1 From d105f0b1215dd656130671b2b02d6c376b12e9e4 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Fri, 21 Sep 2012 10:50:16 +0900 Subject: ARM: dts: Add basic dts file for Samsung Trats board This commit adds basic device tree for Exynos4210-based Trats board. Currently it provides support for eMMC over sdhci and MAX8997 PMIC. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-trats.dts | 237 +++++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4210-trats.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts new file mode 100644 index 000000000000..73567b843e72 --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -0,0 +1,237 @@ +/* + * Samsung's Exynos4210 based Trats board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Trats board which is based on + * Samsung's Exynos4210 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Samsung Trats based on Exynos4210"; + compatible = "samsung,trats", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x20000000 + 0x60000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; + }; + + vemmc_reg: voltage-regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 1 0 0>; + enable-active-high; + }; + + sdhci_emmc: sdhci@12510000 { + bus-width = <8>; + non-removable; + broken-voltage; + gpios = <&gpk0 0 2 0 3>, + <&gpk0 1 2 0 3>, + <&gpk0 3 2 2 3>, + <&gpk0 4 2 2 3>, + <&gpk0 5 2 2 3>, + <&gpk0 6 2 2 3>, + <&gpk1 3 3 3 3>, + <&gpk1 4 3 3 3>, + <&gpk1 5 3 3 3>, + <&gpk1 6 3 3 3>; + vmmc-supply = <&vemmc_reg>; + status = "okay"; + }; + + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + serial@13820000 { + status = "okay"; + }; + + serial@13830000 { + status = "okay"; + }; + + i2c@138B0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + gpios = <&gpb 6 3 3 0>, + <&gpb 7 3 3 0>; + status = "okay"; + + max8997_pmic@66 { + compatible = "maxim,max8997-pmic"; + + reg = <0x66>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 1 0 0>, + <&gpx0 6 1 0 0>, + <&gpl0 0 1 0 0>; + + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, + <950000>, <900000>, + <1100000>, <1000000>, + <950000>, <900000>; + + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + regulators { + valive_reg: LDO2 { + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vusb_reg: LDO3 { + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vmipi_reg: LDO4 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vpda_reg: LDO6 { + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcam_reg: LDO7 { + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vusbdac_reg: LDO8 { + regulator-name = "VUSB/VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccpda_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vpll_reg: LDO10 { + regulator-name = "VPLL_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcclcd_reg: LDO13 { + regulator-name = "VCC_3.3V_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vlcd_reg: LDO15 { + regulator-name = "VLCD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + }; + + camsensor_reg: LDO16 { + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddq_reg: LDO21 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + varm_breg: BUCK1 { + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vint_breg: BUCK2 { + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + camisp_breg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmem_breg: BUCK5 { + regulator-name = "VMEM_1.2V_C210"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vccsub_breg: BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + regulator-always-on; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + }; + }; + }; +}; -- cgit v1.2.1 From 3c817102ea8ee5b18c0e58785a9354fb96348823 Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Fri, 21 Sep 2012 11:04:20 +0900 Subject: ARM: dts: use uart2 for console on smdkv310 and smdk5250 Cc: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-smdkv310.dts | 2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index b87cca2fca74..63610c3ba3af 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -26,7 +26,7 @@ }; chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; sdhci@12530000 { diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 8a5e348793c7..62e1039fb30e 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200"; + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; i2c@12C60000 { -- cgit v1.2.1 From c8c24dad2349fb430641535a4f26a7a1cebb9644 Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Fri, 21 Sep 2012 11:13:25 +0900 Subject: ARM: dts: Enable on-board keys as wakeup source for exynos4210-origen On board keys on Origen board can serve as wakeup sources, hence they are marked accordingly in the device tree file. Signed-off-by: Tushar Behera Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210-origen.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index d1a1101fd96e..c525e98f4953 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -66,30 +66,35 @@ label = "Up"; gpios = <&gpx2 0 0 0 2>; linux,code = <103>; + gpio-key,wakeup; }; down { label = "Down"; gpios = <&gpx2 1 0 0 2>; linux,code = <108>; + gpio-key,wakeup; }; back { label = "Back"; gpios = <&gpx1 7 0 0 2>; linux,code = <158>; + gpio-key,wakeup; }; home { label = "Home"; gpios = <&gpx1 6 0 0 2>; linux,code = <102>; + gpio-key,wakeup; }; menu { label = "Menu"; gpios = <&gpx1 5 0 0 2>; linux,code = <139>; + gpio-key,wakeup; }; }; }; -- cgit v1.2.1 From 740418ef19fd7def7b9c333435d4ca1dce28cc42 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 20 Sep 2012 15:20:39 -0600 Subject: ARM: tegra: harmony: fix ldo7 regulator-name On Harmony, LDO7 does not feed vdd_fuse. Correct the regulator name. This issue was probably the result of copying Ventana's regulator setup when creating the Harmony .dts file. No other naming issues appear to exist. Reported-by: Thierry Reding Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index b98a1b36e694..c3ef1ad26b6a 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -397,7 +397,7 @@ regulator@11 { reg = <11>; regulator-compatible = "ldo7"; - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-name = "vdd_ldo7,avdd_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; -- cgit v1.2.1 From 85594df2bad0dddb36aa8aa242f4d15e6f122f02 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Thu, 20 Sep 2012 21:11:45 -0700 Subject: ARM: dtb: move all dtb targets to common Makefile Since the dtb targets have moved to arch/arm/boot/dts/Makefile, sweep the platforms that have had new targets added recently and move them over. While I was at it, I also made the dtb generation more generic, i.e. if the platform is enabled then all dtbs for that platform will be created. Signed-off-by: Olof Johansson Cc: Tony Lindgren Cc: David Brown Cc: Barry Song Cc: Simon Horman Cc: Rob Herring Cc: Stephen Warren --- arch/arm/boot/dts/Makefile | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index eda7b557c528..d302e6655e65 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ usb_a9260.dtb \ usb_a9263.dtb \ usb_a9g20.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos5250-smdk5250.dtb @@ -39,6 +40,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \ kirkwood-lsxhl.dtb \ kirkwood-ts219-6281.dtb \ kirkwood-ts219-6282.dtb +dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ + msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-xp-db.dtb dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ @@ -58,7 +61,20 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-evk.dtb \ imx28-m28evk.dtb \ imx28-tx28.dtb +dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ + omap3-beagle-xm.dtb \ + omap3-evm.dtb \ + omap3-tobi.dtb \ + omap4-panda.dtb \ + omap4-pandaES.dtb \ + omap4-var_som.dtb \ + omap4-sdp.dtb \ + omap5-evm.dtb +dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += snowball.dtb +dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ + r8a7740-armadillo800eva.dtb \ + sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ -- cgit v1.2.1 From cb935e71577ad0fb5babe34c5494de6a0093693d Mon Sep 17 00:00:00 2001 From: Tony Prisk Date: Fri, 3 Aug 2012 20:54:16 +1200 Subject: arm: vt8500: Add device tree files for VIA/Wondermedia SoC's Add device tree files for VT8500, WM8505 and WM8650 SoC's and reference boards. Signed-off-by: Tony Prisk --- arch/arm/boot/dts/vt8500-bv07.dts | 36 ++++++++++ arch/arm/boot/dts/vt8500.dtsi | 116 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/wm8505-ref.dts | 36 ++++++++++ arch/arm/boot/dts/wm8505.dtsi | 143 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/wm8650-mid.dts | 36 ++++++++++ arch/arm/boot/dts/wm8650.dtsi | 147 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 514 insertions(+) create mode 100644 arch/arm/boot/dts/vt8500-bv07.dts create mode 100644 arch/arm/boot/dts/vt8500.dtsi create mode 100644 arch/arm/boot/dts/wm8505-ref.dts create mode 100644 arch/arm/boot/dts/wm8505.dtsi create mode 100644 arch/arm/boot/dts/wm8650-mid.dts create mode 100644 arch/arm/boot/dts/wm8650.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts new file mode 100644 index 000000000000..567cf4e8ab84 --- /dev/null +++ b/arch/arm/boot/dts/vt8500-bv07.dts @@ -0,0 +1,36 @@ +/* + * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook + * + * Copyright (C) 2012 Tony Prisk + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "vt8500.dtsi" + +/ { + model = "Benign BV07 Netbook"; + + /* + * Display node is based on Sascha Hauer's patch on dri-devel. + * Added a bpp property to calculate the size of the framebuffer + * until the binding is formalized. + */ + display: display@0 { + modes { + mode0: mode@0 { + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + clock = <0>; /* unused but required */ + bpp = <16>; /* non-standard but required */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi new file mode 100644 index 000000000000..d8645e990b21 --- /dev/null +++ b/arch/arm/boot/dts/vt8500.dtsi @@ -0,0 +1,116 @@ +/* + * vt8500.dtsi - Device tree file for VIA VT8500 SoC + * + * Copyright (C) 2012 Tony Prisk + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "via,vt8500"; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc>; + + intc: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + gpio: gpio-controller@d8110000 { + compatible = "via,vt8500-gpio"; + gpio-controller; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <43>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <43>; + }; + + fb@d800e400 { + compatible = "via,vt8500-fb"; + reg = <0xd800e400 0x400>; + interrupts = <12>; + display = <&display>; + default-mode = <&mode0>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&ref24>; + }; + + uart@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&ref24>; + }; + + uart@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&ref24>; + }; + + uart@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&ref24>; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts new file mode 100644 index 000000000000..fd4e248074c6 --- /dev/null +++ b/arch/arm/boot/dts/wm8505-ref.dts @@ -0,0 +1,36 @@ +/* + * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook + * + * Copyright (C) 2012 Tony Prisk + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "wm8505.dtsi" + +/ { + model = "Wondermedia WM8505 Netbook"; + + /* + * Display node is based on Sascha Hauer's patch on dri-devel. + * Added a bpp property to calculate the size of the framebuffer + * until the binding is formalized. + */ + display: display@0 { + modes { + mode0: mode@0 { + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + clock = <0>; /* unused but required */ + bpp = <32>; /* non-standard but required */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi new file mode 100644 index 000000000000..b459691655ab --- /dev/null +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -0,0 +1,143 @@ +/* + * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC + * + * Copyright (C) 2012 Tony Prisk + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "wm,wm8505"; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + gpio: gpio-controller@d8110000 { + compatible = "wm,wm8505-gpio"; + gpio-controller; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007100 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007100 0x200>; + interrupts = <43>; + }; + + uhci@d8007300 { + compatible = "platform-uhci"; + reg = <0xd8007300 0x200>; + interrupts = <43>; + }; + + fb@d8050800 { + compatible = "wm,wm8505-fb"; + reg = <0xd8050800 0x200>; + display = <&display>; + default-mode = <&mode0>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&ref24>; + }; + + uart@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&ref24>; + }; + + uart@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&ref24>; + }; + + uart@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&ref24>; + }; + + uart@d8370000 { + compatible = "via,vt8500-uart"; + reg = <0xd8370000 0x1040>; + interrupts = <31>; + clocks = <&ref24>; + }; + + uart@d8380000 { + compatible = "via,vt8500-uart"; + reg = <0xd8380000 0x1040>; + interrupts = <30>; + clocks = <&ref24>; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts new file mode 100644 index 000000000000..cefd938f842f --- /dev/null +++ b/arch/arm/boot/dts/wm8650-mid.dts @@ -0,0 +1,36 @@ +/* + * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet + * + * Copyright (C) 2012 Tony Prisk + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +/include/ "wm8650.dtsi" + +/ { + model = "Wondermedia WM8650-MID Tablet"; + + /* + * Display node is based on Sascha Hauer's patch on dri-devel. + * Added a bpp property to calculate the size of the framebuffer + * until the binding is formalized. + */ + display: display@0 { + modes { + mode0: mode@0 { + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + hsync-len = <0>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <1>; + clock = <0>; /* unused but required */ + bpp = <16>; /* non-standard but required */ + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi new file mode 100644 index 000000000000..83b9467559bb --- /dev/null +++ b/arch/arm/boot/dts/wm8650.dtsi @@ -0,0 +1,147 @@ +/* + * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC + * + * Copyright (C) 2012 Tony Prisk + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "wm,wm8650"; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc0>; + + intc0: interrupt-controller@d8140000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + reg = <0xd8140000 0x10000>; + #interrupt-cells = <1>; + }; + + /* Secondary IC cascaded to intc0 */ + intc1: interrupt-controller@d8150000 { + compatible = "via,vt8500-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xD8150000 0x10000>; + interrupts = <56 57 58 59 60 61 62 63>; + }; + + gpio: gpio-controller@d8110000 { + compatible = "wm,wm8650-gpio"; + gpio-controller; + reg = <0xd8110000 0x10000>; + #gpio-cells = <3>; + }; + + pmc@d8130000 { + compatible = "via,vt8500-pmc"; + reg = <0xd8130000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref25: ref25M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + ref24: ref24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + plla: plla { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x200>; + }; + + pllb: pllb { + #clock-cells = <0>; + compatible = "wm,wm8650-pll-clock"; + clocks = <&ref25>; + reg = <0x204>; + }; + + arm: arm { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&plla>; + divisor-reg = <0x300>; + }; + + sdhc: sdhc { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&pllb>; + divisor-reg = <0x328>; + divisor-mask = <0x3f>; + enable-reg = <0x254>; + enable-bit = <18>; + }; + }; + }; + + timer@d8130100 { + compatible = "via,vt8500-timer"; + reg = <0xd8130100 0x28>; + interrupts = <36>; + }; + + ehci@d8007900 { + compatible = "via,vt8500-ehci"; + reg = <0xd8007900 0x200>; + interrupts = <43>; + }; + + uhci@d8007b00 { + compatible = "platform-uhci"; + reg = <0xd8007b00 0x200>; + interrupts = <43>; + }; + + fb@d8050800 { + compatible = "wm,wm8505-fb"; + reg = <0xd8050800 0x200>; + display = <&display>; + default-mode = <&mode0>; + }; + + ge_rops@d8050400 { + compatible = "wm,prizm-ge-rops"; + reg = <0xd8050400 0x100>; + }; + + uart@d8200000 { + compatible = "via,vt8500-uart"; + reg = <0xd8200000 0x1040>; + interrupts = <32>; + clocks = <&ref24>; + }; + + uart@d82b0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82b0000 0x1040>; + interrupts = <33>; + clocks = <&ref24>; + }; + + rtc@d8100000 { + compatible = "via,vt8500-rtc"; + reg = <0xd8100000 0x10000>; + interrupts = <48>; + }; + }; +}; -- cgit v1.2.1 From 4f48b7fc5ab6286ab4a9522928aa1acc163a4bf3 Mon Sep 17 00:00:00 2001 From: Alan M Butler Date: Mon, 20 Aug 2012 15:29:07 +0100 Subject: ARM: Kirkwood: Iomega ix2-200 DT support Add support for the Iomega ix2-200. Led's and buttons working as of kernel 3.6-rc2 the 3 lines in the network interface do seem to be required as removing either causes the network card to not be able to reach the network (at least on my device). Product page: http://go.iomega.com/en/products/network-storage-desktop/storcenter-network-storage-solution/network-hard-drive-ix2-200-cloud/?partner=4735#tech_specsItem_tab Signed-off-by: Alan M Butler Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 105 ++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts new file mode 100644 index 000000000000..865aeec40a26 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -0,0 +1,105 @@ +/dts-v1/; + +/include/ "kirkwood.dtsi" + +/ { + model = "Iomega StorCenter ix2-200"; + compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + i2c@11000 { + status = "okay"; + + lm63: lm63@4c { + compatible = "national,lm63"; + reg = <0x4c>; + }; + }; + + serial@12000 { + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x300000>; + }; + + partition@400000 { + label = "uInitrd"; + reg = <0x540000 0x1000000>; + }; + }; + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + }; + gpio-leds { + compatible = "gpio-leds"; + + power_led { + label = "status:white:power_led"; + gpios = <&gpio0 16 0>; + linux,default-trigger = "default-on"; + }; + health_led1 { + label = "status:red:health_led"; + gpios = <&gpio1 5 0>; + }; + health_led2 { + label = "status:white:health_led"; + gpios = <&gpio1 4 0>; + }; + backup_led { + label = "status:blue:backup_led"; + gpios = <&gpio0 15 0>; + }; + }; + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + Power { + label = "Power Button"; + linux,code = <116>; + gpios = <&gpio0 14 1>; + }; + Reset { + label = "Reset Button"; + linux,code = <0x198>; + gpios = <&gpio0 12 1>; + }; + OTB { + label = "OTB Button"; + linux,code = <133>; + gpios = <&gpio1 3 1>; + }; + }; +}; -- cgit v1.2.1 From 2f865c3548e78232baa3f9b41f516055cf3c4770 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Tue, 14 Aug 2012 22:43:42 +0200 Subject: ARM: kirkwood: DT descriptor for Seagate FreeAgent Dockstar This adds the corresponding device tree descriptor for the Seagate FreeAgent Dockstar based on Kirkwood DT. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-dockstar.dts | 57 +++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-dockstar.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts new file mode 100644 index 000000000000..08a582414b88 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ "kirkwood.dtsi" + +/ { + model = "Seagate FreeAgent Dockstar"; + compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + }; + + ocp@f1000000 { + serial@12000 { + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "data"; + reg = <0x0500000 0xfb00000>; + }; + }; + }; + gpio-leds { + compatible = "gpio-leds"; + + health { + label = "status:green:health"; + gpios = <&gpio1 14 1>; + linux,default-trigger = "default-on"; + }; + fault { + label = "status:orange:fault"; + gpios = <&gpio1 15 1>; + }; + }; +}; -- cgit v1.2.1 From 0510c8a014432b45f09509d1fb450922ec96b40d Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 4 Sep 2012 11:55:02 +0200 Subject: ARM: initial DTS support for km_kirkwood This is a first attempt to support the km_kirkwood reference design with a device tree. This km_kirkwood design is present in many Keymile products. It is based on the Marvell Bobcat SOC which integrates a Kirkwood CPU next to a big L2 Ethernet Switch. The Kirkwood in the SOC is very similar to the "normal" one, but there are a few differences. This initial support is minimal: the kernel can boot with network (ge0), serial port and NAND functional. Signed-off-by: Valentin Longchamp Cc: Holger Brunck Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-km_kirkwood.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts new file mode 100644 index 000000000000..75bdb93fed26 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -0,0 +1,29 @@ +/dts-v1/; + +/include/ "kirkwood.dtsi" + +/ { + model = "Keymile Kirkwood Reference Design"; + compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + ocp@f1000000 { + serial@12000 { + clock-frequency = <200000000>; + status = "ok"; + }; + + nand@3000000 { + status = "ok"; + chip-delay = <25>; + }; + }; +}; -- cgit v1.2.1 From 80a8b54b9a0ba418f25d2014b1375f9f4876eb15 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 15 Aug 2012 19:07:34 +0200 Subject: ARM: dove: add device tree descriptors This patch adds device tree decriptors for dove SoC and currently supported boards. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove-cm-a510.dts | 38 ++++++++++ arch/arm/boot/dts/dove-dove-db.dts | 38 ++++++++++ arch/arm/boot/dts/dove.dtsi | 143 +++++++++++++++++++++++++++++++++++++ 3 files changed, 219 insertions(+) create mode 100644 arch/arm/boot/dts/dove-cm-a510.dts create mode 100644 arch/arm/boot/dts/dove-dove-db.dts create mode 100644 arch/arm/boot/dts/dove.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts new file mode 100644 index 000000000000..61a8062e56de --- /dev/null +++ b/arch/arm/boot/dts/dove-cm-a510.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +/include/ "dove.dtsi" + +/ { + model = "Compulab CM-A510"; + compatible = "compulab,cm-a510", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; +}; + +&uart0 { status = "okay"; }; +&uart1 { status = "okay"; }; +&sdio0 { status = "okay"; }; +&sdio1 { status = "okay"; }; +&sata0 { status = "okay"; }; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Winbond W25Q32BV */ + spi-flash@0 { + compatible = "st,w25q32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts new file mode 100644 index 000000000000..e5a920beab45 --- /dev/null +++ b/arch/arm/boot/dts/dove-dove-db.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +/include/ "dove.dtsi" + +/ { + model = "Marvell DB-MV88AP510-BP Development Board"; + compatible = "marvell,dove-db", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; +}; + +&uart0 { status = "okay"; }; +&uart1 { status = "okay"; }; +&sdio0 { status = "okay"; }; +&sdio1 { status = "okay"; }; +&sata0 { status = "okay"; }; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash ST-M25P32-VMF6P */ + spi-flash@0 { + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi new file mode 100644 index 000000000000..96fb824b5e6e --- /dev/null +++ b/arch/arm/boot/dts/dove.dtsi @@ -0,0 +1,143 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "marvell,dove"; + model = "Marvell Armada 88AP510 SoC"; + + interrupt-parent = <&intc>; + + intc: interrupt-controller { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xf1020204 0x04>, + <0xf1020214 0x04>; + }; + + mbus@f1000000 { + compatible = "simple-bus"; + ranges = <0 0xf1000000 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <7>; + clock-frequency = <166666667>; + status = "disabled"; + }; + + uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <8>; + clock-frequency = <166666667>; + status = "disabled"; + }; + + uart2: serial@12200 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <9>; + clock-frequency = <166666667>; + status = "disabled"; + }; + + uart3: serial@12300 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <10>; + clock-frequency = <166666667>; + status = "disabled"; + }; + + wdt: wdt@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>; + }; + + gpio0: gpio@d0400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0400 0x20>; + ngpio = <32>; + interrupts = <12>, <13>, <14>, <60>; + }; + + gpio1: gpio@d0420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0420 0x20>; + ngpio = <32>; + interrupts = <61>; + }; + + gpio2: gpio@e8400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe8400 0x0c>; + ngpio = <8>; + }; + + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <6>; + reg = <0x10600 0x28>; + status = "disabled"; + }; + + spi1: spi@14600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <5>; + reg = <0x14600 0x28>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clock-frequency = <400000>; + timeout-ms = <1000>; + status = "disabled"; + }; + + sdio0: sdio@92000 { + compatible = "marvell,dove-sdhci"; + reg = <0x92000 0x100>; + interrupts = <35>, <37>; + status = "disabled"; + }; + + sdio1: sdio@90000 { + compatible = "marvell,dove-sdhci"; + reg = <0x90000 0x100>; + interrupts = <36>, <38>; + status = "disabled"; + }; + + sata0: sata@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x2400>; + interrupts = <62>; + nr-ports = <1>; + status = "disabled"; + }; + }; +}; -- cgit v1.2.1 From 1f5e6c639e25de9f059ea0e0181a5baeb3b3f4bf Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 15 Aug 2012 19:07:35 +0200 Subject: ARM: dove: SolidRun CuBox DT This patch adds basic support for the SolidRun CuBox to DT based mach-dove. There are still some issues related to ongoing orion/mvebu development, e.g. gpio-led will not work as there is no DT pinctrl for dove yet and we don't have board specific setup code. Nevertheless, the DT description is already introduced here. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove-cubox.dts | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 arch/arm/boot/dts/dove-cubox.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts new file mode 100644 index 000000000000..0adbd5a38095 --- /dev/null +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -0,0 +1,42 @@ +/dts-v1/; + +/include/ "dove.dtsi" + +/ { + model = "SolidRun CuBox"; + compatible = "solidrun,cubox", "marvell,dove"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + leds { + compatible = "gpio-leds"; + power { + label = "Power"; + gpios = <&gpio0 18 1>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&uart0 { status = "okay"; }; +&sdio0 { status = "okay"; }; +&sata0 { status = "okay"; }; +&i2c0 { status = "okay"; }; + +&spi0 { + status = "okay"; + + /* spi0.0: 4M Flash Winbond W25Q32BV */ + spi-flash@0 { + compatible = "st,w25q32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; -- cgit v1.2.1 From 5b40baee4a39d96d4d6a48a2b2383982912c429b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:30 +0200 Subject: arm: mvebu: add address decoding controller to the DT Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 6b6b932a5a7d..16cc82cdaa81 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -63,6 +63,11 @@ reg = <0xd0020300 0x30>; interrupts = <37>, <38>, <39>, <40>; }; + + addr-decoding@d0020000 { + compatible = "marvell,armada-addr-decoding-controller"; + reg = <0xd0020000 0x258>; + }; }; }; -- cgit v1.2.1 From 17ba0226b9e88cf6ee506986befadfab70ebc6c8 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Sun, 5 Aug 2012 22:39:12 +0200 Subject: ARM: Kirkwood: Describe iconnect keys in DT. Define the 2 keys found on iconnect in DT. It's also changing the keycodes/ switches to use better ones. Signed-off-by: Arnaud Patard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-iconnect.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index f8ca6fa88192..3a5219cad9fe 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -69,4 +69,22 @@ gpios = <&gpio1 16 0>; }; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + button@1 { + label = "OTB Button"; + linux,code = <133>; + gpios = <&gpio1 3 1>; + debounce-interval = <100>; + }; + button@2 { + label = "Reset"; + linux,code = <0x198>; + gpios = <&gpio0 12 1>; + debounce-interval = <100>; + }; + }; }; -- cgit v1.2.1 From 2eecb477765840c175133117010a789e58824680 Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Sun, 5 Aug 2012 22:39:13 +0200 Subject: ARM: Kirkwood: Describe iconnect nand in DT. Define the nand and its partitions in DT and remove them from cmdline Signed-off-by: Arnaud Patard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-iconnect.dts | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 3a5219cad9fe..d97cd9d4753e 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -12,7 +12,7 @@ }; chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)"; + bootargs = "console=ttyS0,115200n8 earlyprintk"; linux,initrd-start = <0x4500040>; linux,initrd-end = <0x4800000>; }; @@ -30,7 +30,37 @@ clock-frequency = <200000000>; status = "ok"; }; + + nand@3000000 { + status = "okay"; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0xc0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0xa0000 0x20000>; + }; + + partition@100000 { + label = "zImage"; + reg = <0x100000 0x300000>; + }; + + partition@540000 { + label = "initrd"; + reg = <0x540000 0x300000>; + }; + + partition@980000 { + label = "boot"; + reg = <0x980000 0x1f400000>; + }; + }; }; + gpio-leds { compatible = "gpio-leds"; -- cgit v1.2.1 From f37fbd36c5f9fe716ddf783415a67de03fb0dc3d Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Mon, 3 Sep 2012 20:29:34 +0200 Subject: Crypto: CESA: Add support for DT based instantiation. Based on work by Michael Walle and Jason Cooper. Added support for getting the interrupt number and address of SRAM from DT. Signed-off-by: Andrew Lunn Tested-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper Conflicts: arch/arm/mach-kirkwood/board-dt.c --- arch/arm/boot/dts/kirkwood.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index cef9616f330a..4e5b8154a5be 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -14,7 +14,8 @@ ocp@f1000000 { compatible = "simple-bus"; - ranges = <0 0xf1000000 0x4000000>; + ranges = <0x00000000 0xf1000000 0x4000000 + 0xf5000000 0xf5000000 0x0000400>; #address-cells = <1>; #size-cells = <1>; @@ -105,5 +106,14 @@ clock-frequency = <100000>; status = "disabled"; }; + + crypto@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>, + <0xf5000000 0x800>; + reg-names = "regs", "sram"; + interrupts = <22>; + status = "okay"; + }; }; }; -- cgit v1.2.1 From 1b90e06b14291ce3c252bd10e4ce981a08152e2e Mon Sep 17 00:00:00 2001 From: Jamie Lentin Date: Mon, 10 Sep 2012 14:51:52 +0100 Subject: ARM: kirkwood: Use devicetree to define DNS-32[05] fan Remove more board-specific code by using devicetree to define the fan attached to both boards. Signed-off-by: Jamie Lentin Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-dnskw.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 7408655f91b5..9b32d0272825 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -25,6 +25,16 @@ }; }; + gpio_fan { + /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ + compatible = "gpio-fan"; + gpios = <&gpio1 14 1 + &gpio1 13 1>; + gpio-fan,speed-map = <0 0 + 3000 1 + 6000 2>; + }; + ocp@f1000000 { sata@80000 { status = "okay"; -- cgit v1.2.1 From f3b42b7ce0e541c97548e39d5b162538ca895609 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 13 Sep 2012 17:41:48 +0200 Subject: ARM: mvebu: Add pinctrl support to Armada XP SoCs This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada XP SoCs. Until now, the device tree representation considered the Armada XP as a single SoC. But in fact, there are three different SoCs in the Armada XP families, with different number of CPU cores, different number of Ethernet interfaces... and different number of muxable pins or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for the three SoCs of the Armada XP family. The current armada-xp-db.dts evaluation board uses the MV78460 variant of the SoC. Signed-off-by: Thomas Petazzoni Acked-by: Linus Walleij Acked-by: Thomas Petazzoni Tested-by: Thomas Petazzoni Reviewed-by: Stephen Warren Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/boot/dts/armada-xp-mv78260.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/boot/dts/armada-xp-mv78460.dtsi | 28 ++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi new file mode 100644 index 000000000000..38ede3d68419 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -0,0 +1,28 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Contains definitions specific to the Armada XP MV78230 SoC that are not + * common to all Armada XP SoCs. + */ + +/include/ "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78230 SoC"; + compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + soc { + pinctrl { + compatible = "marvell,mv78230-pinctrl"; + reg = <0xd0018000 0x38>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi new file mode 100644 index 000000000000..b2eafcd2fe1b --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -0,0 +1,28 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Contains definitions specific to the Armada XP MV78260 SoC that are not + * common to all Armada XP SoCs. + */ + +/include/ "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78260 SoC"; + compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + soc { + pinctrl { + compatible = "marvell,mv78260-pinctrl"; + reg = <0xd0018000 0x38>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi new file mode 100644 index 000000000000..cf8624d3784c --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -0,0 +1,28 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Contains definitions specific to the Armada XP MV78460 SoC that are not + * common to all Armada XP SoCs. + */ + +/include/ "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP MV78460 SoC"; + compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + + soc { + pinctrl { + compatible = "marvell,mv78460-pinctrl"; + reg = <0xd0018000 0x38>; + }; + }; + }; -- cgit v1.2.1 From d81b8bafc44b369b326b02af907554769e1b1434 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 13 Sep 2012 17:41:49 +0200 Subject: ARM: mvebu: Add pinctrl support to Armada 370 SoC This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada 370 SoC. Signed-off-by: Thomas Petazzoni Acked-by: Linus Walleij Acked-by: Thomas Petazzoni Tested-by: Thomas Petazzoni Reviewed-by: Stephen Warren Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 3228ccc83332..2bfb904a8248 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -31,5 +31,10 @@ compatible = "marvell,armada-370-xp-system-controller"; reg = <0xd0018200 0x100>; }; + + pinctrl { + compatible = "marvell,mv88f6710-pinctrl"; + reg = <0xd0018000 0x38>; + }; }; }; -- cgit v1.2.1 From 0bec30a7e3c2b044d232d679b049fd0c0421ea09 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 13 Sep 2012 17:41:50 +0200 Subject: ARM: mvebu: adjust Armada XP evaluation board DTS The Armada XP evaluation board is based on the MV78460 Armava XP SoC. Now that we have separate .dtsi files for the three different SoCs of the Armada XP family, use the appropriate one as include for the Armada XP evaluation board .dts file. Signed-off-by: Thomas Petazzoni Acked-by: Linus Walleij Acked-by: Thomas Petazzoni Tested-by: Thomas Petazzoni Reviewed-by: Stephen Warren Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-db.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index f97040d4258d..b1fc728515e9 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -14,11 +14,11 @@ */ /dts-v1/; -/include/ "armada-xp.dtsi" +/include/ "armada-xp-mv78460.dtsi" / { model = "Marvell Armada XP Evaluation Board"; - compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp"; + compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { bootargs = "console=ttyS0,115200 earlyprintk"; -- cgit v1.2.1 From 397d59f3b59e32236a0b74803d636c061d537aef Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 19 Sep 2012 22:53:01 +0200 Subject: arm: mvebu: add DT information for GPIO banks on Armada 370 and XP The gpioX aliases are needed so that the driver can use of_alias_get_id() to get a 0-based number of the GPIO bank, which we then use to compute the base GPIO of the bank being probed. This is similar to what gpio-mxs.c is doing. Signed-off-by: Thomas Petazzoni Cc: Jason Cooper Cc: Andrew Lunn Cc: Gregory Clement Acked-by: Arnd Bergmann Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370.dtsi | 39 +++++++++++++++++++++++++++++ arch/arm/boot/dts/armada-xp-mv78230.dtsi | 29 ++++++++++++++++++++++ arch/arm/boot/dts/armada-xp-mv78260.dtsi | 42 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/armada-xp-mv78460.dtsi | 42 ++++++++++++++++++++++++++++++++ 4 files changed, 152 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 2bfb904a8248..2069151afe01 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -21,6 +21,12 @@ model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + mpic: interrupt-controller@d0020000 { reg = <0xd0020a00 0x1d0>, <0xd0021870 0x58>; @@ -35,6 +41,39 @@ pinctrl { compatible = "marvell,mv88f6710-pinctrl"; reg = <0xd0018000 0x38>; + }; + + gpio0: gpio@d0018100 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018140 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; + }; + + gpio2: gpio@d0018180 { + compatible = "marvell,orion-gpio"; + reg = <0xd0018180 0x40>; + ngpios = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <91>; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 38ede3d68419..ea355192be6f 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -19,10 +19,39 @@ model = "Marvell Armada XP MV78230 SoC"; compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + soc { pinctrl { compatible = "marvell,mv78230-pinctrl"; reg = <0xd0018000 0x38>; }; + + gpio0: gpio@d0018100 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018100 0x40>, + <0xd0018800 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018140 0x40>, + <0xd0018840 0x30>; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <20>, <21>, <22>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index b2eafcd2fe1b..2057863f3dfa 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -19,10 +19,52 @@ model = "Marvell Armada XP MV78260 SoC"; compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + soc { pinctrl { compatible = "marvell,mv78260-pinctrl"; reg = <0xd0018000 0x38>; }; + + gpio0: gpio@d0018100 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018100 0x40>, + <0xd0018800 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018140 0x40>, + <0xd0018840 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <20>, <21>, <22>, <23>; + }; + + gpio2: gpio@d0018180 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018180 0x40>, + <0xd0018870 0x30>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <24>; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index cf8624d3784c..ffac98373792 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -19,10 +19,52 @@ model = "Marvell Armada XP MV78460 SoC"; compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + soc { pinctrl { compatible = "marvell,mv78460-pinctrl"; reg = <0xd0018000 0x38>; }; + + gpio0: gpio@d0018100 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018100 0x40>, + <0xd0018800 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; + + gpio1: gpio@d0018140 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018140 0x40>, + <0xd0018840 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <20>, <21>, <22>, <23>; + }; + + gpio2: gpio@d0018180 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018180 0x40>, + <0xd0018870 0x30>; + ngpios = <3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupts-cells = <2>; + interrupts = <24>; + }; }; }; -- cgit v1.2.1 From b014487044161b83010a9cbe336dbc41d2c38a0b Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Sat, 22 Sep 2012 13:53:12 -0700 Subject: ARM: kirkwood: move new dtbs to common Makefile This moves a few of the newly introduced dtb targets to the common dts/Makefile instead of the per-platform file. Signed-off-by: Olof Johansson --- arch/arm/boot/dts/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d302e6655e65..d4ad2df08920 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -17,6 +17,9 @@ dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \ usb_a9263.dtb \ usb_a9g20.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb +dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ + dove-cubox.dtb \ + dove-dove-db.dtb dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos5250-smdk5250.dtb @@ -32,10 +35,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ + kirkwood-dockstar.dtb \ kirkwood-dreamplug.dtb \ kirkwood-goflexnet.dtb \ kirkwood-ib62x0.dtb \ kirkwood-iconnect.dtb \ + kirkwood-iomega_ix2_200.dtb \ + kirkwood-km_kirkwood.dtb \ kirkwood-lschlv2.dtb \ kirkwood-lsxhl.dtb \ kirkwood-ts219-6281.dtb \ -- cgit v1.2.1 From bbd6eb29214e1a278e8575f57d64b88077bebf6d Mon Sep 17 00:00:00 2001 From: Stefano Stabellini Date: Mon, 24 Sep 2012 16:40:52 +0000 Subject: arm: introduce a DTS for Xen unprivileged virtual machines Given that the xenvm machine is based on vexpress but with an extremely limited selection of peripherals (the guest is supposed to use virtual devices instead), add "xen,xenvm" to the list of compatible machines in mach-vexpress. Changes in v3: - add comments to mark fields that are likely to be changed by the hypervisor. Changes in v2: - remove include skeleton; - use #address-cells = <2> and #size-cells = <2>; - remove the debug bootargs; - use memory@80000000 instead of memory; - remove the ranges and interrupt-map from the motherboard node; - set the machine compatible to "xen,xenvm-4.2", "xen,xenvm"; - rename the dts file to xenvm-4.2.dts; - add "xen,xenvm" to the list of compatible DT strings to mach-vexpress. Signed-off-by: Stefano Stabellini Acked-by: Arnd Bergmann Acked-by: Pawel Moll (v2m changes) --- arch/arm/boot/dts/xenvm-4.2.dts | 68 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 arch/arm/boot/dts/xenvm-4.2.dts (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts new file mode 100644 index 000000000000..ec3f9528e180 --- /dev/null +++ b/arch/arm/boot/dts/xenvm-4.2.dts @@ -0,0 +1,68 @@ +/* + * Xen Virtual Machine for unprivileged guests + * + * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU) + * Cortex-A15 MPCore (V2P-CA15) + * + */ + +/dts-v1/; + +/ { + model = "XENVM-4.2"; + compatible = "xen,xenvm-4.2", "xen,xenvm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + /* this field is going to be adjusted by the hypervisor */ + bootargs = "console=hvc0 root=/dev/xvda"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* this field is going to be adjusted by the hypervisor */ + reg = <0 0x80000000 0 0x08000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x2c001000 0 0x1000>, + <0 0x2c002000 0 0x100>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + hypervisor { + compatible = "xen,xen-4.2", "xen,xen"; + /* this field is going to be adjusted by the hypervisor */ + reg = <0 0xb0000000 0 0x20000>; + /* this field is going to be adjusted by the hypervisor */ + interrupts = <1 15 0xf08>; + }; + + motherboard { + arm,v2m-memory-map = "rs1"; + }; +}; -- cgit v1.2.1 From 07c7e12ca7e32e942d2c42dd67329c5fc3886b07 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Tue, 25 Sep 2012 10:11:41 +0200 Subject: ARM: LPC32xx: LED fix in PHY3250 DTS file This patch adjusts the PHY3250 board file to the actual LED configuration (active high, default-state and trigger configuration). Signed-off-by: Roland Stigge --- arch/arm/boot/dts/phy3250.dts | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index a7ad85e4b8f9..90fdbd77f274 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -189,16 +189,14 @@ leds { compatible = "gpio-leds"; - led0 { - gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */ - linux,default-trigger = "heartbeat"; + led0 { /* red */ + gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ default-state = "off"; }; - led1 { - gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ - linux,default-trigger = "timer"; - default-state = "off"; + led1 { /* green */ + gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ + linux,default-trigger = "heartbeat"; }; }; }; -- cgit v1.2.1 From 84bd48a04eff487570c9cdd91648835456ed65ac Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Wed, 26 Sep 2012 09:02:59 +0900 Subject: ARM: dts: Add nodes for dw_mmc controllers for Samsung EXYNOS5250 platforms Add device nodes for the four instances of dw_mmc controllers in EXYNOS5250 and enable instance 0 and 2 for the SMDK5250 board. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 57 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5250.dtsi | 32 +++++++++++++++++ 2 files changed, 89 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 62e1039fb30e..a352df403b7a 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -16,6 +16,13 @@ model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; compatible = "samsung,smdk5250", "samsung,exynos5250"; + aliases { + mshc0 = &dwmmc_0; + mshc1 = &dwmmc_1; + mshc2 = &dwmmc_2; + mshc3 = &dwmmc_3; + }; + memory { reg = <0x40000000 0x80000000>; }; @@ -72,6 +79,56 @@ status = "disabled"; }; + dwmmc_0: dwmmc0@12200000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3 3>; + samsung,dw-mshc-ddr-timing = <1 2 3>; + + slot@0 { + reg = <0>; + bus-width = <8>; + gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, + <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, + <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>, + <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, + <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>; + }; + }; + + dwmmc_1: dwmmc1@12210000 { + status = "disabled"; + }; + + dwmmc_2: dwmmc2@12220000 { + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3 3>; + samsung,dw-mshc-ddr-timing = <1 2 3>; + + slot@0 { + reg = <0>; + bus-width = <4>; + samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>; + gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>, + <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>, + <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>, + <&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>, + <&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>; + }; + }; + + dwmmc_3: dwmmc3@12230000 { + status = "disabled"; + }; + spi_0: spi@12d20000 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 004aaa8d123c..f69e389e6ffa 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -182,6 +182,38 @@ #size-cells = <0>; }; + dwmmc0@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12200000 0x1000>; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dwmmc1@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12210000 0x1000>; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dwmmc2@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12220000 0x1000>; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + dwmmc3@12230000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12230000 0x1000>; + interrupts = <0 78 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + amba { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.1 From 1dc737c44a11c66f23ebeb09796f52f4b60d59c7 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 21 Aug 2012 12:31:06 +0200 Subject: ARM: highbank: add coherent DMA setup Some highbank DMA masters can support coherent (ACP) or non-coherent DMA. This sets up dma_map_ops for masters which are configured for coherent DMA. Signed-off-by: Rob Herring Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/highbank.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 9fecf1ae777b..7414577c177f 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -121,6 +121,7 @@ compatible = "calxeda,hb-ahci"; reg = <0xffe08000 0x10000>; interrupts = <0 83 4>; + dma-coherent; }; sdhci@ffe0e000 { -- cgit v1.2.1 From 74d8378159de16a0a1d1975d4778120d263d6000 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 21 Sep 2012 18:06:54 +0800 Subject: ARM: dts: Enable 88pm860x pmic Signed-off-by: Haojian Zhuang Signed-off-by: Samuel Ortiz --- arch/arm/boot/dts/pxa910-dkb.dts | 137 +++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/pxa910.dtsi | 4 ++ 2 files changed, 141 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts index e92be5a474e7..595492aa5053 100644 --- a/arch/arm/boot/dts/pxa910-dkb.dts +++ b/arch/arm/boot/dts/pxa910-dkb.dts @@ -29,6 +29,143 @@ }; twsi1: i2c@d4011000 { status = "okay"; + + pmic: 88pm860x@34 { + compatible = "marvell,88pm860x"; + reg = <0x34>; + interrupts = <4>; + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <1>; + + marvell,88pm860x-irq-read-clr; + marvell,88pm860x-slave-addr = <0x11>; + + regulators { + BUCK1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + BUCK2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + BUCK3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + regulator-always-on; + }; + LDO2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO5 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO13 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + rtc { + marvell,88pm860x-vrtc = <1>; + }; + touch { + marvell,88pm860x-gpadc-prebias = <1>; + marvell,88pm860x-gpadc-slot-cycle = <1>; + marvell,88pm860x-tsi-prebias = <6>; + marvell,88pm860x-pen-prebias = <16>; + marvell,88pm860x-pen-prechg = <2>; + marvell,88pm860x-resistor-X = <300>; + }; + backlights { + backlight-0 { + marvell,88pm860x-iset = <4>; + marvell,88pm860x-pwm = <3>; + }; + backlight-2 { + }; + }; + leds { + led0-red { + marvell,88pm860x-iset = <12>; + }; + led0-green { + marvell,88pm860x-iset = <12>; + }; + led0-blue { + marvell,88pm860x-iset = <12>; + }; + }; + }; }; rtc: rtc@d4010000 { status = "okay"; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index aebf32de73b4..1942e5411acd 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -115,6 +115,8 @@ twsi1: i2c@d4011000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4011000 0x1000>; interrupts = <7>; mrvl,i2c-fast-mode; @@ -123,6 +125,8 @@ twsi2: i2c@d4037000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4037000 0x1000>; interrupts = <54>; status = "disabled"; -- cgit v1.2.1