From 080c37473eb671a037b3e9a315303851f0675be5 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 11 Feb 2013 19:52:57 +0530 Subject: ARC: [optim] Cache "current" in Register r25 Signed-off-by: Vineet Gupta --- arch/arc/kernel/entry.S | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arc/kernel/entry.S') diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index ce8670da8306..69d0d376e28b 100644 --- a/arch/arc/kernel/entry.S +++ b/arch/arc/kernel/entry.S @@ -32,6 +32,9 @@ * was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit, * setting it and not clearing it clears ZOL context * + * Vineetg: May 16th, 2008 + * - r25 now contains the Current Task when in kernel + * * Vineetg: Dec 22, 2007 * Minor Surgery of Low Level ISR to make it SMP safe * - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR @@ -535,6 +538,17 @@ restore_regs : ; XXX can this be optimised out IRQ_DISABLE_SAVE r9, r10 ;@r10 has prisitine (pre-disable) copy +#ifdef CONFIG_ARC_CURR_IN_REG + ; Restore User R25 + ; Earlier this used to be only for returning to user mode + ; However with 2 levels of IRQ this can also happen even if + ; in kernel mode + ld r9, [sp, PT_sp] + brhs r9, VMALLOC_START, 8f + RESTORE_USER_R25 +8: +#endif + ; Restore REG File. In case multiple Events outstanding, ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None ; Note that we use realtime STATUS32 (not pt_regs->status32) to -- cgit v1.2.1