From 120e8989ebac7c7c702e351046c20e9918912aca Mon Sep 17 00:00:00 2001 From: Purna Chandra Mandal Date: Fri, 1 Apr 2016 16:48:49 +0530 Subject: spi: pic32: Add bindings for PIC32 SPI peripheral Document the devicetree bindings for the SPI peripheral found on Microchip PIC32 class devices. Signed-off-by: Purna Chandra Mandal Acked-by: Rob Herring Signed-off-by: Mark Brown --- .../bindings/spi/microchip,spi-pic32.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt new file mode 100644 index 000000000000..79de379f4dc0 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/microchip,spi-pic32.txt @@ -0,0 +1,34 @@ +Microchip PIC32 SPI Master controller + +Required properties: +- compatible: Should be "microchip,pic32mzda-spi". +- reg: Address and length of register space for the device. +- interrupts: Should contain all three spi interrupts in sequence + of , , . +- interrupt-names: Should be "fault", "rx", "tx" in order. +- clocks: Phandle of the clock generating SPI clock on the bus. +- clock-names: Should be "mck0". +- cs-gpios: Specifies the gpio pins to be used for chipselects. + See: Documentation/devicetree/bindings/spi/spi-bus.txt + +Optional properties: +- dmas: Two or more DMA channel specifiers following the convention outlined + in Documentation/devicetree/bindings/dma/dma.txt +- dma-names: Names for the dma channels. There must be at least one channel + named "spi-tx" for transmit and named "spi-rx" for receive. + +Example: + +spi1: spi@1f821000 { + compatible = "microchip,pic32mzda-spi"; + reg = <0x1f821000 0x200>; + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>, + <110 IRQ_TYPE_LEVEL_HIGH>, + <111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "fault", "rx", "tx"; + clocks = <&PBCLK2>; + clock-names = "mck0"; + cs-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + dmas = <&dma 134>, <&dma 135>; + dma-names = "spi-rx", "spi-tx"; +}; -- cgit v1.2.1 From 0a4afaae989c47fd93b73cc83d2c4a46b55aa1b7 Mon Sep 17 00:00:00 2001 From: Purna Chandra Mandal Date: Fri, 15 Apr 2016 16:57:18 +0530 Subject: spi: pic32-sqi: add binding document for PIC32 Quad-SPI driver. Document Device tree bindings for the quad SPI peripheral found on Microchip PIC32 class devices. Signed-off-by: Purna Chandra Mandal Acked-by: Rob Herring Cc: Kumar Gala Cc: Ian Campbell Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Mark Brown Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/sqi-pic32.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt b/Documentation/devicetree/bindings/spi/sqi-pic32.txt new file mode 100644 index 000000000000..c82d021bce50 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/sqi-pic32.txt @@ -0,0 +1,18 @@ +Microchip PIC32 Quad SPI controller +----------------------------------- +Required properties: +- compatible: Should be "microchip,pic32mzda-sqi". +- reg: Address and length of SQI controller register space. +- interrupts: Should contain SQI interrupt. +- clocks: Should contain phandle of two clocks in sequence, one that drives + clock on SPI bus and other that drives SQI controller. +- clock-names: Should be "spi_ck" and "reg_ck" in order. + +Example: + sqi1: spi@1f8e2000 { + compatible = "microchip,pic32mzda-sqi"; + reg = <0x1f8e2000 0x200>; + clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>; + clock-names = "spi_ck", "reg_ck"; + interrupts = <169 IRQ_TYPE_LEVEL_HIGH>; + }; -- cgit v1.2.1 From c145344763192042135ef6172b779baaf4a16c1e Mon Sep 17 00:00:00 2001 From: Yuan Yao Date: Wed, 27 Apr 2016 16:12:36 +0800 Subject: spi: spi-fsl-dspi: Update DT binding documentation DSPI driver support the register on the controller with big endian mode R/W. But not use the regmap API. So update the binding documentation for "big-endian". Signed-off-by: Yuan Yao Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index fa77f874e321..d2969d2ceb4b 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -13,8 +13,7 @@ Required properties: Optional property: - big-endian: If present the dspi device's registers are implemented - in big endian mode, otherwise in native mode(same with CPU), for more - detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. + in big endian mode. Optional SPI slave node properties: - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip -- cgit v1.2.1