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path: root/include/linux/soc/qcom/llcc-qcom.h
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* qcom: soc: llcc-slice: Clear the global drv_data pointer on errorJordan Crouse2019-02-121-0/+6
| | | | | | | | | | | | | | | Currently the data structure for llc-slice is devm allocated and stored as a global but never cleared if the probe function fails. This is a problem because devm managed memory gets freed on probe failure the API functions could access the pointer after it has been freed. Initialize the drv_data pointer to an error and reset it to an error on probe failure or device destroy and add protection to the API functions to make sure the memory doesn't get accessed. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* drivers: edac: Add EDAC driver support for QCOM SoCsChannagoud Kadabi2018-09-131-0/+24
| | | | | | | | | | | | | | Add error reporting driver for Single Bit Errors (SBEs) and Double Bit Errors (DBEs). As of now, this driver supports error reporting for Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts are triggered when the errors happen in the cache, the driver handles those interrupts and dumps the syndrome registers. Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Co-developed-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: Add support to register LLCC EDAC driverVenkata Narendra Kumar Gutta2018-09-131-0/+2
| | | | | | | | | | | Cache error reporting controller detects and reports single and double bit errors on Last Level Cache Controller (LLCC) cache. Add required support to register LLCC EDAC driver as platform driver, from LLCC driver. Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* soc: qcom: Add broadcast base for Last Level Cache Controller (LLCC)Venkata Narendra Kumar Gutta2018-09-131-2/+2
| | | | | | | | | | | | | Currently, broadcast base is set to end of the LLCC banks, which may not be correct always. As the number of banks may vary for each chipset and the broadcast base could be at a different address as well. This info depends on the chipset, so get the broadcast base info from the device tree (DT). Add broadcast base in LLCC driver and use this for broadcast writes. Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
* drivers: soc: Add LLCC driverRishabh Bhatnagar2018-07-211-0/+180
LLCC (Last Level Cache Controller) provides additional cache memory in the system. LLCC is partitioned into multiple slices and each slice gets its own priority, size, ID and other config parameters. LLCC driver programs these parameters for each slice. Clients that are assigned to use LLCC need to get information such size & ID of the slice they get and activate or deactivate the slice as needed. LLCC driver provides API for the clients to perform these operations. Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
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