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path: root/drivers/usb/dwc3/gadget.c
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* | usb: dwc3: move generic dwc3 code from gadget into coreSebastian Andrzej Siewior2011-12-121-24/+0
| | | | | | | | | | | | | | | | | | | | A few inits like the scale value or the removal of the DISSCRAMBLE is done in the gadget code however it touches a general register. Move this piece to the core.c file since it is likely to be requied by both, parts of the core (device and host). Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* | usb: dwc3: use a helper function for operation mode settingSebastian Andrzej Siewior2011-12-121-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two where need to set operational mode: - during initialization while we decide to run in host,device or DRD mode - at runtime via the debugfs interface. This patch provides a new function which sets the operational mode and moves its initialiation to the mode switch instead in the gadget code itself. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* | usb: dwc3: calculate number of event buffers dynamicallyFelipe Balbi2011-12-121-1/+1
| | | | | | | | | | | | | | This will allow us to only allocate memory when we actually need. Signed-off-by: Felipe Balbi <balbi@ti.com>
* | usb: dwc3: allow forcing a maximum speedFelipe Balbi2011-12-121-1/+1
| | | | | | | | | | | | | | | | | | this is mainly for testing. In order to be able to test if we're enumerating correctly on all speeds, let that be controlled by a module parameter. Signed-off-by: Felipe Balbi <balbi@ti.com>
* | usb: dwc3: gadget: don't disable endpoints on exitFelipe Balbi2011-12-121-4/+0
|/ | | | | | | when we remove the gadget driver, it will already do that for us. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: initialize max_streamsSebastian Andrzej Siewior2011-11-141-0/+1
| | | | | | | | | | | Without this the gadget will never be able to allocate a stream capable endpoint. The manual says that the stream id is a 16bit id. It does not talk about an upper limit in any other way. So I think 15 is a reasonable limit :) Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: convert structures into bitshiftsFelipe Balbi2011-10-041-21/+19
| | | | | | | | | our parameter structures need to be written to HW, so instead of assuming little endian, we convert those into bit shifts. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: gadget: allow clock gating to workFelipe Balbi2011-10-041-0/+8
| | | | | | | | | | The dwc3 core has internal clock gating support. Let's allow that to happen by clearing the disable bit in GCTL register. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: gadget: implement streams supportFelipe Balbi2011-10-041-4/+30
| | | | | | | | | | | | | The following patch adds support for streams to dwc3 driver. While at that, also fix one small issue on endpoint disable where we should clear all flags not only ENABLED. Reviewied-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: gadget: add support for BurstsFelipe Balbi2011-10-041-0/+1
| | | | | | | | We already have the value from gadget drivers, just need to pass it to our controller. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: gadget: fix DMA offset calculationPaul Zimmerman2011-10-041-1/+1
| | | | | | | | Fix offset calculation in dwc3_trb_dma_offset() Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: gadget: make DWC3_EP_WEDGE do the right thingPaul Zimmerman2011-10-041-1/+5
| | | | | | | | | | | | | This makes DWC3_EP_WEDGE do the right thing, which is prevent DWC3_EP_WEDGE from ever being cleared by a ClearFeature(HALT) command. [ balbi@ti.com : allowed set_wedge to send SetHalt command to controller ] Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: gadget: driver should not wait for RxFIFO to drainPaul Zimmerman2011-10-041-19/+0
| | | | | | | | | | | | | | | An older version of the databook said to wait for the FIFO to drain, but that has been removed from the newer databooks. Waiting for RxFIFO to drain caused problems when testing against one of the host controllers available in the market. After talking to one of the RTL engineers, he stated that we should _not_ wait for RxFIFO to drain. Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: gadget: fix DEPSTARTCFG for non-EP0 EPsPaul Zimmerman2011-10-041-1/+9
| | | | | | | | | | DEPSTARTCFG for non-EP0 EPs must only be sent once per config [ balbi@ti.com : changed config_start to start_config_issued ] Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc: remove "All rights reserved" statement.Sebastian Andrzej Siewior2011-10-041-1/+0
| | | | | | | | | | Some people think that this line is not compatible with the GPL. The statement was required due to the Buenos Aires Convention and is now deprecated. I remove it because it is said that it is pointless nowdays. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: dwc3: gadget: improve debug on link state changeFelipe Balbi2011-09-091-2/+2
| | | | | | | | It's useful to know which states core is going through, as it might help us figure out misbehavior on specific link states. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: drop the useless dma_sync_single* callsFelipe Balbi2011-09-091-9/+0
| | | | | | | | if req->dma isn't DMA_ADDR_INVALID it means gadget driver mapped the request or allocated from coherent, so it's unnecessary to do anything. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: fix GCTL programmingFelipe Balbi2011-09-091-6/+3
| | | | | | | ensure a few bits are cleared before enabling what we need. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: do not map/unmap ZLP transfersSebastian Andrzej Siewior2011-09-091-0/+10
| | | | | | | | | If the gadget drivers sends a ZLP we are trying to map this this request which does not work on all implementations. So we simply skip mapping it. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: drop EP0_STALL stateFelipe Balbi2011-09-091-2/+8
| | | | | | | | | | | Whenever we issue a Set Stall command on EP0, the state machine will be restarted and Stall is cleared automatically, when core receives the next SETUP packet. There's no need to track that EP0_STALL state. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: replace mdelay with udelay in the busy loopSebastian Andrzej Siewior2011-09-091-8/+4
| | | | | | | | | | | | | | | | | | There are two spots where we wait until the HW finishes processing a certain command. Initially we had a few problems and we used 500ms as a limit to be on a the safe side. Paul Zimmerman mentioned this is little too much. After a debugging session, we noticed that we hardly ever go over 20us and didn't pass 30usec so far. Using mdelay() seems way overloaded. Giving the current numbers 500usec as the upper limit is more than enough. Should it ever timeout then something is definitely wrong. While here, also replace the type with u32 since long does not really fit here. Cc: Paul Zimmerman <paul.zimmerman@synopsys.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: rework the dequeue on RESET & DISCONNECTSebastian Andrzej Siewior2011-09-091-19/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - since a while we are disabling an endpoint and purging every requests on RESET and DISCONNECT which leads to a warning since the endpoint was disabled twice (once by the UDC, and second time by the gadget). I think UDC should nuke all requests because all those requests become invalid. It's gadget driver's responsability, though, to disable its used endpoints. This is done by merging dwc3_stop_active_transfer() and dwc3_gadget_nuke_reqs() into dwc3_remove_requests(). - dwc3_stop_active_transfer() is now no longer called unconditionaly. This has the advantage that it is always called to disable an active transfer which means if res_trans_idx 0 than something went wrong and it is an error condition because we can't clean up the requests. - Remove the DWC3_EP_WILL_SHUTDOWN which was introduced while introducing the command complete part for dequeue. All requests on req_queued list should be removed during the dwc3_cleanup_done_reqs() callback so there is no reason to go through the list again. We consider it an error condition if requests are still on this list since we never queue TRB without LST=1 (the last requests has always LST=1, there are no requests with LST=0 behind it). [ balbi@ti.com : reworked commit log a bit, made patch apply ] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: ep0: simplify EP0 state machineFelipe Balbi2011-09-091-2/+1
| | | | | | | | | | | | | | | | | | | | The DesignWare USB3 core tells us which phase of a control transfer should be started, it also tells us which physical endpoint needs that transfer. With these two informations, we have all we need to simply EP0 handling quite a lot and get rid rid of the SW state machine tracking ep0 states. For achieving this perfectly, we needed to add support for situations where we get XferNotReady while endpoint is still busy and XferNotReady while gadget driver still hasn't queued a request. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: add a bounce buffer for control endpointsFelipe Balbi2011-09-091-7/+22
| | | | | | | | | | | This core cannot handle OUT transfers which aren't aligned to wMaxPacketSize, but that can happen at least on control endpoint with the USB Audio Class. This patch adds a bounce buffer to be used on the case of a non-aligned ep0out request is queued. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: improve command completion debug messageFelipe Balbi2011-09-091-2/+2
| | | | | | | | | the previous message had too little meaning. Make it more human readable and use the macro we already had for extracting the command completion status out of DEPCMDn register. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: set request dma to invalid when unmappingFelipe Balbi2011-09-091-0/+1
| | | | | | | | if we don't set DMA address to invalid when unmapping, we might fall in a situation where request buffer can't be mapped to DMA again. Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gaget: clear DWC3_EP_WILL_SHUTDOWN bitSebastian Andrzej Siewior2011-09-091-1/+1
| | | | | | | | Without this patch we won't clear that bit and instead will clear all other bits on our endpoint flag. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: use TRB type 6 for ISOC transfersSebastian Andrzej Siewior2011-09-091-1/+1
| | | | | | | | | Type 6 should be used for the first transfer during an interval. This is also what the reference driver is using. Type 7 seems to be for following or additional transfers within the same interval. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: reset resource index to zeroSebastian Andrzej Siewior2011-09-091-1/+4
| | | | | | | | | | | If we collected two requests together (i.e. only the last of them has LST=1) then we only have to stop transfer once: The clean-up code will cleanup everything until first TRB with the LST bit set. After XferComplete this index should be no longer valid since there is no transfer pending. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* usb: dwc3: gadget: fixing dequeue of TRBsSebastian Andrzej Siewior2011-09-091-3/+9
| | | | | | | | A TRB which is dequeued seems to have its HWO bits set to 1. Therefore we ignore it if we dequeue it after the command is completed. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
* USB: use usb_endpoint_maxp() instead of le16_to_cpu()Kuninori Morimoto2011-08-231-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now ${LINUX}/drivers/usb/* can use usb_endpoint_maxp(desc) to get maximum packet size instead of le16_to_cpu(desc->wMaxPacketSize). This patch fix it up Cc: Armin Fuerst <fuerst@in.tum.de> Cc: Pavel Machek <pavel@ucw.cz> Cc: Johannes Erdfelt <johannes@erdfelt.com> Cc: Vojtech Pavlik <vojtech@suse.cz> Cc: Oliver Neukum <oliver@neukum.name> Cc: David Kubicek <dave@awk.cz> Cc: Johan Hovold <jhovold@gmail.com> Cc: Brad Hards <bhards@bigpond.net.au> Acked-by: Felipe Balbi <balbi@ti.com> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Thomas Dahlmann <dahlmann.thomas@arcor.de> Cc: David Brownell <david-b@pacbell.net> Cc: David Lopo <dlopo@chipidea.mips.com> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Michal Nazarewicz <m.nazarewicz@samsung.com> Cc: Xie Xiaobo <X.Xie@freescale.com> Cc: Li Yang <leoli@freescale.com> Cc: Jiang Bo <tanya.jiang@freescale.com> Cc: Yuan-hsin Chen <yhchen@faraday-tech.com> Cc: Darius Augulis <augulis.darius@gmail.com> Cc: Xiaochen Shen <xiaochen.shen@intel.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com> Cc: Robert Jarzmik <robert.jarzmik@free.fr> Cc: Ben Dooks <ben@simtec.co.uk> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Herbert Pötzl <herbert@13thfloor.at> Cc: Arnaud Patard <arnaud.patard@rtp-net.org> Cc: Roman Weissgaerber <weissg@vienna.at> Acked-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> Cc: Tony Olech <tony.olech@elandigitalsystems.com> Cc: Florian Floe Echtler <echtler@fs.tum.de> Cc: Christian Lucht <lucht@codemercs.com> Cc: Juergen Stuber <starblue@sourceforge.net> Cc: Georges Toth <g.toth@e-biz.lu> Cc: Bill Ryder <bryder@sgi.com> Cc: Kuba Ober <kuba@mareimbrium.org> Cc: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* usb: Introduce DesignWare USB3 DRD DriverFelipe Balbi2011-08-221-0/+2063
The DesignWare USB3 is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI) configurations. Several other parameters can be configured like amount of FIFO space, amount of TX and RX endpoints, amount of Host Interrupters, etc. The current driver has been validated with a virtual model of version 1.73a of that core and with an FPGA burned with version 1.83a of the DRD core. We have support for PCIe bus, which is used on FPGA prototyping, and for the OMAP5, more adaptation (or glue) layers can be easily added and the driver is half prepared to handle any possible configuration the HW engineer has chosen considering we have the information on one of the GHWPARAMS registers to do runtime checking of certain features. More runtime checks can, and should, be added in order to make this driver even more flexible with regards to number of endpoints, FIFO sizes, transfer types, etc. While this supports only the device side, for now, we will add support for Host side (xHCI - see the updated series Sebastian has sent [1]) and OTG after we have it all stabilized. [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2 Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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