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* pinctrl: sirf: wrap all gpio banks into one gpio_chipBarry Song2014-04-231-126/+91
| | | | | | | | all gpio banks are in one chip, that makes software clean in mapping irq and gpio. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sirf: rename inlined accessorLinus Walleij2014-04-231-7/+7
| | | | | | | | | The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is not converting an irqchip to a bank but converts a gpiochip to a bank so rename it sirfsoc_gpiochip_to_bank(). Acked-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: qcom: Add definitions for IPQ8064Andy Gross2014-04-233-0/+662
| | | | | | | | | This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: exynos: Add driver data for Exynos3250Tomasz Figa2014-04-233-0/+70
| | | | | | | | | | | | | | | | | | | This patch adds driver data (bank list and EINT layout) for Exynos3250 to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output ports. There are 23 general port groups. Changes from v1: - Add signed-off of sender - Post only separated patch for pinctrl from following patchset(v1) : https://lkml.org/lkml/2014/4/10/286 Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl/at91: Fix mask creation in at91_gpio_dbg_showAlexander Stein2014-04-221-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pin_to_mask expects a bank pin number. So do not add the chip base. Without that patch cat /sys/kernel/debug/gpio looks like that: GPIOs 0-31, platform/fffff200.gpio, fffff200.gpio: [spi32766.0] GPIOfffff200.gpio5: [gpio] set [ads7846_pendown] GPIOfffff200.gpio15: [gpio] set [ohci_vbus] GPIOfffff200.gpio21: [gpio] set [ohci_vbus] GPIOfffff200.gpio24: [gpio] set [button1] GPIOfffff200.gpio28: [gpio] clear [button2] GPIOfffff200.gpio29: [gpio] clear GPIOs 32-63, platform/fffff400.gpio, fffff400.gpio: [sda] GPIOfffff400.gpio4: [periph A] [scl] GPIOfffff400.gpio5: [periph A] [spi32766.3] GPIOfffff400.gpio11: [periph A] [error] GPIOfffff400.gpio22: [periph A] [run] GPIOfffff400.gpio23: [periph A] GPIOs 64-95, platform/fffff600.gpio, fffff600.gpio: [reset_pin] GPIOfffff600.gpio29: [periph A] GPIOs 96-127, platform/fffff800.gpio, fffff800.gpio: [led1] GPIOfffff800.gpio5: [periph A] [led2] GPIOfffff800.gpio6: [periph A] [led3] GPIOfffff800.gpio7: [periph A] [led4] GPIOfffff800.gpio8: [periph A] GPIOs 128-159, platform/fffffa00.gpio, fffffa00.gpio: [button3] GPIOfffffa00.gpio10: [periph A] [button4] GPIOfffffa00.gpio12: [periph A] Note that every bank despite bank 0 only shows "periph A" which are obviously used as GPIOs. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl/at91: convert driver to use gpiolib irqchipAlexander Stein2014-04-222-105/+33
| | | | | | | | | This converts the AT91 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: add missing kerneldocStephen Warren2014-04-221-0/+4
| | | | | | | | The kerneldoc for struct tegra_pingroup didn't describe all of the fields in the struct. Add some extra kerneldoc to fix that. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: print better error messagesStephen Warren2014-04-221-3/+14
| | | | | | | | | | When an attempt is made to configure an unsupported option on a pin, print the DT property name of that option, so it's easier to debug what the problem is. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: reduce size of data table fieldsStephen Warren2014-04-221-2/+2
| | | | | | | | | The range of npins and function ID values is small enough to fit into a u8. Use this type rather than unsigned to shrink the pinmux data tables. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: remove fsafe from data tablesStephen Warren2014-04-226-783/+772
| | | | | | | | | | | | | | | | | | | | The fsafe value in the pingroup data tables is only used to implement tegra_pinctrl_disable(). The only reason this function is called is when dynamically switching between pinmux states, i.e. when disabling the old state before programming the new state. It's simpler to have the new target state define the expected value of each pin (and all current DTs do that). This also gives more flexibility, since it allows individual boards explicit control over the "inactive" mux function for each pin, rather than requiring it to be an SoC-specific value. Assuming this, we can get rid of the fsafe value from the driver completely, thus saving some more space in the driver tables. While re-writing the content of tegra124_pingroups[], fix the indentation to use a TAB instead of spaces. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: remove redundant data table fieldsStephen Warren2014-04-226-197/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel options has the relevant HW register fields in the same register as the mux function selection. Similarly, the drvtype option is always in the drive register, if it is supported at all. Hence, we don't need to have struct *_reg fields in the pin group table to define which register and bank to use for those options. Delete this to save space in the driver's data tables. However, many of those options are not supported on all SoCs, or not supported on some pingroups. We need a way to detect when they are supported. Previously, this was indicated by setting the struct *_reg field to -1. With the struct *_reg fields removed, we use the struct *_bit fields for this purpose instead. The struct *_bit fields need to be expanded from 5 to 6 bits in order to store a value outside the valid HW bit range of 0..31. Even without removing the struct *_reg fields, we still need to add code to validate the struct *_bit fields, since some struct *_bit fields were already being set to -1, without an option-specific struct *_reg field to "guard" them. In other words, before this change, the pinmux driver might allow some unsupported options to be written to HW. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pfc: r8a7790: add mux data for IIC(B) coresWolfram Sang2014-04-221-2/+116
| | | | | | Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pfc: r8a7790: add i2c0 muxingWolfram Sang2014-04-221-1/+21
| | | | | | | | | Add the muxing for the last missing i2c rcar core. Fix the sorting for SH_PFC_PIN_NAMED while we are here. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinctrl-imx: Print the mux_mode field in hex formatFabio Estevam2014-04-221-1/+1
| | | | | | | | | | | With debug enabled we get better readability dumps of the mux_mode register if we use hexadecimal format instead: imx6sl-pinctrl 20e0000.iomuxc: MX6SL_PAD_FEC_REF_CLK: 0x10 0x0001b0a8 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: r8a7791: Add Audio pin supportKuninori Morimoto2014-04-221-0/+61
| | | | | | | Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* sh-pfc: r8a7791: Add SSI pin supportKuninori Morimoto2014-04-221-0/+314
| | | | | | | Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: fix typo in module author addressAntoine Ténart2014-04-221-1/+1
| | | | | | | | | According to the MODULE_AUTHOR() comments, the author name should be "Name <email>" or just "Name". Add the missing '>'. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: allows not to define the get_group_pins operationAntoine Ténart2014-04-222-17/+23
| | | | | | | | | | | | | | | | | | | | | | | | When using a group only pinctrl driver, which does not have any information on the pins it is useless to define a get_group_pins always returning an empty list of pins. When not using get_group_pin[1], a driver must implement it so pins = NULL and num_pins = 0. This patch makes it the default behaviour if not defined in the pinctrl driver when used in pinmux enable and disable funtions and in pinctrl_groups_show. It also adds a check in pinctrl_get_group_pins and return -EINVAL if not defined. This function is called in the gpiolib when adding when pingroup range. It cannot be used if no group is defined, so this seams reasonable. [1] get_group_pin(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins); Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: add reset control supportBoris BREZILLON2014-04-221-2/+14
| | | | | | | | | | | The A31 SoC define a reset line for the R_PIO block which needs to be deasserted. Try to retrieve a reset control and deassert if one was found. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: define A31 R_PIO pin functionsBoris BREZILLON2014-04-222-0/+75
| | | | | | | | | | | The A31 SoC provides both PL and PM pio bank through the R_PIO block. These pins all support gpio function and can bbe assigned to system peripherals (like TWI, P2WI, JTAG, ...) Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: support multiple pin controllerBoris BREZILLON2014-04-222-16/+15
| | | | | | | | | | | | | Add support for multiple pin controller instances. First remove the static definition of the sunxi gpio chip struct and fill the dynamically struct instead. Then define a new pin_base field in the sunxi_pinctrl_desc which will be used to specify the gpiochip base pin. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: add PL and PM pin definitionsBoris BREZILLON2014-04-221-0/+68
| | | | | | | | Define PL and PM pin macros. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: disable clk when failing to probe pin controllerBoris BREZILLON2014-04-221-2/+4
| | | | | | | | Disable the clk when failing to probe the pin controller device. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: check clk_prepare_enable return valueBoris BREZILLON2014-04-221-1/+3
| | | | | | | | Check the clk_prepare_enable return value to avoid false positive probe. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: st: Use ARRAY_SIZE for STiH415 dataMaxime COQUELIN2014-04-221-2/+2
| | | | | | | | This patch completes the one that used ARRAY_SIZE for STiH407 and STiH416 for setting ninput_delays and noutput_delays fields. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: st: Use const qualifier when requiredMaxime COQUELIN2014-04-221-12/+12
| | | | | | | | This patch adds const qualifier where applicable. Reported-by: Joe Perches <joe@perches.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: lantiq: Fix header file include guardAxel Lin2014-04-221-0/+1
| | | | | | | Define __PINCTRL_LANTIQ_H to prevent multiple inclusion. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: adi2: Statize adi_gpio_irq_domain_opsAxel Lin2014-04-221-1/+1
| | | | | | | It's only referenced in this file, make it static. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groupsLaurent Pinchart2014-04-221-10/+27
| | | | | | | | | The DU parallel interface ODDF signal is optional, move it out of the HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are independent, split them to two different groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: msm8x74: make Kconfig dependency more strictUwe Kleine-König2014-04-221-1/+1
| | | | | | | | | | This driver is only useful on MSM8x74, so let the driver depend on ARCH_QCOM but allow compile coverage testing. The main benefit is that the driver isn't available to be selected for machines that don't have the matching hardware. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: msm: Add definitions for the APQ8064 platformBjorn Andersson2014-04-223-0/+575
| | | | | | | | This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm APQ8064 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: msm: Make number of functions variableBjorn Andersson2014-04-223-4/+6
| | | | | | | | | The various pins may have different number of functions defined, so make this number definable per pin instead of just increasing it to the largest one for all of the platforms. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: st: use gpiolib irqchip helpersLinus Walleij2014-04-222-81/+20
| | | | | | | | | | | | | | | | | | | | | | | | This lets the gpiolib core handle the irqchip set-up and chained IRQ on the primary (behind the mux) IRQ chip in the st pinctrl driver. Default irq type is set to level low at irqchip add time. The v1 was sent by Linus (https://lkml.org/lkml/2014/4/4/287). Two changes were necessary to make it to work properly on STiH416: 1 - dev reference was not passed to the gpio_chip struct, causing a panic. 2 - gpiochip_irqchip_add passed IRQ_TYPE_NONE as default type, which caused lot of warnings at init time. I choose IRQ_TYPE_LEVEL_LOW as default. Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Maxime COQUELIN <maxime.coquelin@st.com>
* pinctrl: st: switch IRQ locking to resource callbacksLinus Walleij2014-04-221-9/+7
| | | | | | | | | | In the mass-conversion to the new irqchip callbacks, this in-transit IRQ support was missed. Fix it. Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com> Cc: Maxime COQUELIN <maxime.coquelin@st.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Rename Broadcom Capri pinctrl driverSherman Yin2014-04-144-1459/+1466
| | | | | | | | | | | | | | | | | To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl driver and its related CONFIG option are renamed to bcm281xx. Devicetree compatible string and binding documentation use "brcm,bcm11351-pinctrl" to match the machine binding here: Documentation/devicetree/bindings/arm/bcm/bcm11351.txt This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155 SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: msm: Correct interrupt code for TLMM v2Bjorn Andersson2014-04-142-1/+6
| | | | | | | | | Acking interrupts are done differently between on v2 and v3, so add an extra attribute to the pingroup struct to let the platform definitions control this. Also make sure to start dual edge detection by detecting the rising edge. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: nomadik: delete stray debug printLinus Walleij2014-04-141-1/+0
| | | | | | I left this in by mistake, get rid of it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: handle first half of rk3188-bank0 correctlyHeiko Stübner2014-04-141-0/+14
| | | | | | | | | | | The first half of pinbank 0 only has one muxing function (as gpios) and does not have a special mux-register. Therefore ensure that no other mux function can be selected and also do not write to a non-existent register. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: add return value to rockchip_set_muxHeiko Stübner2014-04-141-7/+25
| | | | | | | | | In a following change, rockchip_set_mux gets the possibility to fail. Therefore add a return value to it and honor error codes in functions using rockchip_set_mux. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: fix offset of mux registers for rk3188Beniamino Galvani2014-04-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The correct value of .mux_offset for rk3188 seems to be 0x60 instead of 0x68. Heiko adds: GPIO0 only has the second two IOMUX registers: - GRF_GPIO0C_IOMUX at 0x68 - GRF_GPIO0D_IOMUX at 0x6c which I guess is where my mistake comes from. It looks like there does no iomux register exist at all for the first 16 pins. In any case, the current number is wrong, and the 0x60 offset is the correct one, but I guess we need to determine what the affected pins do - do they always have a gpio mux or such? Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'gpio-v3.15-1' of ↵Linus Torvalds2014-04-037-263/+126
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull bulk of gpio updates from Linus Walleij: "A pretty big chunk of changes this time, but it has all been on rotation in linux-next and had some testing. Of course there will be some amount of fixes on top... - Merged in a branch of irqchip changes from Thomas Gleixner: we need to have new callbacks from the irqchip to determine if the GPIO line will be eligible for IRQs, and this callback must be able to say "no". After some thinking I got the branch from tglx and have switched all current users over to use this. - Based on tglx patches, we have added some generic irqchip helpers in the gpiolib core. These will help centralize code when GPIO drivers have simple chained/cascaded IRQs. Drivers will still define their irqchip vtables, but the gpiolib core will take care of irqdomain set-up, mapping from local offsets to Linux irqs, and reserve resources by marking the GPIO lines for IRQs. - Initially the PL061 and Nomadik GPIO/pin control drivers have been switched over to use the new gpiochip-to-irqchip infrastructure with more drivers expected for the next kernel cycle. The factoring of just two drivers still makes it worth it so it is already a win. - A new driver for the Synopsys DesignWare APB GPIO block. - Modify the DaVinci GPIO driver to be reusable also for the new TI Keystone architecture. - A new driver for the LSI ZEVIO SoCs. - Delete the obsolte tnetv107x driver. - Some incremental work on GPIO descriptors: have gpiod_direction_output() use a logical level, respecting assertion polarity through ACTIVE_LOW flags, adding gpiod_direction_output_raw() for the case where you want to set that very value. Add gpiochip_get_desc() to fetch a GPIO descriptor from a specific offset on a certain chip inside driver code. - Switch ACPI GPIO code over to using gpiochip_get_desc() and get rid of gpio_to_desc(). - The ACPI GPIO event handling code has been reworked after encountering an actual real life implementation. - Support for ACPI GPIO operation regions. - Generic GPIO chips can now be assigned labels/names from platform data. - We now clamp values returned from GPIO drivers to the boolean [0,1] range. - Some improved documentation on how to use the polarity flag was added. - a large slew of incremental driver updates and non-critical fixes. Some targeted for stable" * tag 'gpio-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (80 commits) gpio: rcar: Add helper variable dev = &pdev->dev gpio-lynxpoint: force gpio_get() to return "1" and "0" only gpio: unmap gpio irqs properly pch_gpio: set value before enabling output direction gpio: moxart: Actually set output state in moxart_gpio_direction_output() gpio: moxart: Avoid forward declaration gpio: mxs: Allow for recursive enable_irq_wake() call gpio: samsung: Add missing "break" statement gpio: twl4030: Remove redundant assignment gpio: dwapb: correct gpio-cells in binding document gpio: iop: fix devm_ioremap_resource() return value checking pinctrl: coh901: convert driver to use gpiolib irqchip pinctrl: nomadik: convert driver to use gpiolib irqchip gpio: pl061: convert driver to use gpiolib irqchip gpio: add IRQ chip helpers in gpiolib pinctrl: nomadik: factor in platform data container pinctrl: nomadik: rename secondary to latent gpio: Driver for SYSCON-based GPIOs gpio: generic: Use platform_device_id->driver_data field for driver flags pinctrl: coh901: move irq line locking to resource callbacks ...
| * pinctrl: coh901: convert driver to use gpiolib irqchipLinus Walleij2014-03-262-151/+54
| | | | | | | | | | | | | | | | This converts the COH901 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: convert driver to use gpiolib irqchipLinus Walleij2014-03-262-90/+36
| | | | | | | | | | | | | | | | This converts the Nomadik pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: factor in platform data containerLinus Walleij2014-03-251-30/+9
| | | | | | | | | | | | | | | | | | The old platform data struct is just a leftover from the times when the driver was not probed exclusively from the device tree. Factor this into the general state container and simplify the probe path. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: nomadik: rename secondary to latentLinus Walleij2014-03-251-14/+14
| | | | | | | | | | | | | | | | | | | | The "secondary irq" in the nomadik pin control driver is actually not secondary (as in: can occur any time alongside the ordinary irq), it is a latent IRQ. It is an IRQ that has occurred when the system was in sleep state and has been cached in a special register flagged from the low power management unit (PRCM). Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: coh901: move irq line locking to resource callbacksLinus Walleij2014-03-181-5/+23
| | | | | | | | | | | | | | | | | | | | This switches the COH901 GPIO driver over to using the .request_resources() and .release_resources() callbacks from the irqchip vtable and separate the calls from the .enable() and .disable() callbacks as the latter cannot really say no to a request, whereas the resource callbacks can. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * gpio: switch drivers to use new callbackLinus Walleij2014-03-185-24/+41
| | | | | | | | | | | | | | | | | | | | | | | | This switches all GPIO and pin control drivers with irqchips that were using .startup() and .shutdown() callbacks to lock GPIO lines for IRQ usage over to using the .request_resources() and .release_resources() callbacks just introduced into the irqchip vtable. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'pinctrl-v3.15-1' of ↵Linus Torvalds2014-04-0140-4653/+3167
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control bulk changes from Linus Walleij: "Pin control bulk changes for the v3.15 series, no new core functionality this time, just incremental driver updates: - A large refactoring of the MVEBU (Marvell) driver. - A large refactoring of the Tegra (nVidia) driver. - GPIO interrupt including soft edges support in the STi driver. - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin), pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi (AllWinner), i.MX (Freescale), Baytrail" * tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: tegra: add some missing Tegra114 entries pinctrl: tegra: fix some mistakes in Tegra124 pinctrl: msm: fix up out-of-order merge conflict pinctrl: st: Fix error check for of_irq_to_resource usage pinctrl: tegra: consistency cleanup pinctrl: tegra: dynamically calculate function list of groups pinctrl: tegra: init Tegra20/30 at module_init time pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays pinctrl: st: add pinctrl support for the STiH407 SoC pinctrl: st: Enhance the controller to manage unavailable registers pinctrl: msm: Simplify msm_config_reg() and callers pinctrl: msm: Remove impossible WARN_ON()s pinctrl: msm: Replace lookup tables with math pinctrl: msm: Drop OF_IRQ dependency pinctrl: msm: Drop unused includes pinctrl: msm: Check for ngpios > MAX_NR_GPIO pinctrl: msm: Silence recursive lockdep warning pinctrl: mvebu: silence WARN to dev_warn pinctrl: msm: drop wake_irqs bitmap pinctrl-baytrail: add function mux checking in gpio pin request ...
| * pinctrl: tegra: add some missing Tegra114 entriesStephen Warren2014-03-141-29/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | Add some missing pin and drive group definitions to the driver. These are all defined in the TRM, but missing from the driver for some reason. Fix a couple of mistakes in the drive group definitions. Much of the diff to tegra114_groups[] is an indentation change due to one of the new group names being long. git diff/show -w will highlight this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: tegra: fix some mistakes in Tegra124Stephen Warren2014-03-141-5/+5
| | | | | | | | | | | | | | | | | | | | A couple of pairs of pin group names were swapped in the table. This caused the wrong register to be programmed. Luckily, this had little effect, if any, since the swapped pins were likely to be programmed identically. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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