summaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl/pinctrl-sunxi.c
Commit message (Collapse)AuthorAgeFilesLines
* pinctrl: sunxi: fix error return code in sunxi_pinctrl_probe()Wei Yongjun2013-05-271-1/+3
| | | | | | | | | | | Fix to return a negative error code from the devm_clk_get() error handling case instead of 0, as done elsewhere in this function. Introduced by commit 950707c0eb5c7aeaa2c446a04c824f4be686d2f6 (pinctrl: sunxi: add clock support) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Don't override the error code in probe error handlingAxel Lin2013-05-271-1/+2
| | | | | | | | | | Otherwise, we return 0 in probe error paths when gpiochip_remove() returns 0. Also show error message if gpiochip_remove() fails. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Rename wemac functions to emacMaxime Ripard2013-04-091-18/+18
| | | | | | | | | | | | | | The pin functions associated to the ethernet controller were introduced with the label "wemac", which was the name of the ethernet driver in the allwinner source tree, while the real name of the IP is actually "emac", as advertised in several documents including the datasheet. Since this is part of the device tree bindings, and that these part of the bindings have not yet be released in a kernel version, it seems like the good timing to change it and assure consistency. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: add clock supportEmilio López2013-04-031-0/+8
| | | | | | | | | For the port controller to work, we need to enable the apb0_pio gate. This commit adds the ability to enable one clock specified on the device tree to the pinctrl driver. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Add Allwinner A13 pin functionsMaxime Ripard2013-03-071-70/+169
| | | | | | | | | | The initial driver contained only a limited set of pins functions because we lacked of documentation on it. Now that we have such documentation, finish to fill the array. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Add Allwinner A10 pin functionsMaxime Ripard2013-03-071-162/+571
| | | | | | | | | | The initial driver contained only a limited set of pins functions because we lacked of documentation on it. Now that we have such documentation, finish to fill the array. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: Declare operation structures as constLaurent Pinchart2013-03-071-3/+3
| | | | | | | | The pinconf, pinctrl and pinmux operation structures hold function pointers that are never modified. Declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: add of_xlate functionMaxime Ripard2013-02-051-0/+20
| | | | | | | | | | | | Since the pin controller of sunxi chips is represented as a single bank in the driver. Since this is neither convenient nor represented that way in the datasheets, define a custom of_xlate function with the layout <bank pin flag> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: pinctrl: sunxi: Add the pinctrl pin set for Allwinner A10Maxime Ripard2013-02-011-0/+554
| | | | | | | | Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sunxi: Document sun5i pins functionsMaxime Ripard2013-02-011-4/+4
| | | | | Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: gpio: Add Allwinner SoCs GPIO driversMaxime Ripard2013-01-291-2/+132
| | | | | | | | | | | | | | | The IP responsible for the muxing on the Allwinner SoCs are also handling the GPIOs on the system. This patch adds the needed driver that relies on the pinctrl driver for most of its operations. The number of pins available for GPIOs operations are already declared in the pinctrl driver, we only need to probe a generic driver to handle the banks available for each SoC. This driver has been tested on a A13-Olinuxino. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5iMaxime Ripard2013-01-221-0/+253
| | | | | | | | Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Add pinctrl driver for Allwinner SoCsMaxime Ripard2013-01-221-0/+548
The Allwinner SoCs have an IP module that handle both the muxing and the GPIOs. This IP has 8 banks of 32 bits, with a number of pins actually useful for each of these banks varying from one to another, and depending on the SoC used on the board. This driver only implements the pinctrl part, the gpio part will come eventually. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
OpenPOWER on IntegriCloud