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| * | PCI: mobiveil: Use pci_parse_request_of_pci_ranges()Rob Herring2019-10-291-19/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Mobiveil host bridge to use the common pci_parse_request_of_pci_ranges(). There's no need to assign the resources to a temporary list first. Just use bridge->windows directly and remove all the temporary list handling. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in> Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: mediatek: Use pci_parse_request_of_pci_ranges()Rob Herring2019-10-291-30/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert Mediatek host bridge to use the common pci_parse_request_of_pci_ranges(). Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Cc: Ryder Lee <ryder.lee@mediatek.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-mediatek@lists.infradead.org
| * | PCI: iproc: Use pci_parse_request_of_pci_ranges()Rob Herring2019-10-292-11/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the iProc host bridge to use the common pci_parse_request_of_pci_ranges(). There's no need to assign the resources to a temporary list, so just use bridge->windows directly. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com
| * | PCI: faraday: Use pci_parse_request_of_pci_ranges()Rob Herring2019-10-291-40/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Faraday host bridge to use the common pci_parse_request_of_pci_ranges(). There's no need to assign the resources to a temporary list first. Just use bridge->windows directly and remove all the temporary list handling. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: dwc: Use pci_parse_request_of_pci_ranges()Rob Herring2019-10-291-20/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Designware host bridge to use the common pci_parse_request_of_pci_ranges(). Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Andrew Murray <andrew.murray@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: altera: Use pci_parse_request_of_pci_ranges()Rob Herring2019-10-291-39/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert altera host bridge to use the common pci_parse_request_of_pci_ranges(). There's no need to assign the resources to a temporary list first. Just use bridge->windows directly and remove all the temporary list handling. If an I/O range is present, then it will now be mapped. It's expected that h/w which doesn't support I/O range will not define one. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: rfi@lists.rocketboards.org
| * | PCI: aardvark: Use pci_parse_request_of_pci_ranges()Rob Herring2019-10-291-56/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Convert aardvark to use the common pci_parse_request_of_pci_ranges(). There's no need to assign the resources to a temporary list first. Just use bridge->windows directly and remove all the temporary list handling. Tested-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'remotes/lorenzo/pci/vmd'Bjorn Helgaas2019-11-281-8/+24
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add VMD bus 224-255 restriction decode (Jon Derrick) - Add VMD 8086:9A0B device ID (Jon Derrick) - Remove Keith from VMD maintainer list (Keith Busch) * remotes/lorenzo/pci/vmd: MAINTAINERS: Remove Keith from VMD maintainer PCI: vmd: Add device id for VMD device 8086:9A0B PCI: vmd: Add bus 224-255 restriction decode
| * | PCI: vmd: Add device id for VMD device 8086:9A0BJon Derrick2019-11-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for this VMD device which supports the bus restriction mode. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: vmd: Add bus 224-255 restriction decodeJon Derrick2019-11-201-8/+22
| |/ | | | | | | | | | | | | | | | | | | VMD bus restrictions are required when IO fabric is multiplexed such that VMD cannot use the entire bus range. This patch adds another bus restriction decode bit that can be set by firmware to restrict the VMD bus range to between 224-255. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | Merge branch 'remotes/lorenzo/pci/uniphier'Bjorn Helgaas2019-11-281-0/+10
|\ \ | | | | | | | | | | | | | | | | | | - Set uniphier to host (RC) mode always (Kunihiko Hayashi) * remotes/lorenzo/pci/uniphier: PCI: uniphier: Set mode register to host mode
| * | PCI: uniphier: Set mode register to host modeKunihiko Hayashi2019-11-211-0/+10
| |/ | | | | | | | | | | | | | | | | | | Set the mode register to host(RC) mode so that the host controller mode is set-up consistently across SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> [lorenzo.pieralisi@arm.com: updated log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
* | Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas2019-11-281-4/+2
|\ \ | | | | | | | | | | | | | | | | | | - Fix Tegra CLKREQ dependency programming (Vidya Sagar) * remotes/lorenzo/pci/tegra: PCI: tegra: Fix CLKREQ dependency programming
| * | PCI: tegra: Fix CLKREQ dependency programmingVidya Sagar2019-10-181-4/+2
| |/ | | | | | | | | | | | | | | | | | | Corrects the programming to provide REFCLK to the downstream device when there is no CLKREQ sideband signal routing present from root port to the endpont. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com>
* | Merge branch 'remotes/lorenzo/pci/rockchip'Bjorn Helgaas2019-11-281-44/+25
|\ \ | | | | | | | | | | | | | | | | | | - Make rockchip 0V9 and 1V8 power regulators non-optional (Robin Murphy) * remotes/lorenzo/pci/rockchip: PCI: rockchip: Make some regulators non-optional
| * | PCI: rockchip: Make some regulators non-optionalRobin Murphy2019-11-201-44/+25
| |/ | | | | | | | | | | | | | | | | | | | | | | The 0V9 and 1V8 supplies power the PCIe block in the SoC itself, and are thus fundamental to PCIe being usable at all. As such, it makes sense to treat them as non-optional and rely on dummy regulators if not explicitly described. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
* | Merge branch 'remotes/lorenzo/pci/rcar'Bjorn Helgaas2019-11-281-23/+27
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Clear bit 0 of MACCTLR before PCIETCTLR.CFINIT per manual (Yoshihiro Shimoda) - Remove unnecessary header include from rcar (Andrew Murray) - Tighten register index checking for rcar inbound range programming (Marek Vasut) - Fix rcar inbound range alignment calculation to improve packing of multiple entries (Marek Vasut) - Update rcar MACCTLR setting to match documentation (Yoshihiro Shimoda) * remotes/lorenzo/pci/rcar: PCI: rcar: Fix missing MACCTLR register setting in initialization sequence PCI: rcar: Recalculate inbound range alignment for each controller entry PCI: rcar: Move the inbound index check PCI: rcar: Remove unnecessary header include (../pci.h)
| * | PCI: rcar: Fix missing MACCTLR register setting in initialization sequenceYoshihiro Shimoda2019-11-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R-Car Gen2/3 manual - available at: https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg1m.html#documents "RZ/G Series User's Manual: Hardware" section strictly enforces the MACCTLR inizialization value - 39.3.1 - "Initial Setting of PCI Express": "Be sure to write the initial value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT". To avoid unexpected behavior and to match the SW initialization sequence guidelines, this patch programs the MACCTLR with the correct value. Note that the MACCTLR.SPCHG bit in the MACCTLR register description reports that "Only writing 1 is valid and writing 0 is invalid" but this "invalid" has to be interpreted as a write-ignore aka "ignored", not "prohibited". Reported-by: Eugeniu Rosca <erosca@de.adit-jv.com> Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: <stable@vger.kernel.org> # v5.2+
| * | PCI: rcar: Recalculate inbound range alignment for each controller entryMarek Vasut2019-11-111-18/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to hardware constraints, the size of each inbound range entry populated into the controller cannot be larger than the alignment of the entry's start address. Currently, the alignment for each "dma-ranges" inbound range is calculated only once for each range and the increment for programming the controller is also derived from it only once. Thus, a "dma-ranges" entry describing a memory at 0x48000000 and size 0x38000000 would lead to multiple controller entries, each 0x08000000 long. This is inefficient, especially considering that by adding the size to the start address, the alignment increases. This patch moves the alignment calculation into the loop populating the controller entries, thus updating the alignment for each controller entry. Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: linux-renesas-soc@vger.kernel.org
| * | PCI: rcar: Move the inbound index checkMarek Vasut2019-11-111-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the 'idx' variable value is stored across multiple calls to rcar_pcie_inbound_ranges() function, and the 'idx' value is used to index registers which are written, subsequent calls might cause the 'idx' value to be high enough to trigger writes into nonexistent registers. Fix this by moving the 'idx' value check to the beginning of the loop. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: linux-renesas-soc@vger.kernel.org
| * | PCI: rcar: Remove unnecessary header include (../pci.h)Andrew Murray2019-11-111-2/+0
| |/ | | | | | | | | | | | | | | | | | | | | Remove unnecessary header include (../pci.h) since it doesn't provide any needed symbols. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | Merge branch 'remotes/lorenzo/pci/mobiveil'Bjorn Helgaas2019-11-281-57/+62
|\ \ | | | | | | | | | | | | | | | | | | | | | - Change mobiveil csr_read()/write() function names that conflict with riscv arch functions (Kefeng Wang) * remotes/lorenzo/pci/mobiveil: PCI: mobiveil: Fix csr_read()/write() build issue
| * | PCI: mobiveil: Fix csr_read()/write() build issueKefeng Wang2019-10-151-57/+62
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISCV has csr_read()/write() macros in arch/riscv/include/asm/csr.h. The same function naming is used in the PCI mobiveil driver thus causing build error. Rename csr_[read,write][l,] to mobiveil_csr_read()/write() to fix it. drivers/pci/controller/pcie-mobiveil.c:238:69: error: macro "csr_read" passed 3 arguments, but takes just 1 static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size) drivers/pci/controller/pcie-mobiveil.c:253:80: error: macro "csr_write" passed 4 arguments, but takes just 2 static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size) Fixes: bcbe0d9a8d93 ("PCI: mobiveil: Unify register accessors") Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Minghuan Lian <Minghuan.Lian@nxp.com> Cc: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> Cc: Andrew Murray <andrew.murray@arm.com>
* | Merge branch 'remotes/lorenzo/pci/meson'Bjorn Helgaas2019-11-281-27/+109
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix meson PERST# GPIO polarity problem (Remi Pommarel) - Add DT bindings for Amlogic Meson G12A (Neil Armstrong) - Fix meson clock names to match DT bindings (Neil Armstrong) - Add meson support for Amlogic G12A SoC with separate shared PHY (Neil Armstrong) - Add meson extended PCIe PHY functions for Amlogic G12A USB3+PCIe combo PHY (Neil Armstrong) - Add arm64 DT for Amlogic G12A PCIe controller node (Neil Armstrong) - Add commented-out description of VIM3 USB3/PCIe mux in arm64 DT (Neil Armstrong) * remotes/lorenzo/pci/meson: arm64: dts: khadas-vim3: add commented support for PCIe arm64: dts: meson-g12a: Add PCIe node phy: meson-g12a-usb3-pcie: Add support for PCIe mode PCI: amlogic: meson: Add support for G12A PCI: amlogic: Fix probed clock names dt-bindings: pci: amlogic, meson-pcie: Add G12A bindings PCI: amlogic: Fix reset assertion via gpio descriptor
| * | PCI: amlogic: meson: Add support for G12ANeil Armstrong2019-10-151-23/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Amlogic G12A SoC using a separate shared PHY. This adds support for fetching a PHY phandle and call the PHY init, reset and power on/off calls instead of writing in the PHY register or toggling the PHY reset line. The MIPI clock and the PHY memory resource are only required for the Amlogic AXG SoC PCIe PHY setup, thus these elements are ignored for the Amlogic G12A having a separate shared PHY. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | PCI: amlogic: Fix probed clock namesNeil Armstrong2019-10-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the clock names used in the probe function according to the bindings. Fixes: 9c0ef6d34fdb ("PCI: amlogic: Add the Amlogic Meson PCIe controller driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | PCI: amlogic: Fix reset assertion via gpio descriptorRemi Pommarel2019-10-151-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally asserting reset signal on gpio would be achieved with: gpiod_set_value_cansleep(reset_gpio, 1); Meson PCI driver set reset value to '0' instead of '1' as it takes into account the PERST# signal polarity. The polarity should be taken care in the device tree instead. This fixes the reset assertion meaning and moves out the polarity configuration in DT (please note that there is no DT currently using this driver). Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
* | Merge branch 'remotes/lorenzo/pci/layerscape'Bjorn Helgaas2019-11-281-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | - Add layerscape LS1028a support (Xiaowei Bao) * remotes/lorenzo/pci/layerscape: PCI: layerscape: Add LS1028a support dt-bindings: pci: layerscape-pci: add compatible strings "fsl, ls1028a-pcie"
| * | PCI: layerscape: Add LS1028a supportXiaowei Bao2019-11-081-0/+1
| |/ | | | | | | | | | | | | | | | | | | Add support for the LS1028a PCIe controller. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <Andrew.Murray@arm.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
* | Merge branch 'remotes/lorenzo/pci/iproc'Bjorn Helgaas2019-11-281-0/+28
|\ \ | | | | | | | | | | | | | | | | | | | | | - Invalidate iProc PAXB address mapping before programming it (Abhishek Shah) * remotes/lorenzo/pci/iproc: PCI: iproc: Invalidate PAXB address mapping before programming it
| * | PCI: iproc: Invalidate PAXB address mapping before programming itAbhishek Shah2019-10-251-0/+28
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Invalidate PAXB inbound/outbound address mapping on probe before programming it. Kernel relies on outbound/inbound windows VALID bit in OARR registers to detect if a window was programmed and if it is set it does not overwrite it. This causes issues on soft reboot (eg kexec) since the host controller does not go through a HW reset on softboot so the kernel detects valid outbound/inbound windows configuration and is not able to reprogramme it as expected. Therefore, in order to make sure outbound/inbound windows are reprogrammed on soft reboot (eg kexec), invalidate memory windows on each probe to fix the issue. Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
* | Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas2019-11-281-29/+179
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add hibernation support for Hyper-V virtual PCI devices (Dexuan Cui) - Track Hyper-V pci_protocol_version per-hbus, not globally (Dexuan Cui) - Avoid kmemleak false positive on hv hbus buffer (Dexuan Cui) * remotes/lorenzo/pci/hv: PCI: hv: Avoid a kmemleak false positive caused by the hbus buffer PCI: hv: Change pci_protocol_version to per-hbus PCI: hv: Add hibernation support PCI: hv: Reorganize the code in preparation of hibernation
| * | PCI: hv: Avoid a kmemleak false positive caused by the hbus bufferDexuan Cui2019-11-261-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent 59bb47985c1d ("mm, sl[aou]b: guarantee natural alignment for kmalloc(power-of-two)"), kzalloc() is able to allocate a 4KB buffer that is guaranteed to be 4KB-aligned. Here the size and alignment of hbus is important because hbus's field retarget_msi_interrupt_params must not cross a 4KB page boundary. Here we prefer kzalloc to get_zeroed_page(), because a buffer allocated by the latter is not tracked and scanned by kmemleak, and hence kmemleak reports the pointer contained in the hbus buffer (i.e. the hpdev struct, which is created in new_pcichild_device() and is tracked by hbus->children) as memory leak (false positive). If the kernel doesn't have 59bb47985c1d, get_zeroed_page() *must* be used to allocate the hbus buffer and we can avoid the kmemleak false positive by using kmemleak_alloc() and kmemleak_free() to ask kmemleak to track and scan the hbus buffer. Reported-by: Lili Deng <v-lide@microsoft.com> Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
| * | PCI: hv: Change pci_protocol_version to per-hbusDexuan Cui2019-11-261-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A VM can have multiple Hyper-V hbus. It's incorrect to set the global variable 'pci_protocol_version' when *every* hbus is initialized in hv_pci_protocol_negotiation(). This is not an issue in practice since every hbus should have the same value of hbus->protocol_version, but we should make the variable per-hbus, so in case we have busses with different protocol versions, the driver can still work correctly. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
| * | PCI: hv: Add hibernation supportDexuan Cui2019-11-261-2/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add suspend() and resume() functions so that Hyper-V virtual PCI devices are handled properly when the VM hibernates and resumes from hibernation. Note that the suspend() function must make sure there are no pending work items before calling vmbus_close(), since it runs in a process context as a callback in dpm_suspend(). When it starts to run, the channel callback hv_pci_onchannelcallback(), which runs in a tasklet context, can be still running concurrently and scheduling new work items onto hbus->wq in hv_pci_devices_present() and hv_pci_eject_device(), and the work item handlers can access the vmbus channel, which can be being closed by hv_pci_suspend(), e.g. the work item handler pci_devices_present_work() -> new_pcichild_device() writes to the vmbus channel. To eliminate the race, hv_pci_suspend() disables the channel callback tasklet, sets hbus->state to hv_pcibus_removing, and re-enables the tasklet. This way, when hv_pci_suspend() proceeds, it knows that no new work item can be scheduled, and then it flushes hbus->wq and safely closes the vmbus channel. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
| * | PCI: hv: Reorganize the code in preparation of hibernationDexuan Cui2019-11-261-15/+28
| |/ | | | | | | | | | | | | | | | | There is no functional change. This is just preparatory for a later patch which adds the hibernation support for the pci-hyperv driver. Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
* | Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas2019-11-281-5/+6
|\ \ | | | | | | | | | | | | | | | | | | - Fix dwc find_next_bit() usage (Niklas Cassel) * remotes/lorenzo/pci/dwc: PCI: dwc: Fix find_next_bit() usage
| * | PCI: dwc: Fix find_next_bit() usageNiklas Cassel2019-10-151-5/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | find_next_bit() takes a parameter of size long, and performs arithmetic that assumes that the argument is of size long. Therefore we cannot pass a u32, since this will cause find_next_bit() to read outside the stack buffer and will produce the following print: BUG: KASAN: stack-out-of-bounds in find_next_bit+0x38/0xb0 Fixes: 1b497e6493c4 ("PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq()") Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
* | Merge branch 'remotes/lorenzo/pci/cadence'Bjorn Helgaas2019-11-289-210/+315
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Refactor Cadence PCIe host controller to use as a library for both host and endpoint (Tom Joseph) * remotes/lorenzo/pci/cadence: PCI: cadence: Move all files to per-device cadence directory PCI: cadence: Refactor driver to use as a core library
| * | PCI: cadence: Move all files to per-device cadence directoryTom Joseph2019-11-119-47/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cadence core library files may be used by various platform drivers. Add a new directory "cadence" to group all the Cadence core library files and the platforms using Cadence core library. Signed-off-by: Tom Joseph <tjoseph@cadence.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | PCI: cadence: Refactor driver to use as a core libraryTom Joseph2019-11-116-187/+287
| |/ | | | | | | | | | | | | | | | | | | | | Cadence PCIe host and endpoint IP may be embedded into a variety of SoCs/platforms. Let's extract the platform related APIs/Structures in the current driver to a separate file (pcie-cadence-plat.c), such that the common functionality can be used by future platforms. Signed-off-by: Tom Joseph <tjoseph@cadence.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
* | Merge branch 'remotes/lorenzo/pci/aardvark'Bjorn Helgaas2019-11-281-15/+57
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use LTSSM state to build link training flag since Aardvark doesn't implement the Link Training bit (Remi Pommarel) - Delay before training Aardvark link in case PERST# was asserted before the driver probe (Remi Pommarel) - Fix Aardvark issues with Root Control reads and writes (Remi Pommarel) - Don't rely on jiffies in Aardvark config access path since interrupts may be disabled (Remi Pommarel) - Fix Aardvark big-endian support (Grzegorz Jaszczyk) - Fix bridge emulation big-endian support (Grzegorz Jaszczyk) * remotes/lorenzo/pci/aardvark: PCI: pci-bridge-emul: Fix big-endian support PCI: aardvark: Fix big endian support PCI: aardvark: Don't rely on jiffies while holding spinlock PCI: aardvark: Fix PCI_EXP_RTCTL register configuration PCI: aardvark: Wait for endpoint to be ready before training link PCI: aardvark: Use LTSSM state to build link training flag
| * | PCI: aardvark: Fix big endian supportGrzegorz Jaszczyk2019-10-171-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialise every multiple-byte field of emulated PCI bridge config space with proper cpu_to_le* macro. This is required since the structure describing config space of emulated bridge assumes little-endian convention. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: aardvark: Don't rely on jiffies while holding spinlockRemi Pommarel2019-10-151-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | advk_pcie_wait_pio() can be called while holding a spinlock (from pci_bus_read_config_dword()), then depends on jiffies in order to timeout while polling on PIO state registers. In the case the PIO transaction failed, the timeout will never happen and will also cause the cpu to stall. This decrements a variable and wait instead of using jiffies. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * | PCI: aardvark: Fix PCI_EXP_RTCTL register configurationRemi Pommarel2019-10-151-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI_EXP_RTCTL is used to activate PME interrupt only, so writing into it should not modify other interrupts' mask. The ISR mask polarity was also inverted, when PCI_EXP_RTCTL_PMEIE is set PCIE_MSG_PM_PME_MASK mask bit should actually be cleared. Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * | PCI: aardvark: Wait for endpoint to be ready before training linkRemi Pommarel2019-10-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When configuring pcie reset pin from gpio (e.g. initially set by u-boot) to pcie function this pin goes low for a brief moment asserting the PERST# signal. Thus connected device enters fundamental reset process and link configuration can only begin after a minimal 100ms delay (see [1]). Because the pin configuration comes from the "default" pinctrl it is implicitly configured before the probe callback is called: driver_probe_device() really_probe() ... pinctrl_bind_pins() /* Here pin goes from gpio to PCIE reset function and PERST# is asserted */ ... drv->probe() [1] "PCI Express Base Specification", REV. 4.0 PCI Express, February 19 2014, 6.6.1 Conventional Reset Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| * | PCI: aardvark: Use LTSSM state to build link training flagRemi Pommarel2019-10-141-1/+28
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aardvark's PCI_EXP_LNKSTA_LT flag in its link status register is not implemented and does not reflect the actual link training state (the flag is always set to 0). In order to support link re-training feature this flag has to be emulated. The Link Training and Status State Machine (LTSSM) flag in Aardvark LMI config register could be used as a link training indicator. Indeed if the LTSSM is in L0 or upper state then link training has completed (see [1]). Unfortunately because after asking a link retraining it takes a while for the LTSSM state to become less than 0x10 (due to L0s to recovery state transition delays), LTSSM can still be in L0 while link training has not finished yet. So this waits for link to be in recovery or lesser state before returning after asking for a link retrain. [1] "PCI Express Base Specification", REV. 4.0 PCI Express, February 19 2014, Table 4-14 Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Tested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* | Merge branch 'pci/resource'Bjorn Helgaas2019-11-286-10/+10
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Protect pci_reassign_bridge_resources() against concurrent addition/removal (Benjamin Herrenschmidt) - Fix bridge dma_ranges resource list cleanup (Rob Herring) - Add PCI_STD_NUM_BARS for the number of standard BARs (Denis Efremov) - Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters to control the MMIO and prefetchable MMIO window sizes of hotplug bridges independently (Nicholas Johnson) - Fix MMIO/MMIO_PREF window assignment that assigned more space than desired (Nicholas Johnson) - Only enforce bus numbers from bridge EA if the bridge has EA devices downstream (Subbaraya Sundeep) * pci/resource: PCI: Do not use bus number zero from EA capability PCI: Avoid double hpmemsize MMIO window assignment PCI: Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters PCI: Add PCI_STD_NUM_BARS for the number of standard BARs PCI: Fix missing bridge dma_ranges resource list cleanup PCI: Protect pci_reassign_bridge_resources() against concurrent addition/removal
| * | PCI: Add PCI_STD_NUM_BARS for the number of standard BARsDenis Efremov2019-10-146-10/+10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code that iterates over all standard PCI BARs typically uses PCI_STD_RESOURCE_END. However, that requires the unusual test "i <= PCI_STD_RESOURCE_END" rather than something the typical "i < PCI_STD_NUM_BARS". Add a definition for PCI_STD_NUM_BARS and change loops to use the more idiomatic C style to help avoid fencepost errors. Link: https://lore.kernel.org/r/20190927234026.23342-1-efremov@linux.com Link: https://lore.kernel.org/r/20190927234308.23935-1-efremov@linux.com Link: https://lore.kernel.org/r/20190916204158.6889-3-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sebastian Ott <sebott@linux.ibm.com> # arch/s390/ Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> # video/fbdev/ Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> # pci/controller/dwc/ Acked-by: Jack Wang <jinpu.wang@cloud.ionos.com> # scsi/pm8001/ Acked-by: Martin K. Petersen <martin.petersen@oracle.com> # scsi/pm8001/ Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # memstick/
* | PCI: Remove unused includes and superfluous struct declarationKrzysztof Wilczynski2019-11-213-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove <linux/pci.h> and <linux/msi.h> from being included directly as part of the include/linux/of_pci.h, and remove superfluous declaration of struct of_phandle_args. Move users of include <linux/of_pci.h> to include <linux/pci.h> and <linux/msi.h> directly rather than rely on both being included transitively through <linux/of_pci.h>. Link: https://lore.kernel.org/r/20190903113059.2901-1-kw@linux.com Signed-off-by: Krzysztof Wilczynski <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>
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