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| * ixgbe: Make FCoE allocation and configuration closer to how rings workAlexander Duyck2012-07-194-122/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the behavior of the FCoE configuration so that it is much closer to how the main body of the ixgbe driver works for ring allocation. The first piece is the ixgbe_fcoe_ddp_enable/disable calls. These allocate the percpu values and if successful set the fcoe_ddp_xid value indicating that we can support DDP. The next piece is the ixgbe_setup/free_ddp_resources calls. These are called on open/close and will allocate and free the DMA pools. Finally ixgbe_configure_fcoe is now just register configuration. It can go through and enable the registers for the FCoE redirection offload, and FIP configuration without any interference from the DDP pool allocation. The net result of all this is two fold. First it adds a certain amount of exception handling. So for example if ixgbe_setup_fcoe_resources fails we will actually generate an error in open and refuse to bring up the interface. Secondly it provides a much more graceful failure case than the previous model which would skip setting up the registers for FCoE on failure to allocate DDP resources leaving no Rx functionality enabled instead of just disabling DDP. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Merge all FCoE percpu values into a single structureAlexander Duyck2012-07-193-86/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change merges the 2 statistics values for noddp and noddp_ext_buff and the dma_pool into a single structure that can be allocated per CPU. The advantages to this are several fold. First we only need to do one alloc_percpu call now instead of 3, so that means less overhead for handling memory allocation failures. Secondly in the case of ixgbe_fcoe_ddp_setup we only need to call get_cpu once which makes things a bit cleaner since we can drop a put_cpu() from the exception path. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Cleanup configuration of FCoE registersAlexander Duyck2012-07-192-27/+32
| | | | | | | | | | | | | | | | | | | | | | This change makes it so we always use the FCoE redirection table. We just set all 8 entries to the same value in the case of only having one queue for FCoE. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Drop references to deprecated pci_ DMA api and instead use dma_ APIAlexander Duyck2012-07-192-17/+17
| | | | | | | | | | | | | | | | | | | | | | The networking side of the code had already been updated to use dma_ calls instead of the old pci_ calls. However it looks like the FCoE code was never updated. This change goes through and moves everything from the pci APIs to the dma APIs. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Fix memory leak when SR-IOV VFs are direct assignedAlexander Duyck2012-07-191-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The VF driver had a memory leak that would occur if VFs were assigned to a guest. The amount of leak would vary with the number of VFs but could max out at about 14K per PF. To reproduce the leak all you would need to do is enable all the VFs on the first PF. Then start a loop of loading and unloading the driver with max_vfs=63 for the first port. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Use VMDq offset to indicate the default poolAlexander Duyck2012-07-193-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | This change makes it so that we can use the VMDq ring feature offset value to determine the default pool instead of using num_vfs. The reason for this change is to avoid issues should we fail to allocate vfinfo but have pre-existing VFs. What should happen in this case is that num_vfs will go to 0, but the VMDq offset will contain the location of the first PF pool. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Sibai Li <Sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* | ixgbe: use PCI_VENDOR_ID_INTELJon Mason2012-07-203-9/+6
|/ | | | | | | | | | | | | | | | | | Use PCI_VENDOR_ID_INTEL from pci_ids.h instead of creating its own vendor ID #define. Signed-off-by: Jon Mason <jdmason@kudzu.us> Cc: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Cc: Jesse Brandeburg <jesse.brandeburg@intel.com> Cc: Bruce Allan <bruce.w.allan@intel.com> Cc: Carolyn Wyborny <carolyn.wyborny@intel.com> Cc: Don Skidmore <donald.c.skidmore@intel.com> Cc: Greg Rose <gregory.v.rose@intel.com> Cc: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Cc: Alex Duyck <alexander.h.duyck@intel.com> Cc: John Ronciak <john.ronciak@intel.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ixgbe: Cleanup holes in flags after removing several of themAlexander Duyck2012-07-181-25/+25
| | | | | | | | | | This change is just meant to defragment the flags as there are several hole that have been introduced since several features, or the flags for them, have been removed. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Retire RSS enabled and capable flagsAlexander Duyck2012-07-184-37/+8
| | | | | | | | | | | All of our hardware supports RSS even if it is only for a single queue. So instead of toting around the RSS enable flag I am updating the code so that all devices are enabled and if we want to disable RSS it is indicated via the RSS mask. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Add support for SR-IOV w/ DCB or RSSAlexander Duyck2012-07-184-47/+423
| | | | | | | | | | | | | | | | | | | This change essentially makes it so that we can enable almost all of the features all at once. This patch allows for the combination of SR-IOV, DCB, and FCoE in the case of the x540. It also beefs up the SR-IOV by adding support for RSS to the PF. The testing matrix gets to be very complex for this patch as there are a number of different features and subsets for queueing options. I tried to narrow these down a bit by restricting the PF to only supporting 4TC DCB when it is enabled in addition to SR-IOV. Cc: Greg Rose <gregory.v.rose@intel.com> Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Update configure virtualization to allow for multiple PF poolsAlexander Duyck2012-07-181-12/+12
| | | | | | | | | | | | | | This change allows all pools from the default pool forward to be enabled vi ixgbe_configure_virtualization. This is needed as we are planning to use queues belonging to adjacent pools for FCoE when SR-IOV and FCoE are both enabled. In addition this patch contains some minor formatting changes as there were a few spots that seemed to be in need of some cleanup. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Cleanup logic for MRQC and MTQC configurationAlexander Duyck2012-07-171-50/+66
| | | | | | | | | | | | | | | | | | | | | | This change is meant to make the code much more readable for MTQC and MRQC configuration. The big change is that I simplified much of the logic so that we are essentially handling just 4 cases and their variants. In the cases where RSS is disabled we are actually just programming the RETA table with all 1s resulting in a single queue RSS. In the case of SR-IOV I am treating that as a subset of VMDq. This all results int he following configuration for the hardware: DCB En Dis VMDq En VMDQ/DCB VMDq/RSS Dis DCB/RSS RSS Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Update the logic for ixgbe_cache_ring_dcb and DCB RSS configurationAlexander Duyck2012-07-172-50/+42
| | | | | | | | | | | | | | | | | This change cleans up some of the logic in an attempt to try and simplify things for how we are configuring DCB w/ RSS. In this patch I basically did 3 things. I updated the logic for getting the first register index. I applied the fact that all TCs get the same number of queues to simplify the looping logic in caching the DCB ring register. Finally I updated how we configure the RQTC register to match the fact that all TCs are assigned the same number of queues. Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Move configuration of set_real_num_rx/tx_queues into openAlexander Duyck2012-07-172-56/+38
| | | | | | | | | | | It makes much more sense for us to configure the real number of Tx and Rx queues in the ixgbe_open call than it does in ixgbe_set_num_queues. By setting the number in ixgbe_open we can avoid a number of unecessary updates and only have to make the calls once. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Handle failures in the ixgbe_setup_rx/tx_resources callsAlexander Duyck2012-07-171-4/+16
| | | | | | | | | | | | Previously we were exiting without cleaning up the memory internally on the ixgbe_setup_rx_resources and ixgbe_setup_tx_resources calls. Instead of forcing the caller to clean things up for us we should instead just unwind the rings and free the memory as we go. This way we can more gracefully clean up the rings in the event of an allocation failure. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Ping the VFs on link status change to trigger link changeAlexander Duyck2012-07-171-0/+6
| | | | | | | | | | | | | | When the link status changes on the PF we need to notify the VFs. In order to do this we should ping all of the VFs in order to trigger a link status change on them as well. This fixes issues in which the PF would reset, but the VF didn't because the NAK flag was not set in the VF mailbox. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* Merge branch 'master' of ↵David S. Miller2012-07-167-212/+226
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next Jett Kirsher says: ==================== This series contains updates to e1000e and ixgbe. ... Alexander Duyck (5): ixgbe: Simplify logic for getting traffic class from user priority ixgbe: Cleanup unpacking code for DCB ixgbe: Populate the prio_tc_map in ixgbe_setup_tc ixgbe: Add function for obtaining FCoE TC based on FCoE user priority ixgbe: Merge FCoE set_num and cache_ring calls into RSS/DCB config ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
| * ixgbe: Merge FCoE set_num and cache_ring calls into RSS/DCB configAlexander Duyck2012-07-142-147/+129
| | | | | | | | | | | | | | | | | | | | | | This change merges the ixgbe_cache_ring_fcoe and ixgbe_set_fcoe_queues logic into the DCB and RSS initialization calls. Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Add function for obtaining FCoE TC based on FCoE user priorityAlexander Duyck2012-07-144-15/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | In upcoming patches it will become increasingly common to need to determine the FCoE traffic class in order to determine the correct queues for FCoE. In order to make this easier I am adding a function for obtaining the FCoE traffic class based on the user priority. Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Populate the prio_tc_map in ixgbe_setup_tcAlexander Duyck2012-07-144-23/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There were cases where the prio_tc_map was not populated when we were calling open. This will result in us incorrectly configuring the traffic classes when DCB is enabled. In order to correct this I have updated the code so that we now populate the values prior to allocating the q_vectors and calling ixgbe_open. Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Cleanup unpacking code for DCBAlexander Duyck2012-07-141-25/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | This is meant to be a generic clean-up of the remaining functions for unpacking data from the DCB structures. The only real changes are: replaced the variable i with tc for functions that were looping through the traffic classes, and added a pointer for tc_class instead of path since that way we only need to pull the pointer once instead of once per loop. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Simplify logic for getting traffic class from user priorityAlexander Duyck2012-07-141-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is meant to help simplify the logic for getting traffic classes from user priorities. To do this I am adding a function named ixgbe_dcb_get_tc_from_up that will go through the traffic classes in reverse order in order to determine which traffic class contains a bit for a given user priority. Adding a declaration for this new function to the header so that we have a centralized means for sorting out traffic classes belonging to features such as FCoE. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* | ethernet: Use eth_random_addrJoe Perches2012-07-161-1/+1
|/ | | | | | | | Convert the existing uses of random_ether_addr to the new eth_random_addr. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* ixgbe: Merge RSS and flow director ring register caching and configurationAlexander Duyck2012-07-111-74/+24
| | | | | | | | | | | | | | There are really only 3 modes that can control the number of queues. Those are RSS, DCB, and VMDq/SR-IOV. Currently we have things much more broken up than they need to be for how we are configuring the rings. In order to try and straiten some of this out I am going to start merging similar functionality into single functions. To start with I am merging the Flow Director ring configuration into the RSS ring configuration since Flow Director cannot function with DCB or SR-IOV. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Clean up a useless switch statement and dead code in configure_srrctlAlexander Duyck2012-07-111-21/+15
| | | | | | | | | | | | | This patch replaces a switch statement for an 82598 workaround with an if statement that only applies to 82598. In addition I am pulling out several dead pieces of code and instead of reading the SRRCTL register and then modifying it we are just writing a value which we generate from scratch. Finally I am also removing any drop enable related code since that was moved to a function of its own. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Add feature offset value to ring featuresAlexander Duyck2012-07-114-18/+16
| | | | | | | | | | | | The mask value for ring features was overloaded for FCoE which can lead to some confusion. In order to avoid any confusion I am splitting the mask value and adding an offset value. This can be used for the start of the FCoE rings, and in the future I hope to use it to store the start of the registers for SR-IOV. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: Add upper limit to ring featuresAlexander Duyck2012-07-114-8/+14
| | | | | | | | | | | | We are currently using indices to indicate the upper limit on a ring feature. However since we can switch back and forth on features such as DCB and that has effects on other features such as RSS it is preferable to instead store the upper limit separate from the current value for the number of rings related to the feature. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: count q_vectors instead of MSI-X vectorsAlexander Duyck2012-07-114-89/+59
| | | | | | | | | | | It makes much more sense for us to count q_vectors instead of MSI-X vectors. We were using num_msix_vectors to find the number of q_vectors in multiple places. This was wasteful since we only had one place that actually needs the number of MSI-X vectors and that is in slow path. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2012-07-101-0/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: net/batman-adv/bridge_loop_avoidance.c net/batman-adv/bridge_loop_avoidance.h net/batman-adv/soft-interface.c net/mac80211/mlme.c With merge help from Antonio Quartulli (batman-adv) and Stephen Rothwell (drivers/net/usb/qmi_wwan.c). The net/mac80211/mlme.c conflict seemed easy enough, accounting for a conversion to some new tracing macros. Signed-off-by: David S. Miller <davem@davemloft.net>
| * ixgbe: DCB and SR-IOV can not co-exist and will cause hangsAlexander Duyck2012-07-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCB and SR-IOV cannot currently be enabled at the same time as the queueing schemes are incompatible. If they are both enabled it will result in Tx hangs since only the first Tx queue will be able to transmit any traffic. This simple fix for this is to block us from enabling TCs in ixgbe_setup_tc if SR-IOV is enabled. This change will be reverted once we can support SR-IOV and DCB coexistence. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Acked-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | drivers/net/ethernet: Fix (nearly-)kernel-doc comments for various functionsBen Hutchings2012-07-106-50/+52
| | | | | | | | | | | | | | | | | | | | Fix incorrect start markers, wrapped summary lines, missing section breaks, incorrect separators, and some name mismatches. Delete a few that are content-free. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2012-06-283-7/+13
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/net/caif/caif_hsi.c drivers/net/usb/qmi_wwan.c The qmi_wwan merge was trivial. The caif_hsi.c, on the other hand, was not. It's a conflict between 1c385f1fdf6f9c66d982802cd74349c040980b50 ("caif-hsi: Replace platform device with ops structure.") in the net-next tree and commit 39abbaef19cd0a30be93794aa4773c779c3eb1f3 ("caif-hsi: Postpone init of HIS until open()") in the net tree. I did my best with that one and will ask Sjur to check it out. Signed-off-by: David S. Miller <davem@davemloft.net>
| * ixgbe: Do not pad FCoE frames as this can cause issues with FCoE DDPAlexander Duyck2012-06-263-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FCoE target mode was experiencing issues due to the fact that we were sending up data frames that were padded to 60 bytes after the DDP logic had already stripped the frame down to 52 or 56 depending on the use of VLANs. This was resulting in the FCoE DDP logic having issues since it thought the frame still had data in it due to the padding. To resolve this, adding code so that we do not pad FCoE frames prior to handling them to the stack. CC: <stable@vger.kernel.org> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2012-06-252-3/+12
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/net/usb/qmi_wwan.c net/batman-adv/translation-table.c net/ipv6/route.c qmi_wwan.c resolution provided by Bjørn Mork. batman-adv conflict is dealing merely with the changes of global function names to have a proper subsystem prefix. ipv6's route.c conflict is merely two side-by-side additions of network namespace methods. Signed-off-by: David S. Miller <davem@davemloft.net>
| * ixgbe: Fix memory leak in ixgbe when receiving traffic on DDP enabled ringsAlexander Duyck2012-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a memory leak that was introduced in the 3.4 kernel. The leak occurred when FCoE was enabled and traffic was passed over the FCoE rings reserved for FCoE. The memory leak was due to us not populating the compound page information on the order 1 pages needed for FCoE. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
| * ixgbe: Fix PHC loophole allowing misconfiguration of increment registerJacob Keller2012-06-171-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a potential hole when configuring the cycle counter used to generate the nanosecond time clock. This clock is based off of the SYSTIME registers along with the TIMINCA registers. The TIMINCA register determines the increment to be added to the SYSTIME registers every DMA clock tick. This register needs to be reconfigured whenever the link-speed changes. However, the value calculated stays the same when link is down and when link is up. Misconfiguration can occur if the link status changes due to a reset, which causes the TIMINCA register to be reset. This reset puts the device in an unstable state where the SYSTIME registers stop incrementing and the PTP protocol does not function. The solution is to double check the TIMINCA value and always reset the value if the register is zero. This prevents a misconfiguration bug that halts the PHC. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Acked-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | ixgbe: simplify padding and length checksStephen Hemminger2012-06-211-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The check for length <= 0 is bogus because length is unsigned, and network stack never sends zero length packets (unless it is totally broken). The check for really small packets can be optimized (using unlikely) and calling skb_pad directly. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | ixgbe: clean up ixgbe_get_settings ethtool functionJacob Keller2012-06-201-85/+62
| | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up the method used for determining the link speed of devices. The old method re-wrote some logic already existing in a mac.ops function which should be used instead. The result is much simpler to understand and removes a strange double-check of logic, as well as reducing code redundancy. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* | ixgbe: add support for 1G SX modulesJacob Keller2012-06-203-5/+24
| | | | | | | | | | | | | | | | | | | | This patch adds support for 1G Fiber PHY modules (SFP+ modules). This support comes along side support for 1G Copper PHY modules, but uses a different PHY type (ixgbe_sfp_type_1g_sx_core). Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* | ixgbe: Check PTP Rx timestamps via BPF filterJacob Keller2012-06-143-14/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a potential Rx timestamp deadlock that causes the Rx timestamping to stall indefinitely. The issue could occur when a PTP packet is timestamped by hardware but never reaches the Rx queue. In order to prevent a permanent loss of timestamping, the RXSTMP(L/H) registers have to be read to unlock them. (This used to only occur when a packet that was timestamped reached the software.) However the registers can't be read early otherwise there is no way to correlate them to the packet. This patch introduces a filter function which can be used to determine if a packet should have been timestamped. Supplied with the filter setup by the hwtstamp ioctl, check to make sure the PTP protocol and message type match the expected values. If so, then read the timestamp registers (to free them.) At this point check the descriptor bit, if the bit is set then we know this packet correlates to the timestamp stored in the RXTSTAMP registers. Otherwise, assume that packet was dropped by the hardware, and ignore this timestamp value. However, we have at least unlocked the rxtstamp registers for future timestamping. Due to the way the driver handles skb data, it cannot be directly accessed. In order to work around this, a copy of the skb data into a linear buffer is made. From this buffer it becomes possible to read the data correctly Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Reviewed-by: Richard Cochran <richardcochran@gmail.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* | ixgbe: PTP Fix hwtstamp mode settingsJacob Keller2012-06-141-15/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling the hwtstamp mode for Rx timestamping the V2 ptp event type specific modes (Delay Request and Sync) have been rolled into the V2 all event packet modes, in order to more accurately represent what hardware is doing. Hardware always timestamps the Path delay packets when a V2 mode is selected, regardless of what type was selected (in order to always support Path delay mode). However this means the user selected modes of timestamping only Sync or Delay Request is not truly supported. This patch correctly sets the mode for the hwtstamp config and returns to the user that all V2 event packets will be timestamped. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* | ixgbe: ptp code cleanupJacob Keller2012-06-142-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes two minor nits from Richard Cochran. The first is a case of ambitious line wrapping that wasn't necessary. The second is to re-order the flag checks for PPS support. Previously, the hardware test was done first, and the interrupt flag test was done second. Now, test the interrupt flag and use the unlikely macro. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* | ixgbe: do not compile ixgbe_sysfs.c when CONFIG_IXGBE_HWMON is not setEmil Tantilov2012-06-142-4/+2
| | | | | | | | | | | | | | | | | | | | ixgbe_sysfs.c is only needed when CONFIG_IXGBE_HWMON is configured in the kernel. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Acked-by: Don Skidmore <Donald.c.skidmore@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* | ixgbe: align flow control DV macros with datasheetJohn Fastabend2012-06-141-15/+22
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flow control DV macros are used to calculate the flow control high and low thresholds. This patch annotates these macros slightly better and fixes the issues below. The macro variables are renamed LINK to _max_frame_link and TC to _max_frame_tc. This was to avoid confusion and make them more readable. It was found that people auditing the code read TC to be 'traffic class' in the 802.1Q definition instead of the max frame size of the tc. Hopefully it is clear now. This audit also found the following real deviations from the theoretical values. Fixed in this patch. * I multiplied the DV calculations by (36/25) which always evaluates to 1. This does not match the intended theoretical value of 1.44. * IXGBE_BT2KB added 1023 to account for rounding however this really should be 8 * 1023 - 1 to account for division by 8k. * x2 multiplication of max frame in DV calculations to account for updated hardware recommendations. With this patch the DV values are inline with the recommendations in the 82599 and 82598 data sheets. Its worth noting I did not see any dropped frames with flow control on in my experiments without this patch. However aligning with the hardware specs and recommendations seems like a good idea here to account for worst case scenarios. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: IXGBE_RXD_STAT_VP set even with Rx stripping enabledJohn Fastabend2012-06-051-2/+5
| | | | | | | | | | | | | | | | | The hardware bit IXGBE_RXD_STAT_VP appears to be set even when Rx stripping is disabled. This results in passing frames up the stack which do not have the 802.1Q tag stripped but have the tci bits set as if it was. Working around this with a check for the feature flag bit. I would welcome any better ideas or a pointer to exactly which bits in the hardware register need to be cleared to get the IXGBE_RXD_STAT_VP bit to be set per data sheet. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Acked-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Marcus Dennis <marcusx.e.dennis@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: fix_features rxvlan is independent of DCB and needs to be setJohn Fastabend2012-06-051-10/+5
| | | | | | | | | | | | | DCB can be used independent of if RX VLAN stripping is enabled or disabled so remove erroneous check. Also enable or disable VLAN stripping when features are applied so hardware and feature flags are in sync. CC: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Marcus Dennis <marcusx.e.dennis@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: update version numberDon Skidmore2012-05-091-2/+2
| | | | | | | | | Update version number to better match the version of the out of tree driver with similar functionality. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: cleanup the hwmon function callsDon Skidmore2012-05-093-32/+10
| | | | | | | | | | When the hwmon code was initially added it was with the assumption that a sysfs patch would be also coming soon. Since that isn't the case some clean up needs to be done. This patch does that. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: support software timestampingJacob Keller2012-05-091-0/+2
| | | | | | | | | | Kernel software timestamping requires that the driver calls skb_tx_timestamp just before passing the skb to the MAC, in order to provide the best software timestamps. This patch adds this call for that support. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
* ixgbe: add support for get_ts_infoJacob Keller2012-05-091-0/+41
| | | | | | | | | | This patch adds support for the ethtool get_ts_info operation, which enables access of available timestamp/timesync support for that device. It can query which ptp clock device is associated with the particular port. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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