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* mmc: sdhci: Allow override of get_cd() called from sdhci_request()Adrian Hunter2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | commit 8d28b7a72fe18bcdcdb047243ba8fec36b149955 upstream. Drivers may need to provide their own get_cd() mmc host op, but currently the internals of the current op (sdhci_get_cd()) are provided by sdhci_do_get_cd() which is also called from sdhci_request(). To allow override of the get_cd functionality, change sdhci_request() to call ->get_cd() instead of sdhci_do_get_cd(). Note, in the future the call to ->get_cd() will likely be removed from sdhci_request() since most drivers don't need actually it. However this change is being done now to facilitate a subsequent bug fix. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci: Allow override of mmc host operationsAdrian Hunter2016-03-032-1/+3
| | | | | | | | | | | | | | | | | | | commit bf60e592a1af4d6f65dd54593250183f14360eed upstream. In the past, fixes for specific hardware devices were implemented in sdhci using quirks. That approach is no longer accepted because the growing number of quirks was starting to make the code difficult to understand and maintain. One alternative to quirks, is to allow drivers to override the default mmc host operations. This patch makes it easy to do that, and it is needed for a subsequent bug fix, for which separate patches are provided. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci-pci: Fix card detect race for Intel BXT/APLAdrian Hunter2016-03-031-0/+31
| | | | | | | | | | | | | | | | | | | | commit 163cbe31e5163459908a41a2b4e0d33a28fd557a upstream. Intel BXT/APL use a card detect GPIO however the host controller will not enable bus power unless it's card detect also reflects the presence of a card. Unfortunately those 2 things race which can result in commands not starting, after which the controller does nothing and there is a 10 second wait for the driver's 10-second timer to timeout. That is fixed by having the driver look also at the present state register to determine if the card is present. Consequently, provide a 'get_cd' mmc host operation for BXT/APL that does that. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: pxamci: fix again read-only gpio detection polarityRobert Jarzmik2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | commit 41c89159a6ae5472d39ed8bded5b3b4e07a37944 upstream. The commit fixing the conversion of pxamci to slot-gpio API fixed the inverted the logic of the read-only gpio. Unfortunately, the commit was tested on a non-inverted gpio, and not on the inverted one. And the fix did work partially, by luck. This is the remaining missing part of the fix, trivial but still necessary. Fixes: Fixes: 26d49fe71953 ("mmc: pxamci: fix read-only gpio detection polarity") Reported-by: Andrea Adami <andrea.adami@gmail.com> Tested-by: Andrea Adami <andrea.adami@gmail.com> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci-acpi: Fix card detect race for Intel BXT/APLAdrian Hunter2016-03-031-0/+30
| | | | | | | | | | | | | | | | | | | | commit 6a645dd87a5a506779810d7d9935c25fc2ef4687 upstream. Intel BXT/APL use a card detect GPIO however the host controller will not enable bus power unless it's card detect also reflects the presence of a card. Unfortunately those 2 things race which can result in commands not starting, after which the controller does nothing and there is a 10 second wait for the driver's 10-second timer to timeout. That is fixed by having the driver look also at the present state register to determine if the card is present. Consequently, provide a 'get_cd' mmc host operation for BXT/APL that does that. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: mmci: fix an ages old detection errorLinus Walleij2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | commit 0bcb7efdff63564e80fe84dd36a9fbdfbf6697a4 upstream. commit 4956e10903fd ("ARM: 6244/1: mmci: add variant data and default MCICLOCK support") added variant data for ARM, U300 and Ux500 variants. The Nomadik NHK8815/8820 variant was erroneously labeled as a U300 variant, and when the proper Nomadik variant was later introduced in commit 34fd421349ff ("ARM: 7378/1: mmci: add support for the Nomadik MMCI variant") this was not fixes. Let's say this fixes the latter commit as there was no proper Nomadik support until then. Fixes: 34fd421349ff ("ARM: 7378/1: mmci: add support for the Nomadik...") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: core: Enable tuning according to the actual timingCarlo Caione2016-03-032-6/+6
| | | | | | | | | | | | | | | | | | | | commit e10c321977091f163eceedec0650e0ef4b3cf4bb upstream. While in sdhci_execute_tuning() the choice whether or not to enable the tuning is done on the actual timing, in the mmc_sdio_init_uhs_card() the check is done on the capability of the card. This difference is causing some issues with some SDIO cards in DDR50 mode where the CDM19 is wrongly issued. With this patch we modify the check in both mmc_(sd|sdio)_init_uhs_card() functions to take the proper decision only according to the actual timing specification. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci: Fix sdhci_runtime_pm_bus_on/off()Adrian Hunter2016-03-031-2/+2
| | | | | | | | | | | | | | | | | | | | | commit 5c671c410c8704800f4f1673b6f572137e7e6ddd upstream. sdhci has a legacy facility to prevent runtime suspend if the bus power is on. This is needed in cases where the power to the card is dependent on the bus power. It is controlled by a pair of functions: sdhci_runtime_pm_bus_on() and sdhci_runtime_pm_bus_off(). These functions use a boolean variable 'bus_on' to ensure changes are always paired. There is an additional check for 'runtime_suspended' which is the problem. In fact, its use is ill-conceived as the only requirement for the logic is that 'on' and 'off' are paired, which is actually broken by the check, for example if the bus power is turned on during runtime resume. So remove the check. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: mmc: Fix incorrect use of driver strength switching HS200 and HS400Wenkai Du2016-03-031-4/+2
| | | | | | | | | | | | | | | | | | | commit adb24d42a516bca8b9741ed21206509daaab5b13 upstream. Commit cc4f414c885c ("mmc: mmc: Add driver strength selection") added driver strength selection for eMMC HS200 and HS400 modes. That patch also set the driver stength when transitioning through High Speed mode to HS200/HS400, but driver strength is not defined for High Speed mode. While the JEDEC specification is not clear on this point it has been observed to cause problems for some eMMC, and removing the driver strength setting in this case makes it consistent with the normal use of High Speed mode. Signed-off-by: Wenkai Du <wenkai.du@intel.com> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdio: Fix invalid vdd in voltage switch power cycleAdrian Hunter2016-03-031-1/+1
| | | | | | | | | | | | | | | | | commit d9bfbb95ed598a09cf336adb0f190ee0ff802f0d upstream. The 'ocr' parameter passed to mmc_set_signal_voltage() defines the power-on voltage used when power cycling after a failure to set the voltage. However, in the case of mmc_sdio_init_card(), the value passed has the R4_18V_PRESENT flag set which is not valid for power-on and results in an invalid vdd. Fix by passing the card's ocr value which does not have the flag. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci: Fix DMA descriptor with zero data lengthAdrian Hunter2016-03-031-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 347ea32dc118326c4f2636928239a29d192cc9b8 upstream. SDHCI has built-in DMA called ADMA2. ADMA2 uses a descriptor table to define DMA scatter-gather. Each desciptor can specify a data length up to 65536 bytes, however the length field is only 16-bits so zero means 65536. Consequently, putting zero when the size is zero must not be allowed. This patch fixes one case where zero data length could be set inadvertently. The problem happens because unaligned data gets split and the code did not consider that the remaining aligned portion might be zero length. That case really only happens for SDIO because SD and eMMC cards transfer blocks that are invariably sector- aligned. For SDIO, access to function registers is done by data transfer (CMD53) when the register is bigger than 1 byte. Generally registers are 4 bytes but 2-byte registers are possible. So DMA of 4 bytes or less can happen. When 32-bit DMA is used, the data alignment must be 4, so 4-byte transfers won't casue a problem, but a 2-byte transfer could. However with the introduction of 64-bit DMA, the data alignment for 64-bit DMA was made 8 bytes, so all 4-byte transfers not on 8-byte boundaries get "split" into a 4-byte chunk and a 0-byte chunk, thereby hitting the bug. In fact, a closer look at the SDHCI specs indicates that only the descriptor table requires 8-byte alignment for 64-bit DMA. That will be dealt with in a separate patch, but the potential for a 2-byte access remains, so this fix is needed anyway. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: sdhci-pci: Do not default to 33 Ohm driver strength for Intel SPTAdrian Hunter2016-03-031-1/+1
| | | | | | | | | | | | | | | | commit 1ca896856281d3f1ad4f6f7d4e32e2943452de23 upstream. In some cases, the stronger 33 Ohm driver strength must not be used so it is not a suitable default. Change it to the standard default 50 Ohm value. The patch applies to v4.2+ except the file name changed. It is drivers/mmc/host/sdhci-pci.c prior to v.4.4. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: usdhi6rol0: handle NULL data in timeoutRabin Vincent2016-03-031-1/+2
| | | | | | | | | | | | | | | | commit 05caee939f8d58d81e962071da85761e1e3a4c73 upstream. Commit bb08a7d489bd ("mmc: usdhi6rol0: fix NULL pointer deref in debug print") fixed one NULL pointer dereference but unfortunately introduced another. "data" may be NULL if this is a command timeout for a command without any data, so we should only use it if we're actually waiting for data. Fixes: bb08a7d489bd ("mmc: usdhi6rol0: fix NULL pointer deref in debug print") Signed-off-by: Rabin Vincent <rabin.vincent@axis.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* mmc: remove bondage between REQ_META and reliable writeLuca Porzio2015-11-091-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Anytime a write operation is performed with Reliable Write flag enabled, the eMMC device is enforced to bypass the cache and do a write to the underling NVM device by Jedec specification; this causes a performance penalty since write operations can't be optimized by the device cache. In our tests, we replayed a typical mobile daily trace pattern and found ~9% overall time reduction in trace replay by using this patch. Also the write ops within 4KB~64KB chunk size range get a 40~60% performance improvement by using the patch (as this range of write chunks are the ones affected by REQ_META). This patch has been discussed in the Mobile & Embedded Linux Storage Forum and it's the results of feedbacks from many people. We also checked with fsdevl and f2fs mailing list developers that this change in the usage of REQ_META is not affecting FS behavior and we got positive feedbacks. Reporting here the feedbacks: http://comments.gmane.org/gmane.linux.file-systems/97219 http://thread.gmane.org/gmane.linux.file-systems.f2fs/3178/focus=3183 Signed-off-by: Bruce Ford <bford@micron.com> Signed-off-by: Luca Porzio <lporzio@micron.com> Fixes: ce39f9d17c14 ("mmc: support packed write command for eMMC4.5 devices") Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: MMC_GOLDFISH should depend on HAS_DMAGeert Uytterhoeven2015-11-091-0/+1
| | | | | | | | | | | | | | If NO_DMA=y: ERROR: dma_unmap_sg [drivers/mmc/host/android-goldfish.ko] undefined! ERROR: dma_alloc_coherent [drivers/mmc/host/android-goldfish.ko] undefined! ERROR: dma_map_sg [drivers/mmc/host/android-goldfish.ko] undefined! ERROR: dma_free_coherent [drivers/mmc/host/android-goldfish.ko] undefined! Add a dependency on HAS_DMA to fix this. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mediatek: Preinitialize delay_phase in get_best_delay()Geert Uytterhoeven2015-11-091-1/+1
| | | | | | | | | | | | drivers/mmc/host/mtk-sd.c: In function ‘get_best_delay’: drivers/mmc/host/mtk-sd.c:1284: warning: ‘delay_phase.start’ is used uninitialized in this function drivers/mmc/host/mtk-sd.c:1284: warning: ‘delay_phase.maxlen’ is used uninitialized in this function If delay is zero, these fields are indeed not initialized. Let the compiler preinitialize the whole struct to fix this. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmc: Improve reliability of mmc_select_hs400()Adrian Hunter2015-11-091-2/+26
| | | | | | | | | | | | | | | | | | | | | | | mmc_select_hs400() calls __mmc_switch() which checks the switch is successful using CMD13 (SEND_STATUS). The problem is that it does that using the timing settings of the previous mode. That is prone to error, especially when switching from HS to HS400 because the timing parameters for HS mode are tighter than the timing parameters for HS400 mode. In the case when CMD13 polling is used (i.e. not MMC_CAP_WAIT_WHILE_BUSY) with the switch command, it must be assumed that using different modes on the card and host must work. However in the case when CMD13 polling is not used (i.e. MMC_CAP_WAIT_WHILE_BUSY) mmc_select_hs400() can be made more reliable by setting the host to the correct timing before sending CMD13. This patch does that. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: <stable@vger.kernel.org> # 4.2+ Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmc: Move mmc_switch_status()Adrian Hunter2015-11-091-13/+13
| | | | | | | | | | Move the mmc_switch_status() function in preparation for calling it in mmc_select_hs400(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: <stable@vger.kernel.org> # 4.2+ Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmc: Fix HS setting in mmc_select_hs400()Adrian Hunter2015-11-091-6/+8
| | | | | | | | | | | | | | | | | | | | | mmc_select_hs400() begins with the card and host in HS200 mode. Therefore, any commands sent to the card should use HS200 timing. It is incorrect to set the host to High Speed (HS) timing before sending the switch command. Doing so is unreliable because the timing parameters for HS mode are tighter than the timing parameters for HS200 mode. Thus the HS timings should be set only after the card has switched mode. However, it is not unreasonable first to reduce the frequency to the HS mode frequency, which should make the switch command and subsequent CMD13 commands more reliable. This patch does that. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: <stable@vger.kernel.org> # 4.2+ Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmc: Improve reliability of mmc_select_hs200()Adrian Hunter2015-11-091-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently mmc_select_hs200() uses __mmc_switch() which checks the success of the switch to HS200 mode using CMD13 (SEND_STATUS). The problem is that it does that using the timing settings of legacy mode. That is prone to error, not least because the timing parameters for legacy mode are tighter than the timing parameters for HS200 mode. In the case when CMD13 polling is used (i.e. not MMC_CAP_WAIT_WHILE_BUSY) with the switch command, it must be assumed that using different modes on the card and host must work. However in the case when CMD13 polling is not used (i.e. MMC_CAP_WAIT_WHILE_BUSY) mmc_select_hs200() can be made more reliable by setting the host to the correct timing before sending CMD13. This patch does that. A complication is that the caller, mmc_select_timing(), will ignore a switch error (indicated by -EBADMSG), assume the old mode is valid and continue, so the old timing must be restored in that case. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: <stable@vger.kernel.org> # 4.2+ Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: pxamci: fix read-only gpio detection polarityRobert Jarzmik2015-11-091-1/+1
| | | | | | | | | | The commit converting pxamci to slot-gpio API inverted the logic of the read-only gpio. Fix it by inverting the logic again. Fixes: fd546ee6a7dc ("mmc: pxamci: fix card detect with slot-gpio API") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* Merge tag 'spi-v4.4' of ↵Linus Torvalds2015-11-051-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "Quite a lot of activity in SPI this cycle, almost all of it in drivers with a few minor improvements and tweaks in the core. - Updates to pxa2xx to support Intel Broxton and multiple chip selects. - Support for big endian in the bcm63xx driver. - Multiple slave support for the mt8173 - New driver for the auxiliary SPI controller in bcm2835 SoCs. - Support for Layerscale SoCs in the Freescale DSPI driver" * tag 'spi-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (87 commits) spi: pxa2xx: Rework self-initiated platform data creation for non-ACPI spi: pxa2xx: Add support for Intel Broxton spi: pxa2xx: Detect number of enabled Intel LPSS SPI chip select signals spi: pxa2xx: Add output control for multiple Intel LPSS chip selects spi: pxa2xx: Use LPSS prefix for defines that are Intel LPSS specific spi: Add DSPI support for layerscape family spi: ti-qspi: improve ->remove() callback spi/spi-xilinx: Fix race condition on last word read spi: Drop owner assignment from spi_drivers spi: Add THIS_MODULE to spi_driver in SPI core spi: Setup the master controller driver before setting the chipselect spi: dw: replace magic constant by DW_SPI_DR spi: mediatek: mt8173 spi multiple devices support spi: mediatek: handle controller_data in mtk_spi_setup spi: mediatek: remove mtk_spi_config spi: mediatek: Update document devicetree bindings to support multiple devices spi: fix kernel-doc warnings about missing return desc in spi.c spi: fix kernel-doc warnings about missing return desc in spi.h spi: pxa2xx: Align a few defines spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select ...
| *-. Merge remote-tracking branches 'spi/topic/omap-100k', ↵Mark Brown2015-11-041-1/+0
| |\ \ | | | | | | | | | | | | 'spi/topic/omap-uwire', 'spi/topic/owner', 'spi/topic/pxa' and 'spi/topic/pxa2xx' into spi-next
| | | * spi: Drop owner assignment from spi_driversAndrew F. Davis2015-10-281-1/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | An spi_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | mmc: dw_mmc: fix the wrong setting for UHS-DDR50 modeJaehoon Chung2015-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When card is running with DDR mode, dwmmc needs to set DDR_REG bit at UHS_REG register. Before this patch, dwmmc controller doesn't consider this. If this patch is not applied, CRC or other error shoulds be occurred. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl registerJaehoon Chung2015-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to DesignWare DoC file, CardThreshold bit should be bit[27:16]. So it's correct to use (0xFFF << 16), not (0x1FFF << 16). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: NULL dereference in error messageDan Carpenter2015-10-291-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The "host->dms->ch" pointer is NULL here so we can't use it to print the error message. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: pwrseq: Use highest priority for eMMC restart handlerJavier Martinez Canillas2015-10-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pwrseq_emmc driver does a eMMC card reset before a system reboot to allow broken or limited ROM boot-loaders (that don't have an eMMC reset logic) to be able to read the second stage from the eMMC. But this has to be called before a system reboot handler and while most of them use the priority 128, there are other restart handlers (such as the syscon-reboot one) that use a higher priority. So, use the highest priority to make sure that the eMMC hw is reset before a system reboot. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: add HS400 supportChaotian Jing2015-10-271-5/+244
| | | | | | | | | | | | | | | | | | | | | add HS400 mode and tune support Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mmc: extend the mmc_send_tuning()Chaotian Jing2015-10-278-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mmc_execute_tuning() has already prepared the opcode, there is no need to prepare it again at mmc_send_tuning(), and, there is a BUG of mmc_send_tuning() to determine the opcode by bus width, assume eMMC was running at HS200, 4bit mode, then the mmc_send_tuning() will overwrite the opcode from CMD21 to CMD19, then got error. in addition, extend an argument of "cmd_error" to allow getting if there was cmd error when tune response. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> [Ulf: Rebased patch] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: add implement of ops->hw_reset()Chaotian Jing2015-10-271-0/+11
| | | | | | | | | | | | | | | | | | | | | add implement of ops->hw_reset() for eMMC Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: fix got GPD checksum error interrupt when data transferChaotian Jing2015-10-271-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Even if we only use one gpd, we need alloc 2 gpd and make the gpd->next pointer to the second gpd, or may get gpd checksum error, this was checked by hardware Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: change the argument "ddr" to "timing"Chaotian Jing2015-10-271-12/+8
| | | | | | | | | | | | | | | | | | | | | | | | use the ios->timing directly is better It can reflect current timing and do settings by timing Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mediatek: make cmd_ints_mask to constChaotian Jing2015-10-271-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | cmd_ints_mask and data_ints_mask are constant value, so make it to const Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: core: Add DT bindings for eMMC hardware reset supportChaotian Jing2015-10-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Sometime only need set MMC_CAP_HW_RESET for one of MMC hosts, So set it in device tree is better. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: omap_hsmmc: Enable omap_hsmmc for Keystone 2Lokesh Vutla2015-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable omap_hsmmc for Keystone 2 architecture which reuses the HSMMC IP found on OMAP platforms. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-acpi: Add more ACPI HIDs for Intel controllersAdrian Hunter2015-10-261-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add ACPI HIDs for Intel host controllers including one supporting HS400. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pci: Add more PCI IDs for Intel controllersAdrian Hunter2015-10-262-0/+54
| | | | | | | | | | | | | | | | | | | | | Add PCI IDs for Intel host controllers Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: use macro for HCON register operationsShawn Lin2015-10-262-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add some macros for HCON register operations to make code more readable. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: Add external dma interface supportShawn Lin2015-10-264-62/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DesignWare MMC Controller can supports two types of DMA mode: external dma and internal dma. We get a RK312x platform integrated dw_mmc and ARM pl330 dma controller. This patch add edmac ops to support these platforms. I've tested it on RK31xx platform with edmac mode and RK3288 platform with idmac mode. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-of-esdhc: avoid writing power control registeryangbo lu2015-10-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The eSDHC doesn't have a standard power control register, so when writing this register in stack we should do nothing to avoid incorrect operation. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: skip reclaiming host on mmc_add_card() errorSergei Shtylyov2015-10-262-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There's little sense in releasing the host on mmc_add_card() error immediately after reclaiming it, so reclaim the host only in case of success. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: android-goldfish: Allow compiling the driver with COMPILE_TESTLuis de Bethencourt2015-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver depends on GOLDFISH but there isn't a build dependency so it's a good idea to allow the driver to always be built when the COMPILE_TEST option is enabled. That way, the driver can be built with a config generated by make allyesconfig and check if a patch would break the build. Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc-rockchip: MMC tuning with the clock phase frameworkAlexandru M Stan2015-10-261-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This algorithm will try 1 degree increments, since there's no way to tell what resolution the underlying phase code uses. As an added bonus, doing many tunings yields better results since some tests are run more than once (ex: if the underlying driver uses 45 degree increments, the tuning code will try the same angle more than once). It will then construct a list of good phase ranges (even ranges that cross 360/0), will pick the biggest range then it will set the sample_clk to the middle of that range. We do not touch ciu_drive (and by extension define default-drive-phase). Drive phase is mostly used to define minimum hold times, while one could write some code to determine what phase meets the minimum hold time (ex 10 degrees) this will not work with the current clock phase framework (which floors angles, so we'll get 0 deg, and there's no way to know what resolution the floors happen at). We assume that the default drive angles set by the hardware are good enough. If a device has device specific code (like exynos) then that will still take precedence, otherwise this new code will execute. If the device wants to tune, but has no sample_clk defined we'll return EIO with an error message. Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: Use mmc_regulator_set_vqmmc in start_signal_voltage_switchDouglas Anderson2015-10-261-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've introduced a new helper in the MMC core: mmc_regulator_set_vqmmc(). Let's use this in dw_mmc. Using this new helper has some advantages: 1. We get the mmc_regulator_set_vqmmc() behavior of trying to match VQMMC and VMMC when the signal voltage is 3.3V. This ensures max compatibility. 2. We get rid of a few more warnings when probing unsupported voltages. 3. We get rid of some non-dw_mmc specific code in dw_mmc. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: core: Add mmc_regulator_set_vqmmc()Douglas Anderson2015-10-261-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds logic to the MMC core to set VQMMC. This is expected to be called by MMC drivers like dw_mmc as part of (or instead of) their start_signal_voltage_switch() callback. A few notes: * When setting the signal voltage to 3.3V we do our best to make VQMMC and VMMC match. It's been reported that this makes some old cards happy since they were tested back in the day before UHS when VQMMC and VMMC were provided by the same regulator. A nice side effect of this is that we don't end up on the hairy edge of VQMMC (2.7V), which some EEs claim is a little too close to the minimum for comfort. This is done in two steps. At first we try to find a VQMMC within a 0.3V tolerance of VMMC and if this is not supported by the supplying regulator we try to find a suitable voltage within the whole 2.7V-3.6V area of the spec. * The two step approach is currently necessary, as the used regulator_set_voltage_triplet(min, target, max) uses a simple implementation that just tries two basic steps: regulator_set_voltage(target, max); regulator_set_voltage(min, target); So with only one step with 2.7-3.6V borders, if a suitable voltage is a bit below VMMC, we would directly get the lowest 2.7V which some boards (like Rockchips) don't like at all. * When setting the signal voltage to 1.8V or 1.2V we aim for that specific voltage instead of picking the lowest one in the range. * We very purposely don't print errors in mmc_regulator_set_vqmmc(). There are cases where the MMC core will try several different voltages and we don't want to pollute the logs. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: core: move ocr-bit to voltage translation into separate functionHeiko Stuebner2015-10-261-16/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | We will shortly need the calculation of an ocr-bit to the actual voltage in a second place too, so move it from mmc_regulator_set_ocr to a common function mmc_ocrbitnum_to_vdd to make that possible. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: core: Remove MMC_CLKGATEUlf Hansson2015-10-2610-426/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMC_CLKGATE was once invented to save power by gating the bus clock at request inactivity. At that time it served its purpose. The modern way to deal with power saving for these scenarios, is by using runtime PM. Nowadays, several host drivers have deployed runtime PM, but for those that haven't and which still cares power saving at request inactivity, it's certainly time to deploy runtime PM as it has been around for several years now. To simplify code to mmc core and thus decrease maintenance efforts, this patch removes all code related to MMC_CLKGATE. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | | mmc: sdhci-of-esdhc: add quirk SDHCI_QUIRK_BROKEN_TIMEOUT_VAL for ls1021ayangbo lu2015-10-261-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: kconfig: reconfigure MMC_SDHCI_OF_ESDHC optionyangbo lu2015-10-261-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale eSDHC driver now supports both little-endian and big-endian mode eSDHC IPs for ARM and PPC. So, MMC_SDHCI_OF_ESDHC option needs to be reconfigured. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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