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| * | irqchip/mmp: Do not call irq_set_default_host() on DT platformsLubomir Rintel2019-08-201-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Using a default domain on DT platforms is unnecessary, as the firmware tables describe the full topology, and nothing is implicit. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> [maz: wrote an actual changelog] Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3-its: Remove the redundant set_bit for lpi_mapZenghui Yu2019-08-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We try to find a free LPI region in device's lpi_map and allocate them (set them to 1) when we want to allocate LPIs for this device. This is what bitmap_find_free_region() has done for us. The following set_bit is redundant and a bit confusing (since we only set_bit against the first allocated LPI idx). Remove it, and make the set_bit explicit by comment. Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803Marc Zyngier2019-08-201-10/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It looks like the HIP06/07 SoCs have extra bits in their GICD_TYPER registers, which confuse the GICv3.1 code (these systems appear to expose ESPIs while they actually don't). Detect these systems as early as possible and wipe the fields that should be RES0 in the register. Tested-by: John Garry <john.garry@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic: Skip DT quirks when evaluating IIDR-based quirksMarc Zyngier2019-08-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | When evaluating potential quirks matched by reads of the IIDR register, skip the quirk entries that use a "compatible" property attached to them, as these are DT based. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3: Warn about inconsistent implementations of extended rangesMarc Zyngier2019-08-201-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As is it usual for the GIC, it isn't disallowed to put together a system that is majorly inconsistent, with a distributor supporting the extended ranges while some of the CPUs don't. Kindly tell the user that things are sailing isn't going to be smooth. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3: Add EPPI range supportMarc Zyngier2019-08-201-7/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Expand the pre-existing PPI support to be able to deal with the Extended PPI range (EPPI). This includes obtaining the number of PPIs from each individual redistributor, and compute the minimum set (just in case someone builds something really clever...). Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3: Dynamically allocate PPI partition descriptorsMarc Zyngier2019-08-201-3/+11
| | | | | | | | | | | | | | | | | | | | | Again, PPIs are becoming a variable set. Let's hack the PPI partition code to make the top-level array dynamically allocated. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3: Dynamically allocate PPI NMI refcountsMarc Zyngier2019-08-201-13/+34
| | | | | | | | | | | | | | | | | | | | | | | | As we're about to have a variable number of PPIs, let's make the allocation of the NMI refcounts dynamic. Also apply some minor cleanups (moving things around). Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic: Prepare for more than 16 PPIsMarc Zyngier2019-08-205-17/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GICv3.1 allows up to 80 PPIs (16 legaci PPIs and 64 Extended PPIs), meaning we can't just leave the old 16 hardcoded everywhere. We also need to add the infrastructure to discover the number of PPIs on a per redistributor basis, although we still pretend there is only 16 of them for now. No functional change. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3: Add ESPI range supportMarc Zyngier2019-08-201-16/+69
| | | | | | | | | | | | | | | | | | | | | Add the required support for the ESPI range, which behave exactly like the SPIs of old, only with new funky INTIDs. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3: Add INTID range and convertion primitivesMarc Zyngier2019-08-201-29/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the beginning, life was simple. The GIC driver mostly cared about PPIs, SPIs and LPIs, all with nicely layed out ranges. We're about to change all that, with new ranges such as EPPI and ESPI interleaved in the middle of the no-irq-land between the "special IDs" and the LPI range. Boo. In order to make our life less hellish, let's introduce a set of primitives that will allow ranges to be identified easily and offsets to be remapped. So far, there is no functionnal change. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic: Rework gic_configure_irq to take the full ICFGR baseMarc Zyngier2019-08-204-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gic_configure_irq is currently passed the (re)distributor address, to which it applies an a fixed offset to get to the configuration registers. This offset is constant across all GICs, or rather it was until to v3.1... An easy way out is for the individual drivers to pass the base address of the configuration register for the considered interrupt. At the same time, move part of the error handling back to the individual drivers, as things are about to change on that front. Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/ixp4xx: Register the base PA instead of its VA in fwnodeMarc Zyngier2019-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Do not expose the base VA (it appears in debugfs). Instead, record the PA, which at least can be used to precisely identify the associated irqchip and domain. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v2m: Register the frame's PA instead of its VA in fwnodeMarc Zyngier2019-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Do not expose the frame's VA (it appears in debugfs). Instead, record the PA, which at least can be used to precisely identify the associated irqchip and domain. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic: Register the distributor's PA instead of its VA in fwnodeMarc Zyngier2019-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Do not expose the distributor's VA (it appears in debugfs). Instead, record the PA, which at least can be used to precisely identify the associated irqchip and domain. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3-its: Register the ITS' PA instead of its VA in fwnodeMarc Zyngier2019-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Do not expose the ITS' VA (it appears in debugfs). Instead, record the PA, which at least can be used to precisely identify the associated irqchip and domain. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * | irqchip/gic-v3: Register the distributor's PA instead of its VA in fwnodeMarc Zyngier2019-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Do not expose the distributor's VA (it appears in debugfs). Instead, record the PA, which at least can be used to precisely identify the associated irqchip and domain. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org>
* | | irqchip/sifive-plic: set max threshold for ignored handlersChristoph Hellwig2019-09-051-2/+10
|/ / | | | | | | | | | | | | | | When running in M-mode, the S-mode plic handlers are still listed in the device tree. Ignore them by setting the maximum threshold. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
* | Merge tag 'irqchip-fixes-5.3' of ↵Thomas Gleixner2019-08-014-3/+13
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent Pull irqchip fixes from Marc Zyngier: A small bunch of fixes from the irqchip department: - Fix a couple of UAF on error paths (RZA1, GICv3 ITS) - Fix iMX GPCv2 trigger setting - Add missing of_node_put on error path in MBIGEN - Add another bunch of /* fall-through */ to silence warnings
| * irqchip/renesas-rza1: Fix an use-after-free in rza1_irqc_probe()Wen Yang2019-07-261-7/+8
| | | | | | | | | | | | | | | | | | | | The gic_node is still being used in the rza1_irqc_parse_map() call after the of_node_put() call, which may result in use-after-free. Fixes: a644ccb819bc ("irqchip: Add Renesas RZ/A1 Interrupt Controller driver") Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * irqchip/irq-imx-gpcv2: Forward irq type to parentLucas Stach2019-07-261-0/+1
| | | | | | | | | | | | | | | | | | The GPCv2 is a stacked IRQ controller below the ARM GIC. It doesn't care about the IRQ type itself, but needs to forward the type to the parent IRQ controller, so this one can be configured correctly. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * irqchip/irq-mbigen: Add of_node_put() before returnNishka Dasgupta2019-07-261-2/+7
| | | | | | | | | | | | | | | | | | | | | | Each iteration of for_each_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Add an of_node_put before the return in three places. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * irqchip/gic-v3-its: Free unused vpt_page when alloc vpe table failNianyao Tang2019-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | In its_vpe_init, when its_alloc_vpe_table fails, we should free vpt_page allocated just before, instead of vpe->vpt_page. Let's fix it. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Nianyao Tang <tangnianyao@huawei.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
| * irqchip/gic-v3: Mark expected switch fall-throughAnders Roxell2019-07-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When fall-through warnings was enabled by default the following warning was starting to show up: In file included from ../arch/arm64/include/asm/cputype.h:132, from ../arch/arm64/include/asm/cache.h:8, from ../include/linux/cache.h:6, from ../include/linux/printk.h:9, from ../include/linux/kernel.h:15, from ../include/linux/list.h:9, from ../include/linux/kobject.h:19, from ../include/linux/of.h:17, from ../include/linux/irqdomain.h:35, from ../include/linux/acpi.h:13, from ../drivers/irqchip/irq-gic-v3.c:9: ../drivers/irqchip/irq-gic-v3.c: In function ‘gic_cpu_sys_reg_init’: ../arch/arm64/include/asm/sysreg.h:853:2: warning: this statement may fall through [-Wimplicit-fallthrough=] asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ ^~~ ../arch/arm64/include/asm/arch_gicv3.h:20:29: note: in expansion of macro ‘write_sysreg_s’ #define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r) ^~~~~~~~~~~~~~ ../drivers/irqchip/irq-gic-v3.c:773:4: note: in expansion of macro ‘write_gicreg’ write_gicreg(0, ICC_AP0R2_EL1); ^~~~~~~~~~~~ ../drivers/irqchip/irq-gic-v3.c:774:3: note: here case 6: ^~~~ Rework so that the compiler doesn't warn about fall-through. Fixes: d93512ef0f0e ("Makefile: Globally enable fall-through warning") Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
* | irqchip/gic-v3-its: Fix misuse of GENMASK macroJoe Perches2019-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | Arguments are supposed to be ordered high then low. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/ab5deb4fc3cd604cb620054770b7d00016d736bc.1562734889.git.joe@perches.com
* | irqchip/renesas-rza1: Prevent use-after-free in rza1_irqc_probe()Wen Yang2019-07-091-7/+8
| | | | | | | | | | | | | | | | | | | | | | The gic_node is still being used in the rza1_irqc_parse_map() call after the of_node_put() call, which may result in use-after-free. Fixes: a644ccb819bc ("irqchip: Add Renesas RZ/A1 Interrupt Controller driver") Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lkml.kernel.org/r/1562566745-7447-3-git-send-email-wen.yang99@zte.com.cn
* | Merge branch 'irq-core-for-linus' of ↵Linus Torvalds2019-07-0813-124/+890
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "The irq departement provides the usual mixed bag: Core: - Further improvements to the irq timings code which aims to predict the next interrupt for power state selection to achieve better latency/power balance - Add interrupt statistics to the core NMI handlers - The usual small fixes and cleanups Drivers: - Support for Renesas RZ/A1, Annapurna Labs FIC, Meson-G12A SoC and Amazon Gravition AMR/GIC interrupt controllers. - Rework of the Renesas INTC controller driver - ACPI support for Socionext SoCs - Enhancements to the CSKY interrupt controller - The usual small fixes and cleanups" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (39 commits) irq/irqdomain: Fix comment typo genirq: Update irq stats from NMI handlers irqchip/gic-pm: Remove PM_CLK dependency irqchip/al-fic: Introduce Amazon's Annapurna Labs Fabric Interrupt Controller Driver dt-bindings: interrupt-controller: Add Amazon's Annapurna Labs FIC softirq: Use __this_cpu_write() in takeover_tasklets() irqchip/mbigen: Stop printing kernel addresses irqchip/gic: Add dependency for ARM_GIC_MAX_NR genirq/affinity: Remove unused argument from [__]irq_build_affinity_masks() genirq/timings: Add selftest for next event computation genirq/timings: Add selftest for irqs circular buffer genirq/timings: Add selftest for circular array genirq/timings: Encapsulate storing function genirq/timings: Encapsulate timings push genirq/timings: Optimize the period detection speed genirq/timings: Fix timings buffer inspection genirq/timings: Fix next event index function irqchip/qcom: Use struct_size() in devm_kzalloc() irqchip/irq-csky-mpintc: Remove unnecessary loop in interrupt handler dt-bindings: interrupt-controller: Update csky mpintc ...
| * irqchip/gic-pm: Remove PM_CLK dependencySameer Pujar2019-07-031-1/+0
| | | | | | | | | | | | | | | | | | gic-pm driver does not use pm-clk interface now and hence the dependency is removed from Kconfig. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/al-fic: Introduce Amazon's Annapurna Labs Fabric Interrupt ↵Talel Shenhar2019-07-033-0/+287
| | | | | | | | | | | | | | | | | | | | | | Controller Driver The Amazon's Annapurna Labs Fabric Interrupt Controller has 32 inputs. A FIC (Fabric Interrupt Controller) may be cascaded into another FIC or directly to the main CPU Interrupt Controller (e.g. GIC). Signed-off-by: Talel Shenhar <talel@amazon.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/mbigen: Stop printing kernel addressesKefeng Wang2019-06-181-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit ad67b74d2469d9b8 ("printk: hash addresses printed with %p"), it will print "____ptrval____" instead of actual addresses when mbigen create domain fails, Hisilicon MBIGEN-V2 HISI0152:00: Failed to create mbi-gen@(____ptrval____) irqdomain Hisilicon MBIGEN-V2: probe of HISI0152:00 failed with error -12 dev_xxx() helper contains the device info, HISI0152:00, which stands for mbigen ACPI HID and its UID, we can identify the failing probed mbigen, so just remove the printing "mgn_chip->base", and also add missing "\n". Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Reviewed-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/gic: Add dependency for ARM_GIC_MAX_NRJiangfeng Xiao2019-06-171-0/+1
| | | | | | | | | | | | | | | | | | CONFIG_ARM_GIC_MAX_NR is enabled by default. It is redundant in x86 and IA-64 where is without GIC. Signed-off-by: Jiangfeng Xiao <xiaojiangfeng@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/qcom: Use struct_size() in devm_kzalloc()Gustavo A. R. Silva2019-06-111-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct foo { int stuff; struct boo entry[]; }; size = sizeof(struct foo) + count * sizeof(struct boo); instance = devm_kzalloc(dev, size, GFP_KERNEL); Instead of leaving these open-coded and prone to type mistakes, we can now use the new struct_size() helper: instance = devm_kzalloc(dev, struct_size(instance, entry, count), GFP_KERNEL); Notice that, in this case, variable alloc_sz is not necessary, hence it is removed. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/irq-csky-mpintc: Remove unnecessary loop in interrupt handlerGuo Ren2019-06-111-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | csky_mpintc_handler() ->handle_domain_irq() ->irq_exit() ->invoke_softirq() ->__do_softirq() ->local_irq_enable() If new interrupt coming, it'll get into interrupt trap before return to csky_mpintc_handler(). So there is no need loop in csky_mpintc_handler. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/irq-csky-mpintc: Add triger typeGuo Ren2019-06-111-1/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support 4 triger types: - IRQ_TYPE_LEVEL_HIGH - IRQ_TYPE_LEVEL_LOW - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING All of above could be set in DeviceTree file and it still compatible with the old DeviceTree format. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/renesas-irqc: Use proper irq_chip name and parentGeert Uytterhoeven2019-06-111-1/+2
| | | | | | | | | | | | | | | | The irq_chip .name field should contain the device's class (not instance) name, while .parent_device should point to the device itself. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/renesas-intc-irqpin: Use proper irq_chip name and parentGeert Uytterhoeven2019-06-111-1/+2
| | | | | | | | | | | | | | | | The irq_chip .name field should contain the device's class (not instance) name, while .parent_device should point to the device itself. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/meson-gpio: Add support for Meson-G12A SoCXingyu Chen2019-06-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of: - 223:100 undefined (no interrupt) - 99:97 3 pins on bank GPIOE - 96:77 20 pins on bank GPIOX - 76:61 16 pins on bank GPIOA - 60:53 8 pins on bank GPIOC - 52:37 16 pins on bank BOOT - 36:28 9 pins on bank GPIOH - 27:12 16 pins on bank GPIOZ - 11:0 12 pins in the AO domain Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip: Enable compile-testing for Renesas driversGeert Uytterhoeven2019-06-111-4/+16
| | | | | | | | | | | | | | | | | | | | Enable compile-testing for all Renesas interrupt controller drivers, except for RENESAS_H8300H_INTC. The latter relies on a function (ctrl_bclr()) that is not available on other architectures. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/gic-v2m: Add support for Amazon Graviton variant of GICv3+GICv2mZeev Zilberman2019-06-112-17/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Amazon Graviton custom variant of GICv2m, where the message is encoded using the MSI message address, as opposed to standard GICv2m, where the SPI number is encoded in the MSI message data. In addition, the Graviton flavor of GICv2m is used along GICv3 (and not GICv2). Co-developed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Zeev Zilberman <zeev@amazon.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/renesas-irqc: Convert to managed initializationsGeert Uytterhoeven2019-05-291-39/+15
| | | | | | | | | | | | | | | | | | | | | | | | Simplify error handling by converting the driver to use managed allocations and initializations. Note that platform_get_resource() and ioremap_nocache() are combined in devm_platform_ioremap_resource(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/renesas-irqc: Replace irqc_priv.pdev by irqc_priv.devGeert Uytterhoeven2019-05-291-4/+3
| | | | | | | | | | | | | | | | Nothing really uses irqc_priv.pdev, all users need irqc_priv.pdev->dev. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/renesas-irqc: Add helper variable dev = &pdev->devGeert Uytterhoeven2019-05-291-13/+13
| | | | | | | | | | | | | | | | | | The probe function uses "&pdev->dev" a lot, hence add a shorthand for that. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/renesas-irqc: Remove error messages on out-of-memory conditionsGeert Uytterhoeven2019-05-291-2/+0
| | | | | | | | | | | | | | | | | | | | There is no need to print error messages if kzalloc() or ioremap_nocache() fail, as the memory allocation core already takes care of that. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/renesas-irqc: Remove unneeded inclusion of <linux/spinlock.h>Geert Uytterhoeven2019-05-291-1/+0
| | | | | | | | | | | | | | | | | | The driver never used spinlocks, and thus does not need to include <linux/spinlock.h>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip: Add Renesas RZ/A1 Interrupt Controller driverGeert Uytterhoeven2019-05-293-0/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the Renesas RZ/A1 Interrupt Controller. This supports using up to 8 external interrupts on RZ/A1, with configurable sense select. NMI edge select is not yet supported. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/exiu: Implement ACPI supportArd Biesheuvel2019-05-281-8/+68
| | | | | | | | | | | | | | | | | | | | | | Expose the existing EXIU hierarchical irqchip domain code to permit the interrupt controller to be used as the irqchip component of a GPIO controller on ACPI systems, or as the target of ordinary interrupt resources. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * irqchip/exiu: Preparatory refactor for ACPI supportArd Biesheuvel2019-05-281-23/+43
| | | | | | | | | | | | | | | | | | In preparation of adding support for EXIU controller devices described via ACPI, split the DT init function in a DT specific and a generic part, where the latter will be reused for ACPI support later. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | Merge tag 'arm64-upstream' of ↵Linus Torvalds2019-07-081-0/+7
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: - arm64 support for syscall emulation via PTRACE_SYSEMU{,_SINGLESTEP} - Wire up VM_FLUSH_RESET_PERMS for arm64, allowing the core code to manage the permissions of executable vmalloc regions more strictly - Slight performance improvement by keeping softirqs enabled while touching the FPSIMD/SVE state (kernel_neon_begin/end) - Expose a couple of ARMv8.5 features to user (HWCAP): CondM (new XAFLAG and AXFLAG instructions for floating point comparison flags manipulation) and FRINT (rounding floating point numbers to integers) - Re-instate ARM64_PSEUDO_NMI support which was previously marked as BROKEN due to some bugs (now fixed) - Improve parking of stopped CPUs and implement an arm64-specific panic_smp_self_stop() to avoid warning on not being able to stop secondary CPUs during panic - perf: enable the ARM Statistical Profiling Extensions (SPE) on ACPI platforms - perf: DDR performance monitor support for iMX8QXP - cache_line_size() can now be set from DT or ACPI/PPTT if provided to cope with a system cache info not exposed via the CPUID registers - Avoid warning on hardware cache line size greater than ARCH_DMA_MINALIGN if the system is fully coherent - arm64 do_page_fault() and hugetlb cleanups - Refactor set_pte_at() to avoid redundant READ_ONCE(*ptep) - Ignore ACPI 5.1 FADTs reported as 5.0 (infer from the 'arm_boot_flags' introduced in 5.1) - CONFIG_RANDOMIZE_BASE now enabled in defconfig - Allow the selection of ARM64_MODULE_PLTS, currently only done via RANDOMIZE_BASE (and an erratum workaround), allowing modules to spill over into the vmalloc area - Make ZONE_DMA32 configurable * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (54 commits) perf: arm_spe: Enable ACPI/Platform automatic module loading arm_pmu: acpi: spe: Add initial MADT/SPE probing ACPI/PPTT: Add function to return ACPI 6.3 Identical tokens ACPI/PPTT: Modify node flag detection to find last IDENTICAL x86/entry: Simplify _TIF_SYSCALL_EMU handling arm64: rename dump_instr as dump_kernel_instr arm64/mm: Drop [PTE|PMD]_TYPE_FAULT arm64: Implement panic_smp_self_stop() arm64: Improve parking of stopped CPUs arm64: Expose FRINT capabilities to userspace arm64: Expose ARMv8.5 CondM capability to userspace arm64: defconfig: enable CONFIG_RANDOMIZE_BASE arm64: ARM64_MODULES_PLTS must depend on MODULES arm64: bpf: do not allocate executable memory arm64/kprobes: set VM_FLUSH_RESET_PERMS on kprobe instruction pages arm64/mm: wire up CONFIG_ARCH_HAS_SET_DIRECT_MAP arm64: module: create module allocations without exec permissions arm64: Allow user selection of ARM64_MODULE_PLTS acpi/arm64: ignore 5.1 FADTs that are reported as 5.0 arm64: Allow selecting Pseudo-NMI again ...
| * | arm64: Fix interrupt tracing in the presence of NMIsJulien Thierry2019-06-211-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the presence of any form of instrumentation, nmi_enter() should be done before calling any traceable code and any instrumentation code. Currently, nmi_enter() is done in handle_domain_nmi(), which is much too late as instrumentation code might get called before. Move the nmi_enter/exit() calls to the arch IRQ vector handler. On arm64, it is not possible to know if the IRQ vector handler was called because of an NMI before acknowledging the interrupt. However, It is possible to know whether normal interrupts could be taken in the interrupted context (i.e. if taking an NMI in that context could introduce a potential race condition). When interrupting a context with IRQs disabled, call nmi_enter() as soon as possible. In contexts with IRQs enabled, defer this to the interrupt controller, which is in a better position to know if an interrupt taken is an NMI. Fixes: bc3c03ccb464 ("arm64: Enable the support of pseudo-NMIs") Cc: <stable@vger.kernel.org> # 5.1.x- Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Julien Thierry <julien.thierry@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2019-06-294-17/+41
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Ingo Molnar: "Diverse irqchip driver fixes" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-v3-its: Fix command queue pointer comparison bug irqchip/mips-gic: Use the correct local interrupt map registers irqchip/ti-sci-inta: Fix kernel crash if irq_create_fwspec_mapping fail irqchip/irq-csky-mpintc: Support auto irq deliver to all cpus
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