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| * | iio: add SPDX identifier for various driversMatt Ranostay2018-02-181-12/+4
| | | | | | | | | | | | | | | | | | | | | Add GPLv2+ SPDX identifier and update email for author's drivers. Signed-off-by: Matt Ranostay <matt.ranostay@konsulko.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: change license descriptionMilan Stevanovic2018-01-301-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Using an SPDX tag. Remove a license notice to keep the whole purpose of using an SPDx id. Signed-off-by: Milan Stevanovic <milan.o.stevanovic@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: driver for ti adc081s/adc101s/adc121sMilan Stevanovic2018-01-301-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Linux device driver for TI single-channel CMOS 8/10/12-bit analog-to-digital converter with a high-speed serial interface. Signed-off-by: Milan Stevanovic <milan.o.stevanovic@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio/adc: depend on SYSFS instead of selecting itRandy Dunlap2018-01-301-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drivers should not 'select' a subsystem. Instead they should depend on it. If the subsystem is disabled, the user probably did that for a purpose and one driver shouldn't be changing that. This also makes all IIO drivers consistent w.r.t depending on SYSFS instead of selecting it. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Jonathan Cameron <jic23@kernel.org> Cc: linux-iio@vger.kernel.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: axp20x_adc: add support for AXP813 ADCQuentin Schulz2018-01-301-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The X-Powers AXP813 PMIC is really close to what is already done for AXP20X/AXP22X. There are two pairs of bits to set the rate (one for Voltage and Current measurements and one for TS/GPIO0 voltage measurements) instead of one. The register to set the ADC rates is different from the one for AXP20X/AXP22X. GPIO0 can be used as an ADC (measuring Volts) unlike for AXP22X. The scales to apply to the different inputs are unlike the ones from AXP20X and AXP22X. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: axp20x_adc: make it possible to probe from DTQuentin Schulz2018-01-301-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To prepare for a future patch that will add a DT node for the ADC, make axp20x_adc able to probe from DT and get the per-variant data from of_device_id.data since platform_device_id.driver_data won't be set when probing by DT. Leave the ability to probe via platform for driver compatibility with old DTs. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: axp20x_adc: put ADC rate setting in a per-variant functionQuentin Schulz2018-01-301-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | To prepare for a new comer that set a different register with different values, move rate setting in a function that is specific to each AXP variant. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: ep93xx: remove redundant return value check of platform_get_resource()Wei Yongjun2018-01-301-4/+0
| |/ | | | | | | | | | | | | | | | | Remove unneeded error handling on the result of a call to platform_get_resource() when the value is passed to devm_ioremap_resource(). Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* | Merge tag 'staging-4.16-rc1' of ↵Linus Torvalds2018-02-0113-297/+955
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging Pull staging/IIO updates from Greg KH: "Here is the big Staging and IIO driver patches for 4.16-rc1. There is the normal amount of new IIO drivers added, like all releases. The networking IPX and the ncpfs filesystem are moved into the staging tree, as they are on their way out of the kernel due to lack of use anymore. The visorbus subsystem finall has started moving out of the staging tree to the "real" part of the kernel, and the most and fsl-mc codebases are almost ready to move out, that will probably happen for 4.17-rc1 if all goes well. Other than that, there is a bunch of license header cleanups in the tree, along with the normal amount of coding style churn that we all know and love for this codebase. I also got frustrated at the Meltdown/Spectre mess and took it out on the dgnc tty driver, deleting huge chunks of it that were never even being used. Full details of everything is in the shortlog. All of these patches have been in linux-next for a while with no reported issues" * tag 'staging-4.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (627 commits) staging: rtlwifi: remove redundant initialization of 'cfg_cmd' staging: rtl8723bs: remove a couple of redundant initializations staging: comedi: reformat lines to 80 chars or less staging: lustre: separate a connection destroy from free struct kib_conn Staging: rtl8723bs: Use !x instead of NULL comparison Staging: rtl8723bs: Remove dead code Staging: rtl8723bs: Change names to conform to the kernel code staging: ccree: Fix missing blank line after declaration staging: rtl8188eu: remove redundant initialization of 'pwrcfgcmd' staging: rtlwifi: remove unused RTLHALMAC_ST and RTLPHYDM_ST staging: fbtft: remove unused FB_TFT_SSD1325 kconfig staging: comedi: dt2811: remove redundant initialization of 'ns' staging: wilc1000: fix alignments to match open parenthesis staging: wilc1000: removed unnecessary defined enums typedef staging: wilc1000: remove unnecessary use of parentheses staging: rtl8192u: remove redundant initialization of 'timeout' staging: sm750fb: fix CamelCase for dispSet var staging: lustre: lnet/selftest: fix compile error on UP build staging: rtl8723bs: hal_com_phycfg: Remove unneeded semicolons staging: rts5208: Fix "seg_no" calculation in reset_ms_card() ...
| * iio: adc: stm32: fix scan of multiple channels with DMAFabrice Gasnier2018-01-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, watermark is set to '1'. Watermark is used to fine tune cyclic dma buffer period. In case watermark is left untouched (e.g. 1) and several channels are being scanned, buffer period is wrongly set (e.g. to 1 sample). As a consequence, data is never pushed to upper layer. Fix buffer period size, by taking scan channels number into account. Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * Drivers:iio:adc:ti_am335x_adc remove comparison to boolVenkat Prashanth B U2018-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | This is the patch to the file ti_am335x_adc.c which fixes the following coccinelle warning: WARNING: Comparison to bool Signed-off-by: Venkat Prashanth B U <venkat.prashanth2498@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: ina2xx: Actually align the loop with the conversion ready flagStefan Brüns2018-01-081-19/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the registers are read out once per conversion interval. If the reading is delayed as the conversion has not yet finished, this extra time is treated as being part of the readout, although it should delay the start of the poll interval. This results in the interval starting slightly earlier in each iteration, until all time between reads is spent polling the status registers instead of sleeping. To fix this, the delay has to account for the state of the conversion ready flag. Whenever the conversion is already finished, schedule the next read on the regular interval, otherwise schedule it one interval after the flag bit has been set. Split the work function in two functions, one for the status poll and one for reading the values, to be able to note down the time when the flag bit is raised. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: ina2xx: Align timestamp with conversion ready flagStefan Brüns2018-01-081-2/+2
| | | | | | | | | | | | | | | | | | As the timestamp is no longer (ab-)used to measure the function run time, it can be taken at the correct time, i.e. when the conversion has finished. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: ina2xx: Use a monotonic clock for delay calculationStefan Brüns2018-01-081-14/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iio timestamp clock is user selectable and may be non-monotonic. Also, only part of the acquisition time is measured, thus the delay was longer than intended. Use a monotonic timestamp to track the time for the next poll iteration. The timestamp is advanced by the sampling interval each iteration. In case the conversion overrruns the register readout (i.e. fast sampling combined with a slow bus), one or multiple samples will be dropped. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: ina2xx: Make calibration register value fixedMaciej Purski2018-01-081-31/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calibration register is used for calculating current register in hardware according to datasheet: current = shunt_volt * calib_register / 2048 (ina 226) current = shunt_volt * calib_register / 4096 (ina 219) Fix calib_register value to 2048 for ina226 and 4096 for ina 219 in order to avoid truncation error and provide best precision allowed by shunt_voltage measurement. Make current scale value follow changes of shunt_resistor from sysfs as calib_register value is now fixed. Power_lsb value should also follow shunt_resistor changes as stated in datasheet: power_lsb = 25 * current_lsb (ina 226) power_lsb = 20 * current_lsb (ina 219) This is a part of the patchset: https://lkml.org/lkml/2017/11/22/394 Signed-off-by: Maciej Purski <m.purski@samsung.com> Reviewed-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * Drivers: iio:adc: fix brace coding style issue in at91_adc.cVenkat Prashanth B U2018-01-081-2/+2
| | | | | | | | | | | | | | | | | | This is a patch to the at91_adc.c file that fixes up a brace warning found by the checkpatch.pl tool Signed-off-by: Venkat Prashanth B U <venkat.prashanth2498@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: hx711: fix bug in reset functionalityAndreas Klinger2018-01-081-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Return value in hx711_reset() should indicate status of dout otherwise the calling function is reporting an error as false positive If there are two reads too close to each other, then the second one will never succeed. This happens especially when using buffered mode with both channels enabled. When changing the channel on every trigger event the former 100 ms are not enough for waiting until the device indicates normal mode. Wait up to 1 second until the device turns into normal mode. Signed-off-by: Andreas Klinger <ak@it-klinger.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: hx711: add triggered buffer supportAndreas Klinger2018-01-082-23/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add buffer to device data struct and add trigger function Data format is quite simple: voltage - channel 0 32 Bit voltage - channel 1 32 Bit timestamp 64 Bit Using both channels at the same time is working quite slow because of changing the channel which needs a dummy read. Signed-off-by: Andreas Klinger <ak@it-klinger.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: ina2xx: Do not udelay for several secondsStefan Brüns2018-01-081-3/+5
| | | | | | | | | | | | | | | | | | The conversion time can be up to 16 seconds (8 ms per channel, 2 channels, 1024 times averaging). Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: ina2xx: Remove unneeded dummy read to clear CNVR flagStefan Brüns2018-01-081-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Although the datasheet states the CNVR flag is cleared by reading the BUS_VOLTAGE register, it is actually cleared by reading any of the voltage/current/power registers. The behaviour has been confirmed by TI support: http://e2e.ti.com/support/amplifiers/current-shunt-monitors/f/931/p/647053/2378282 Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: ina2xx: Clarify size requirement for data bufferStefan Brüns2018-01-081-1/+2
| | | | | | | | | | | | | | | | | | | | The timestamp is inserted into the buffer after the sample data by iio_push_to_buffers_with_timestamp, document the space requirement for the timestamp. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: ina2xx: Remove bogus cast for data argumentStefan Brüns2018-01-081-2/+1
| | | | | | | | | | | | | | | | | | iio_push_to_buffers_with_timestamp expects a void pointer, so the cast is both unnecessary and misleading. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: meson-saradc: program the channel muxes during initializationMartin Blumenstingl2018-01-081-3/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some Meson8 devices the channel muxes are not programmed. This results in garbage values when trying to read channels that are not set up. Fix this by initializing the channel 0 and 1 muxes in MESON_SAR_ADC_CHAN_10_SW as well as the muxes for all other channels in MESON_SAR_ADC_AUX_SW based on what the vendor driver does (which is simply a 1:1 mapping of channel number and channel mux). This only showed up on Meson8 devices, because for GXBB and newer BL30 is taking care of initializing the channel muxes. This additionally fixes a typo in the MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK macro because the old definition assumed that the register fields were 2 bit wide, while they are actually 3 bit wide. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: adc: meson-saradc: fix the clock frequency on Meson8 and Meson8bMartin Blumenstingl2018-01-081-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GX SoCs use a 1.2 MHz ADC clock, while the older SoCs use a 1.14 MHz clock. A comment in the driver from Amlogic's GPL kernel says that it's running at 1.28 MHz. However, it's actually programming a divider of 20 + 1. With a XTAL clock of 24 MHz this results in a frequency of 1.14 MHz. (their calculation might be based on a 27 MHz XTAL clock, but this is not what we have on the Meson8 and Meson8b SoCs). The ADC was still working with the 1.2MHz clock. In my own tests I did not see a difference between 1.2 and 1.14 MHz (regardless of the clock frequency used, the ADC results were identical). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * iio: stm32: Adopt SPDX identifierBenjamin Gaignard2018-01-083-40/+3
| | | | | | | | | | | | | | | | | | | | Add SPDX identifier in stm32's files in IIO directory Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Philippe Ombredanne <pombredanne@nexb.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * Merge Linus's staging merge point into staging-nextGreg Kroah-Hartman2017-12-062-11/+43
| |\ | | | | | | | | | | | | | | | | | | | | | This resolves the merge issue pointed out by Stephen in drivers/iio/adc/meson_saradc.c. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | iio: Add macro to populate struct iio_map arrayLukas Wunner2017-12-021-14/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO core provides a handy GPIO_LOOKUP() macro to populate a struct gpiod_lookup array without having to spell out attribute names (but still avoid breakage when attributes within the struct are rearranged or added). The axp288_adc.c driver uses a similar macro to populate a struct iio_map array. Make it available to others. Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Lukas Wunner <lukas@wunner.de> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: meson-saradc: remove irrelevant clock "sana"Xingyu Chen2017-12-021-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "sana" clock is not used at SAR ADC module in Amlogic Meson SoC, it is irrelevant for the SAR ADC. Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: aspeed: Deassert reset in probeJoel Stanley2017-12-021-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ASPEED SoC must deassert a reset in order to use the ADC peripheral. The device tree bindings are updated to document the resets phandle, and the example is updated to match what is expected for both the reset and clock phandle. Note that the bindings should have always had the reset controller, as the hardware is unusable without it. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: stm32: add support for differential channelsFabrice Gasnier2017-12-021-20/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32H7 ADC channels can be configured either as single ended or differential with 'st,adc-channels' or 'st,adc-diff-channels' (positive and negative input pair: <vinp vinn>, ...). Differential channels have different offset and scale, from spec: raw value = (full_scale / 2) * (1 + (vinp - vinn) / vref). Add offset attribute. Differential channels are selected by DIFSEL register. Negative inputs must be added to pre-selected channels as well (PCSEL). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: stm32: remove const channel names definitionFabrice Gasnier2017-12-021-52/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove const array that defines channels. Build channels definition at probe time, when initializing channels (only for requested ones). This will ease adding differential channels support. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: ina2xx: Allow setting Shunt Voltage PGA gain and Bus Voltage rangeStefan Brüns2017-12-021-3/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reducing shunt and bus voltage range improves the accuracy, so allow altering the default settings. Both settings are exposed as gain values. While for the shunt voltage this is straightforward, the bus range settings of 32V (default) and 16V are mapped to gain values of 1 resp. 2, to provide a uniform API to userspace. As the gain settings are incorporated into the raw values by the sensor itself, adjusting of the scale attributes is not necessary. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: ina2xx: Use LSB specifier instead of divider in configStefan Brüns2017-12-021-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the config uses the physical value corresponding to the LSB for both the power and the bus voltage register, the shunt voltage is specified as parts of 1 mV. Use the LSB physical value for all registers. No functional change. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: ina2xx: Shift bus voltage register to mask flag bitsStefan Brüns2017-12-021-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lower bits of the INA219/220 bus voltage register are conversion status flags, properly shift the value. When reading via IIO buffer, the value is passed on unaltered, shifting is the responsibility of the user. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: at91-sama5d2_adc: ack DRDY irq in direct modeEugen Hristev2017-12-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Need to acknowledge DRDY irq in direct mode/ software triggered mode. Otherwise, on the next conversion, overrun flag will be raised, which is not a correct state. This doesn't affect the functionality, but will generate possible incorrect overrun reports. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc: at91-sama5d2_adc: add support for DMAEugen Hristev2017-12-022-20/+434
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support for DMA transfers. The implementation uses the user watermark to decide whether DMA will be used or not. For watermark 1, DMA will not be used. If watermark is bigger, DMA will be used. Sysfs attributes are created to indicate whether the DMA is used, with hwfifo_enabled, and the current DMA watermark is readable in hwfifo_watermark. Minimum and maximum values are in hwfifo_watermark_min and hwfifo_watermark_max. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
| * | iio: adc/accel: Fix up module licensesLinus Walleij2017-12-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The module license checker complains about these two so just fix it up. They are both GPLv2, both written by me or using code I extracted while refactoring from the GPLv2 drivers. Cc: Randy Dunlap <rdunlap@infradead.org> Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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*-. \ \ Merge remote-tracking branches 'asoc/topic/hisilicon', 'asoc/topic/iio', ↵Mark Brown2018-01-186-0/+1925
|\ \ \ \ | | |/ / | |/| / | |_|/ |/| | 'asoc/topic/max98373' and 'asoc/topic/max98926' into asoc-next
| | * IIO: ADC: stm32-dfsdm: fix static check warningArnaud Pouliquen2018-01-151-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | iio_priv does not return an error pointer, so check is not valid. Patch suppresses it. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * IIO: ADC: stm32-dfsdm: code optimizationArnaud Pouliquen2018-01-152-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use of_device_get_match_data to optimize the source code. No check is needed on dev_data as match table is defined in driver. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * IIO: ADC: fix return value check in stm32_dfsdm_adc_probe()Wei Yongjun2018-01-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_iio_device_alloc() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: e2e6771c6462 ("IIO: ADC: add STM32 DFSDM sigma delta ADC support") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * IIO: ADC: stm32-dfsdm: avoid unused-variable warningArnd Bergmann2018-01-111-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building with CONFIG_OF disabled produces a compiler warning: drivers/iio/adc/stm32-dfsdm-core.c: In function 'stm32_dfsdm_probe': drivers/iio/adc/stm32-dfsdm-core.c:245:22: error: unused variable 'pnode' [-Werror=unused-variable] This removes the variable and open-codes it in the only place it gets used to avoid that warning. Fixes: bed73904e76f ("IIO: ADC: add stm32 DFSDM core support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * IIO: ADC: stm32_dfsdm_stop_filter() can be statickbuild test robot2018-01-101-4/+4
| | | | | | | | | | | | | | | | | | | | | Fixes: e2e6771c6462 ("IIO: ADC: add STM32 DFSDM sigma delta ADC support") Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Acked-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * IIO: ADC: add stm32 DFSDM support for PDM microphoneArnaud Pouliquen2018-01-101-7/+495
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code offers a way to handle PDM audio microphones in ASOC framework. Audio driver should use consumer API. A specific management is implemented for DMA, with a callback, to allows to handle audio buffers efficiently. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * IIO: ADC: add STM32 DFSDM sigma delta ADC supportArnaud Pouliquen2018-01-103-0/+742
| | | | | | | | | | | | | | | | | | | | | | | | Add DFSDM driver to handle sigma delta ADC. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * IIO: ADC: add stm32 DFSDM core supportArnaud Pouliquen2018-01-104-0/+632
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for stm32 DFSDM pheripheral. Its converts a sigma delta stream in n bit samples through a low pass filter and an integrator. stm32-dfsdm-core driver is the core part supporting the filter instances dedicated to sigma-delta ADC or audio PDM microphone purpose. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * IIO: ADC: add sigma delta modulator supportArnaud Pouliquen2018-01-103-0/+81
| |/ | | | | | | | | | | | | | | | | | | | | Add generic driver to support sigma delta modulators. Typically, this device is hardware connected to an IIO device in charge of the conversion. Devices are bonded through the hardware consumer API. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | iio: adc: meson-saradc: Meson8 and Meson8b do not have REG11 and REG13Martin Blumenstingl2017-12-021-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | The Meson GXBB and newer SoCs have a few more registers than the older Meson8 and Meson8b SoCs. Use a separate regmap config to limit the older SoCs to the DELTA_10 register. Fixes: 6c76ed31cd05 ("iio: adc: meson-saradc: add Meson8b SoC compatibility") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* | iio: adc: meson-saradc: initialize the bandgap correctly on older SoCsMartin Blumenstingl2017-12-021-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Meson8 and Meson8b do not have the MESON_SAR_ADC_REG11 register. The bandgap setting for these SoCs is configured in the MESON_SAR_ADC_DELTA_10 register instead. Make the driver aware of this difference and use the correct bandgap register depending on the SoC. This has worked fine on Meson8 and Meson8b because the bootloader is already initializing the bandgap setting. Fixes: 6c76ed31cd05 ("iio: adc: meson-saradc: add Meson8b SoC compatibility") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
* | iio: adc: meson-saradc: fix the bit_idx of the adc_en clockMartin Blumenstingl2017-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Meson8 and Meson8b SoCs use the the SAR ADC gate clock provided by the MESON_SAR_ADC_REG3 register within the SAR ADC register area. According to the datasheet (and the existing MESON_SAR_ADC_REG3_CLK_EN definition) the gate is on bit 30. The fls() function returns the last set bit, which is "bit index + 1" (fls(MESON_SAR_ADC_REG3_CLK_EN) returns 31). Fix this by switching to __ffs() which returns the first set bit, which is bit 30 in our case. This off by one error results in the ADC not being usable on devices where the bootloader did not enable the clock. Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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