| Commit message (Collapse) | Author | Age | Files | Lines |
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Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro definition as separate patch
as per Maarten's suggestion.
v3: Removed a redundant 3rd Pipe register definition and
simplified the equally spaced register definition by adding an
offset as per Matt's comment.
v4: No Change
v5: Renamed the register Macro as per Matt's suggestion.
v6: No Change
v7: No Change
v8: No Change
v9: No Change
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1541099420-12419-2-git-send-email-uma.shankar@intel.com
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We're no longer programming any watermarks when we're disabling
a pipe. That means ilk_wm_merge() & co. will keep considering
the any pipe that is getting disabled as still enabled. Thus we
either get no LP1+ watermakrs (ilk-ivb), or we get suboptimal
ones (hsw-bdw).
This seems to have been broken by commit b6b178a77210 ("drm/i915:
Calculate ironlake intermediate watermarks correctly, v2."). Before
that we apparently had some difference between the intermediate
and optimal watermarks and so we would program the optiomal ones.
Now intermediate and optimal are identical for disabled pipes
and so we don't program either.
Fix this by programming the intermediate watermarks even for
disabled pipes. We were already doing that for skl+. We'll
leave out gmch platforms for now since those do the merging
in a different manner and should work as is. We'll want to
unify this eventually, but play it safe for now and just put
in a FIXME.
Cc: stable@vger.kernel.org
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Fixes: b6b178a77210 ("drm/i915: Calculate ironlake intermediate watermarks correctly, v2.")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181025130536.29024-1-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
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On GEN9 LP (BXT/GLK) DC6 is not supported, so don't print the counter
on those platforms. So far we did this on GLK too.
While at it warn if we forgot to adjust the printout properly for a
new platform. (Rodrigo)
Testcase: igt/pm_dc/dc6-dpms
Cc: Jyoti Yadav <jyoti.r.yadav@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031200220.11608-1-imre.deak@intel.com
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The MG DP mode needs to be configured for Type C static/fixed/legacy
HDMI ports too, the same way as it's configured for Type C
static/fixed/legacy, fix this.
Bspec: 4232, 21735
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Tested-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181102192656.4472-3-imre.deak@intel.com
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The MG PHY clock gating needs to be configured for Type C
static/fixed/legacy HDMI ports the same way it's configured for Type C
static/fixed/legacy and aternate mode DP ports, fix this.
Bspec: 4232, 21735
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Tested-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181102192656.4472-2-imre.deak@intel.com
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Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
v3: Print FEC CAPABILITY value. (Manasi)
Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181102041455.15818-1-anusha.srivatsa@intel.com
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Since the flags are being used to operate on a u64 variable, they too
need to be marked as such so that the inverses are full width (and not
zero extended on 32b kernels and bdw+).
Reported-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181102161232.17742-2-chris@chris-wilson.co.uk
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The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)
v3:
- Remove register offset defines. (Jani)
- Update comment. (Anusha)
v4: rebase. Remove comment.(Lucas)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101185557.29585-1-anusha.srivatsa@intel.com
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Use the newly added "max bpc" connector property to limit pipe bpp.
V3: Use drm_connector_state to access the "max bpc" property
V4: Initialize the drm property, add suuport to DP(Ville)
V5: Use the property in the connector and fix CI failure(Ville)
V6: Use the core function to attach max_bpc property, remove the redundant
clamping of pipe bpp based on connector info
V7: Fix Checkpatch warnings
V9: Cleanup connected_sink_max_bpp and fix initial value in DP(Ville)
V12: Fix debug message(Ville)
V13: Remove the redundant check and simplify the check logic(Stan)
V14: Fix the check in connected_sink_max_bpp(Stan)
v15 (From Manasi): Add missing break (Stan)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Kishore Kadiyala <kishore.kadiyala@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181023014400.16055-1-manasi.d.navare@intel.com
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At times 12bpc HDMI cannot be driven due to faulty cables, dongles
level shifters etc. To workaround them we may need to drive the output
at a lower bpc. Currently the user space does not have a way to limit
the bpc. The default bpc to be programmed is decided by the driver and
is run against connector limitations.
Creating a new connector property "max bpc" in order to limit the bpc.
xrandr can make use of this connector property to make sure that bpc does
not exceed the configured value. This property can be used by userspace to
set the bpc.
V2: Initialize max_bpc to satisfy kms_properties
V3: Move the property to drm_connector
V4: Split drm and i915 components(Ville)
V5: Make the property per connector(Ville)
V6: Compare the requested bpc to connector bpc(Daniel)
Move the attach_property function to core(Ville)
V7: Fix checkpatch warnings
V8: Simplify the connector check code(Ville)
V9: Const display_info(Ville)
V10,V11: Fix CI issues.
V12: Add the Kernel documentation(Daniel)
V14: Crossreference the function name in the doc(Daniel)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Kishore Kadiyala <kishore.kadiyala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Sunpeng Li <sunpeng.li@amd.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181012184233.29250-1-radhakrishna.sripada@intel.com
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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Keep the register choosing macros together. No functional changes.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031110453.12722-4-jani.nikula@intel.com
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Try to make it slightly less of an eye sore. No functional changes.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031110453.12722-3-jani.nikula@intel.com
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Minor semantic nit, no functional changes.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031110453.12722-2-jani.nikula@intel.com
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The device info offset arrays for unevenly spaced register offsets is
great for widely used registers. However, the palette registers are only
used in one function, i9xx_load_luts_internal(), and only for GMCH
platforms, wasting device info. Replace palette_offsets with _PICK() in
palette register definition.
While the use of _PICK() does not check for pipe C existence, neither
does the current offset array usage, and leads to bogus address when
pipe C is passed to PALETTE() on non-CHV. Using _PICK() at least leads
to a sensible register offset, just non-existing on non-CHV. Either way,
this shouldn't happen anyway.
Remove unused old palette macros while at it.
Bloat-o-meter results below for completeness.
add/remove: 0/0 grow/shrink: 3/6 up/down: 94/-278 (-184)
Function old new delta
i9xx_load_luts_internal 394 483 +89
i915_driver_load 5103 5107 +4
g4x_pre_enable_dp 378 379 +1
intel_engines_init_mmio 1117 1116 -1
intel_engine_lookup_user 47 46 -1
hdmi_port_clock_valid 310 309 -1
gen11_irq_handler 707 706 -1
intel_device_info_dump_runtime 329 311 -18
intel_device_info_runtime_init 5166 4910 -256
Total: Before=918650, After=918466, chg -0.02%
add/remove: 0/0 grow/shrink: 0/48 up/down: 0/-576 (-576)
Data old new delta
intel_valleyview_info 200 188 -12
intel_skylake_gt4_info 200 188 -12
intel_skylake_gt3_info 200 188 -12
intel_skylake_gt2_info 200 188 -12
intel_skylake_gt1_info 200 188 -12
intel_sandybridge_m_gt2_info 200 188 -12
intel_sandybridge_m_gt1_info 200 188 -12
intel_sandybridge_d_gt2_info 200 188 -12
intel_sandybridge_d_gt1_info 200 188 -12
intel_pineview_info 200 188 -12
intel_kabylake_gt3_info 200 188 -12
intel_kabylake_gt2_info 200 188 -12
intel_kabylake_gt1_info 200 188 -12
intel_ivybridge_q_info 200 188 -12
intel_ivybridge_m_gt2_info 200 188 -12
intel_ivybridge_m_gt1_info 200 188 -12
intel_ivybridge_d_gt2_info 200 188 -12
intel_ivybridge_d_gt1_info 200 188 -12
intel_ironlake_m_info 200 188 -12
intel_ironlake_d_info 200 188 -12
intel_icelake_11_info 200 188 -12
intel_i965gm_info 200 188 -12
intel_i965g_info 200 188 -12
intel_i945gm_info 200 188 -12
intel_i945g_info 200 188 -12
intel_i915gm_info 200 188 -12
intel_i915g_info 200 188 -12
intel_i865g_info 200 188 -12
intel_i85x_info 200 188 -12
intel_i845g_info 200 188 -12
intel_i830_info 200 188 -12
intel_haswell_gt3_info 200 188 -12
intel_haswell_gt2_info 200 188 -12
intel_haswell_gt1_info 200 188 -12
intel_gm45_info 200 188 -12
intel_geminilake_info 200 188 -12
intel_g45_info 200 188 -12
intel_g33_info 200 188 -12
intel_coffeelake_gt3_info 200 188 -12
intel_coffeelake_gt2_info 200 188 -12
intel_coffeelake_gt1_info 200 188 -12
intel_cherryview_info 200 188 -12
intel_cannonlake_info 200 188 -12
intel_broxton_info 200 188 -12
intel_broadwell_rsvd_info 200 188 -12
intel_broadwell_gt3_info 200 188 -12
intel_broadwell_gt2_info 200 188 -12
intel_broadwell_gt1_info 200 188 -12
Total: Before=195529, After=194953, chg -0.29%
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031110453.12722-1-jani.nikula@intel.com
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Although there's nothing crucial missing, it's been a long time since
the last backmerge. Catch up with drm-next.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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This patch fixes the naming of the registers:
s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
And also fix the hex values to lower case, to match
rest of the definitions.
Manasi noticed this with the patch that was merged.
v2: fix "Fixes" tag.
Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers")
Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101214216.8958-1-anusha.srivatsa@intel.com
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BIOS can leave the PLL to port mapping enabled, even if the
corresponding encoder is disabled. Disable the port mapping in this
case.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-9-imre.deak@intel.com
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Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
parameters. As opposed to this the flag specifying the thunderbolt vs.
non-thunderbolt mode of the port is not related to AUX transfers at all
(rather it's repurposed to enable either TBT or non-TBT PHY HW blocks).
The programming has to be done before enabling the corresponding AUX
power well, so make it part of the power well code.
v3:
- Use existing enable/disable helpers instead of opencoding. (Jose)
- Fix type of is_tc_tbt to remain a bitfield. (Lucas)
- Add comment describing the is_tc_tbt power well flag. (Lucas)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108548
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-8-imre.deak@intel.com
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DDI/TypeC ports need the AUX power domain for main link functionality
even when they operate in HDMI static mode, so enable the power domain
for these ports too.
v4:
- Rebase on the upstream ICL pre_pll_enable change.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-7-imre.deak@intel.com
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For DDI/TypeC ports the AUX power domain needs to be enabled before the
port's PLL is enabled, so move the enabling earlier accordingly.
v2:
- Preserve the pre_pll hook for GEN9_LP. (Ville)
v3:
- Add related BSpec entries to commit log. (Jose)
v4:
- Rebase on the upstream ICL pre_pll_enable change.
BSpec: 21750, 22243
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-6-imre.deak@intel.com
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From ICL onwards the AUX power domain may change dynamically based on
whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode, so
use a helper function instead of a static field to get the current
domain.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-5-imre.deak@intel.com
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From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to know
which AUX CH belongs to them, so initialize aux_ch for those ports too.
For consistency do this for all HDMI ports, not only for DDI/TypeC ones.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-4-imre.deak@intel.com
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From ICL onwards all DDI/TypeC ports - even working in HDMI mode - need
to know their corresponding AUX CH, so move the field to a common
struct.
No functional change.
v3:
- Add code comment about which ports aux_ch is used for. (Jose)
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-3-imre.deak@intel.com
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From ICL onwards all the DDI/TypeC ports - even working in HDMI mode -
need to know their corresponding AUX channel, so move the corresponding
helper to a common place.
No functional change.
v4:
- Fix 'no space is necessary after a cast' checkpatch warn.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-2-imre.deak@intel.com
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Required for Bindless samplers.
Userspace consumer: mesa
V2: Rebase
V3: Update commit message
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030084504.21537-4-radhakrishna.sripada@intel.com
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Required to dinamically set 'Trilinear Filter Quality Mode'
Userpsace consumer is mesa.
V2: Rebase
V3: Update commit message
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030084504.21537-3-radhakrishna.sripada@intel.com
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Display WA_1405510057 asks to not enable YUV 420 HDMI
10bpc when horizontal blank size mod 8 reminder is 2.
V2: Rebase(r-b: Anusha)
V3: crtc_state->s/ycbcr420/output_format/
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030084504.21537-2-radhakrishna.sripada@intel.com
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Gen11 Display suports 32 planes in total. Enable the new format in context
status to be used and expanded to 32 planes.
V2: Move the WA to display WA's(Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030084504.21537-1-radhakrishna.sripada@intel.com
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CNL A stepping was the only affected there.
But also it is time to clean old pre-production
CNL Workarounds, so let's just remove and clean
this W/A.
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031162845.12419-4-rodrigo.vivi@intel.com
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Let's introduce the WA number that is the
cause of having NV12 disabled on both SLK and BXT.
According to Spec:
WA 0870: "Display flickers with NV12 video playback in
Y tiling mode.
WA: Use YUV422 surface format instead of NV12."
v2: remove the useless dead code and consequently
avoiding device info flag. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031162845.12419-3-rodrigo.vivi@intel.com
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According to BSpec this is not needed anymore:
"This workaround is no longer needed since NV12
support is dropped for the affected projects.
"
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031162845.12419-2-rodrigo.vivi@intel.com
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First of all I believe this WA as written here was wrong.
Because it is listed on BSpec only for SKL and BXT, exactly
the only 2 platforms skipped here.
But also it is written there that we don't need this WA
anymore:
"This workaround is no longer needed since NV12 support is
dropped for the affected projects in #0870."
SO, let's kill it.
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Vidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031162845.12419-1-rodrigo.vivi@intel.com
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Add missing block that takes care of inline intel_suspend_complete
for DC9 on ICL.
Daniele noticed this was part of original patch but missed on
on merged commit ("drm/i915/icl: Enable DC9 as lowest possible
state during screen-off").
Fixes: 3e68928b7d4c ("drm/i915/icl: Enable DC9 as lowest possible state during screen-off")
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[Rodrigo added a commit message while merging]
Link: https://patchwork.freedesktop.org/patch/msgid/20181031202726.4021-1-anusha.srivatsa@intel.com
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Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding
compression enabled on left or right branch.
v2:
- rebase. Remove overlapping defines(James Ausmus)
- Rename the register to ICL_DSS_CTL1/2_PIPE_ (manasi)
- take pixels as an argument for overlap.(Manasi)
v3:
- rebase. merge DSS_CTL1/2 introduced in Madhav's patch
to avoid confusion (madhav chauhan)
- Rename registers in accordance to BSpec (Madhav, Rodrigo)
- Add define to conditionally check the buffer target depth (James Ausmus)
v4:
- remove redundant definitions.(madhav)
v5:
- Add mask for overlap pixels.
- Code Style changes.(Madhav)
v6:
- Code style changes. (Madhav)
Suggested-by: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Gaurav Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/07021336cb87d09e8f97fbff709c4e686d7de536.1540900289.git.jani.nikula@intel.com
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For Gen11 DSI, we don't need to wait for getting
DSI FIFO empty after sending DCS commands.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/5e078a0274c1fba2521cb14d7d02fd1038ec1b0e.1540900289.git.jani.nikula@intel.com
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This patch detects DSI presence for ICL platform
by reading VBT. DSI detection is done while initializing
DSI using newly added function intel_gen11_dsi_init.
v2 by Jani:
- Preserve old behavour of intel_bios_is_dsi_present()
- s/intel_gen11_dsi_init/icl_dsi_init/g
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2324cdfc8918bda3165354e5e0d15053b1074f14.1540900289.git.jani.nikula@intel.com
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This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.
v2 by Jani:
- Drop full register mask and shift for payload
- Use lower case for hex 0x
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/18275c49215e512347a14bc38715314c2d6f95a4.1540900289.git.jani.nikula@intel.com
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In case of Legacy DP connector on TypeC port, the
flex IO DPMLE register is set to number of lanes configured
by the display driver which will be programmed into DDI_BUF_CTL
PORT_WIDTH_SELECTION.
This needs to be programmed before enabling the shared PLLs hence
add a pre_pll_enable hook for ICL and add this programming in that hook.
v2:
* Remove the check for combophy port (Jose)
* Simplify the port reversal check logic (Jose)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181023191248.26418-2-manasi.d.navare@intel.com
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This patch fixes the macros used for defining the DFLEXDPMLE
register bit fields. This accounts for changes in the spec.
Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: <stable@vger.kernel.org> # v4.19+
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181023191248.26418-1-manasi.d.navare@intel.com
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enc_to_dig_port() returns NULL for encoders of type
INTEL_OUTPUT_DP_MST causing the crash bellow:
[ 2832.836101] BUG: unable to handle kernel paging request at 00000000000012b8
[ 2832.843062] PGD 0 P4D 0
[ 2832.845610] Oops: 0000 [#1] SMP
[ 2832.848764] CPU: 2 PID: 3577 Comm: kworker/2:0 Tainted: G W 4.19.0-rc7+ #491
[ 2832.857106] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.2352.A01.1808281852 08/28/2018
[ 2832.870734] Workqueue: events output_poll_execute
[ 2832.875480] RIP: 0010:icl_get_dpll+0xa4/0x5d0 [i915]
[ 2832.880449] Code: e9 03 f3 48 ab 8b 6e 74 41 8b 8c 24 5c 03 00 00 85 ed 0f 88 3f 02 00 00 83 fd 01 0f 8e ad 01 00 00 83 fd 05 0f 8f 2d 02 00 00 <83> ba b8 12 00 00 02 48 8b 36 0f 84 39 02 00 00 44 8b be ec 89 00
[ 2832.899176] RSP: 0018:ffffc90001b57a78 EFLAGS: 00010293
[ 2832.904404] RAX: 0000000000000000 RBX: ffffc90001b57a94 RCX: 0000000000083d60
[ 2832.911536] RDX: 0000000000000000 RSI: ffff8804a8c0dc00 RDI: ffffc90001b57b18
[ 2832.918668] RBP: 0000000000000003 R08: ffff8804a8c1f990 R09: ffff8804a8c1f990
[ 2832.925797] R10: 0000000000000000 R11: ffff8804a8e99600 R12: ffff8804a7760000
[ 2832.932930] R13: ffff88049e94d000 R14: ffff88049e94d000 R15: 000000000000000e
[ 2832.940063] FS: 0000000000000000(0000) GS:ffff8804b0300000(0000) knlGS:0000000000000000
[ 2832.948147] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 2832.953893] CR2: 00000000000012b8 CR3: 0000000004a1d004 CR4: 0000000000760ee0
[ 2832.961027] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 2832.968155] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[ 2832.975286] PKRU: 55555554
[ 2832.978003] Call Trace:
[ 2832.980496] haswell_crtc_compute_clock+0x3d/0x68 [i915]
[ 2832.985841] intel_crtc_atomic_check+0x61/0x340 [i915]
[ 2832.990987] drm_atomic_helper_check_planes+0x130/0x1c0
[ 2832.996245] intel_atomic_check+0x4d5/0x10f0 [i915]
[ 2833.001147] drm_atomic_check_only+0x484/0x690
[ 2833.005629] drm_atomic_commit+0x13/0x50
[ 2833.009564] restore_fbdev_mode_atomic+0x1c9/0x1e0
[ 2833.014363] drm_fb_helper_restore_fbdev_mode_unlocked+0x47/0x90
[ 2833.020368] drm_fb_helper_set_par+0x29/0x50
[ 2833.024641] drm_fb_helper_hotplug_event.part.33+0x92/0xb0
[ 2833.030130] drm_kms_helper_hotplug_event+0x26/0x30
[ 2833.035013] output_poll_execute+0x192/0x1b0
[ 2833.039293] process_one_work+0x2a5/0x5f0
[ 2833.043315] worker_thread+0x2d/0x3d0
[ 2833.046988] ? rescuer_thread+0x340/0x340
[ 2833.051009] kthread+0x112/0x130
[ 2833.054247] ? kthread_create_worker_on_cpu+0x70/0x70
[ 2833.059307] ret_from_fork+0x3a/0x50
[ 2833.062893] Modules linked in: i915 prime_numbers snd_hda_codec_realtek snd_hda_codec_generic asix snd_usb_audio snd_usbmidi_lib snd_seq_midi snd_seq_midi_event snd_rawmidi cdc_ether usbnet x86_pkg_temp_thermal xhci_pci xhci_hcd ucsi_acpi typec_ucsi typec efivarfs [last unloaded: prime_numbers]
[ 2833.088917] CR2: 00000000000012b8
[ 2833.092241] ---[ end trace 25f9fe3d47af2e75 ]---
[ 2833.096895] RIP: 0010:icl_get_dpll+0xa4/0x5d0 [i915]
[ 2833.101866] Code: e9 03 f3 48 ab 8b 6e 74 41 8b 8c 24 5c 03 00 00 85 ed 0f 88 3f 02 00 00 83 fd 01 0f 8e ad 01 00 00 83 fd 05 0f 8f 2d 02 00 00 <83> ba b8 12 00 00 02 48 8b 36 0f 84 39 02 00 00 44 8b be ec 89 00
[ 2833.120589] RSP: 0018:ffffc90001b57a78 EFLAGS: 00010293
[ 2833.125815] RAX: 0000000000000000 RBX: ffffc90001b57a94 RCX: 0000000000083d60
[ 2833.132946] RDX: 0000000000000000 RSI: ffff8804a8c0dc00 RDI: ffffc90001b57b18
[ 2833.140080] RBP: 0000000000000003 R08: ffff8804a8c1f990 R09: ffff8804a8c1f990
[ 2833.147213] R10: 0000000000000000 R11: ffff8804a8e99600 R12: ffff8804a7760000
[ 2833.154350] R13: ffff88049e94d000 R14: ffff88049e94d000 R15: 000000000000000e
[ 2833.161483] FS: 0000000000000000(0000) GS:ffff8804b0300000(0000) knlGS:0000000000000000
[ 2833.169565] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 2833.175313] CR2: 00000000000012b8 CR3: 0000000004a1d004 CR4: 0000000000760ee0
[ 2833.182449] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 2833.189578] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[ 2833.196712] PKRU: 55555554
MST ports are allocated from struct intel_dp_mst_encoder not from
struct intel_digital_port as regular ports, so to get the TC type it
is necessary check the primary digital port of the mst encoder.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030215750.28213-5-jose.souza@intel.com
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It is only used by eDP ports so no need to initialize it for each DP
port.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030215750.28213-4-jose.souza@intel.com
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Otherwise it would be in a inconsistent state as port is disconnected
but with a valid tc type.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030215750.28213-3-jose.souza@intel.com
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Otherwise it would be in a inconsistent state as port is disconnected
but with a valid tc type.
Also setting it to unknown will earlier return
icl_tc_phy_disconnect() for any future calls to
intel_digital_port_connected(), this way we don't need to check if
port is marked as safe everytime.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030215750.28213-2-jose.souza@intel.com
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Besides of give the expected output of i915_display_info it will also
avoid some aux ch transactions that would timeout by obvious reasons.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181030215750.28213-1-jose.souza@intel.com
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Let's not leak obj->framebuffer_references when we decide that
the framebuffer domensions are not suitable for NV12.
Cc: stable@vger.kernel.org
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Vidya Srinivas <vidya.srinivas@intel.com>
Fixes: e44134f2673c ("drm/i915: Add NV12 support to intel_framebuffer_init")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181029140031.11765-1-ville.syrjala@linux.intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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Use intel_panel_actually_set_backlight() instead of a direct
call to pwm_config() in pwm_disable_backlight().
The main benefit is consistent debug logging when we turn off the
backlight. Currently we see nothing in dmesg which made me wonder
whether the backlight was even getting turned off properly.
The second benefit is consistency; This is what we do for all
the other backlight implementations.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181024155208.18987-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jani Nikula <jani.nikula@intel.com>
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supported
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-6-manasi.d.navare@intel.com
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This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as input arguments
so that this can be called in intel_dp_mode_valid (Manasi)
v5:
* Get the max slice width from DPCD
* Check against Min_Slice_width of 2560 (Anusha)
v4:
* #defines for PPR in slice count helper (Gaurav)
v3:
* Simply logic for bpp (DK)
* Limit the valid slice count by max supported by Sink (Manasi)
v2:
* Change the small joiner RAM buffer constant as bspec changed (Manasi)
* rename it as SMALL_JOINER since we are not enabling
big joiner yet (Anusha)
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-5-manasi.d.navare@intel.com
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This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing corresponding DPCD registers.
v4:
* Add helper to give line buf bit depth (Manasi)
* Correct the bit masking in color depth helper (manasi)
v3:
* Use SLICE_CAP_2 for DP (Anusha)
v2:
* Add DSC sink support macro (Jani N)
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Acked-by: Sean Paul <seanpaul@chromium.org> (For merging through
drm-intel)
Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-4-manasi.d.navare@intel.com
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