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* drm/msm: change gem->vmap() to get/putRob Clark2016-07-169-14/+41
| | | | | | | | Before we can add vmap shrinking, we really need to know which vmap'ings are currently being used. So switch to get/put interface. Stubbed put fxns for now. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: shrinker supportRob Clark2016-07-166-0/+180
| | | | | | | | For a first step, only purge obj->madv==DONTNEED objects. We could be more agressive and next try unpinning inactive objects.. but that is only useful if you have swap. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add put_iova() helperRob Clark2016-07-161-9/+21
| | | | | | We'll need this too for shrinker/purging. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add madvise ioctlRob Clark2016-07-164-2/+78
| | | | | | | Doesn't do anything too interesting until we wire up shrinker. Pretty much lifted from i915. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: use mutex_lock_interruptible for submit ioctlRob Clark2016-07-161-4/+9
| | | | | | Be kinder to things that do lots of signal handling (ie. Xorg) Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Don't get DSI index from DTArchit Taneja2016-07-168-12/+75
| | | | | | | | | | | | | | | | | | | | The DSI host and PHY driver currently expects the DT bindings to provide custom properties "qcom,dsi-host-index" and "qcom,dsi-phy-index" so that the driver can identify which DSI instance it is. The binding isn't acceptable, but the driver still needs to figure out what its instance id. This is now done by storing the mmio starting addresses for each DSI instance in every SoC version in the driver. The driver then identifies the index number by trying to match the stored address with comparing the resource start address we get from DT. We don't have compatible strings for DSI PHY on each SoC, but only the DSI PHY type. We only support one SoC version for each PHY type, so we get away doing the same thing above for the PHY driver. We can revisit this when we support two SoCs with the same DSI PHY. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Update compatible strings for MDSS/MDP5Archit Taneja2016-07-162-5/+11
| | | | | | | | | | | | | | | | | Introduce new compatible strings for the top level MDSS wrapper device, and the MDP5 device. Previously, the "qcom,mdp5" and "qcom,mdss_mdp" compatible strings were used to match the top level platform_device (which was also tied to the top level drm_device struct). Now, these strings are used to match the MDP5 platform device. Use "qcom,mdss" as the compatible string for top level MDSS device. This is now used to match the top level platform_device (which is tied to the drm_device struct). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Drop the gpu bindingArchit Taneja2016-07-161-20/+22
| | | | | | | | | | | | | | | The driver currently identifies the GPU components it needs by parsing a phandle list from the 'gpus' DT property. This isn't the right binding to go with. So, for now, just search all device nodes and find the gpu node we need by parsing a list of compatible strings. Once we know how to link the kms and gpu drivers, we'll drop this method and use the correct binding. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Add components for MDP5Archit Taneja2016-07-161-2/+59
| | | | | | | | | | | | | For MDP5 based platforms, the master device isn't the MDP5 platform device, but the top level MDSS device, which is a parent to MDP5 and interface (DSI, HDMI, eDP etc) devices. In order to add components on MDP5 platforms, we first need to populate the MDSS children, locate the MDP5 child, and then parse its ports to get the display interfaces. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Add display components by parsing MDP portsArchit Taneja2016-07-161-1/+55
| | | | | | | | | | | | | | | | | | The kms driver currently identifies all the mdss components it needs by parsing a phandle list from the 'connectors' DT property. Instead of this, describe a list of ports that the MDP hardware provides to the external world. These ports are linked to external encoder interfaces such as DSI, HDMI. These are also the subcomponent devices that we need add. This description of ports complies with the generic graph bindings. The LVDS port is a special case since it is a part of MDP4 itself, and its output connects directly to the LVDS panel. In this case, we don't try to add it as a component. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Create separate funcs for adding display/gpu componentsArchit Taneja2016-07-161-2/+20
| | | | | | | Simplifies some of the code that we'll add later. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add missing mdp5_enable/disable callsArchit Taneja2016-07-162-0/+4
| | | | | | | | | Since runtime PM isn't implemented yet, we need to call mdp5_enable/disable in a few more places. These would later be replaced by runtime PM get/put calls. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Call pm_runtime_enable/disable for newly created devicesArchit Taneja2016-07-166-4/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new device hierarchy for MDP5, we need to enable runtime PM for both the toplevel MDSS device and the MDP5 device itself. Enable runtime PM for the new devices. Since MDP4 and MDP5 now have different places where runtime PM is enabled, remove the previous pm_runtime_enable/disable calls, and squash them in the respective kms drivers. The new device hierarchy (as expressed in the DT bindings) has the GDSC tied only to the MDSS wrapper device. This GDSC needs to be enabled for accessing any register in the MDSS sub-blocks. Once every driver is runtime adapted, the GDSC will be enabled when any sub-block device calls runtime_get because of the parent-child relationship with MDSS. Until then, we call pm_runtime_get_sync() once for the MDSS device to ensure the GDSC is never disabled. This will be removed once all the drivers are runtime PM adapted. The error handling paths become a bit tricky when we call these runtime PM funcs. There doesn't seem to be any helper that checks if runtime PM is enabled already. Add bool variables in mdp4_kms/mdp5_kms structs to check if the driver had managed to call pm_runtime_enable before bailing out. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Update the register offsets of MDP5 sub-blocksArchit Taneja2016-07-161-59/+54
| | | | | | | | | | | | The MDP5 sub-block register offsets are relative to the top level MDSS register address. Now that we have the start of MDP5 register address space, provide the offsets relative to that. This involves subtracting the offsets with 0x1000 or 0x100 depending on the MDP5 version. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Use updated MDP5 register namesArchit Taneja2016-07-168-160/+143
| | | | | | | | | | | | | | | | | | | | Since MDSS registers were stuffed within the the MDP5 register space, we had an __offset_MDP() macro to identify the offset between the start of MDSS and MDP5 address spaces. This offset macro expected a MDP index argument, which didn't make much sense since we don't have multiple MDPs. The offset is no longer needed now that we have devices for the 2 different register address spaces. Also, remove the "REG_MDP5_MDP_" prefix to "REG_MDP5_". Update the generated headers in mdp5.xml.h We generally update headers as a separate patch, but we need to do these together to prevent breaking build. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Remove old kms init/destroy funcsArchit Taneja2016-07-164-236/+4
| | | | | | | | | With the new kms_init/destroy funcs in place for MDP5, we can get rid of the old kms funcs. Some members of the mdp5_kms struct also become redundant, so we remove those too. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Use the new hierarchy and drop old irq managementArchit Taneja2016-07-163-119/+18
| | | | | | | | | | | | | | Call msm_mdss_init in msm_drv to set up top level registers/irq line. Start using the new kms_init2/destroy2 funcs to inititalize MDP5 KMS. With the MDSS interrupt and irqdomain set up, the old MDP5 irq code can be dropped. The mdp5_hw_init kms func now uses the platform device tied to MDP5 instead of the one tied to the drm_device/MDSS. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Prepare new kms_init funcsArchit Taneja2016-07-162-0/+116
| | | | | | | | | | | | | | | | With MDP5 as a new device, we need to do less for MDP when initializing modeset after all the components are bound. Create mdp5_kms_init2/destroy2 funcs that inits modeset. These will eventually replace the older kms_init/destroy funcs. In the new kms_init2, the platform_device used is the one corresponding to the new MDP5 platform_device. The new change here is that the irq is now retrieved using irq_of_parse_and_map(), since MDP5 is a child interrupt of the MDSS interrupt controller. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Create a separate MDP5 deviceArchit Taneja2016-07-164-3/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to have a tree-like device hierarchy between MDSS and its sub-blocks (MDP5, DSI, HDMI, eDP etc), we need to create a separate device/driver for MDP5. Currently, MDP5 and MDSS are squashed together are are tied to the top level platform_device, which is also the one used to create drm_device. The mdp5_kms_init code is split into two parts. The part where device resources are allocated are associated with the MDP5 driver's probe, the rest is executed later when we initialize modeset. With this change, unlike MDP4, the MDP5 platform_device isn't tied to the top level drm_device anymore. The top level drm_device is now associated with a platform device that corresponds to MDSS wrapper hardware. Create mdp5_init/destroy funcs that will be used by the MDP5 driver probe/remove. Use the HW_VERSION register in the MDP5 register address space. Both the MDSS and MDP VERSION registers give out identical version info. The older mdp5_kms_init code is left as is for now, this would be removed later when we have all the pieces to support the new device hierarchy. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add MDSS top level driverArchit Taneja2016-07-164-0/+230
| | | | | | | | | | | | | | | | | | | | SoCs that contain MDP5 have a top level wrapper called MDSS that manages clocks, power and irq for the sub-blocks within it. Currently, the MDSS portions are stuffed into the MDP5 driver. This makes it hard to represent the DT bindings in the correct way. We create a top level MDSS helper that handles these parts. This is essentially moving out some of the mdp5_kms irq code and MDSS register space and keeping it as a separate entity. We haven't given any clocks to the top level MDSS yet, but a AHB clock would be added in the future to access registers. One thing to note is that the resources allocated by this helper are tied to the top level platform_device (the one that allocates the drm_device struct too). This device would be the parent to MDSS sub-blocks like MDP5, DSI, eDP etc. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Get irq number within kms driver itselfArchit Taneja2016-07-164-8/+31
| | | | | | | | | | | | | | | | | | | | | | The driver gets the irq number using platform_get_irq on the main kms platform device. This works fine since both MDP4 and MDP5 currently have a flat device hierarchy. The platform device tied with the drm_device points to the MDP DT node in both cases. This won't work when MDP5 supports a tree-like hierarchy. In this case, the platform device tied to the top level drm_device is the MDSS DT node, and the irq we need for KMS is the one generated by MDP5, not MDSS. Get the irq number from the MDP4/5 kms driver itself. Each driver can later provide the irq number based on what device hierarchy it uses. While we're at it, call drm_irq_install only when we have a valid KMS driver. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Remove unused fieldsArchit Taneja2016-07-161-5/+0
| | | | | | | | These aren't used. Probably left overs when driver was refactored to support both MDP4 and MDP5. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Drop the id_table in platform_driverArchit Taneja2016-07-161-6/+0
| | | | | | | This isn't needed as we only support OF. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Use a standard DT binding for data lanesArchit Taneja2016-07-161-3/+14
| | | | | | | | | | | | | | | | A more standard DT binding describing data lanes already exists here: Documentation/devicetree/bindings/media/video-interfaces.txt Use this binding instead of "qcom,data-lane-map". One difference in the standard binding w.r.t to the existing binding is that it provides a logical to physical mapping instead of the other way round. Tweak the code to translate the data the way we want it. The MSM DSI DT bindings aren't used anywhere at the moment, so it's okay to update this property. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Use generic PHY bindingsArchit Taneja2016-07-161-1/+1
| | | | | | | | | The DSI host links to the DSI PHY device using a custom binding. Switch to the generic PHY bindings. The DSI PHY driver itself doesn't use the common PHY framework for now. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Modify port parsingArchit Taneja2016-07-161-5/+5
| | | | | | | | | | | | | | | | | | The DSI interface is going to have two ports defined in its device node. The first port is always going to be the link between the MDP output and the input to DSI, the second port is going to be the link between the DSI output and the connected panel/bridge: ----- ----- ------- | MDP | ------> | DSI | ------> | Panel | ----- ----- ------- (Port 0) (Port 1) Until now, there was only one Port representing the output. Update the DSI host driver such that it parses Port #1 for a connected device. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp4: Clean up some MDP4 clocksArchit Taneja2016-07-162-20/+13
| | | | | | | | | | | | | | | | | Fix some issues with MDP4 clocks: - mdp4_dtv_encoder tries to get "src_clk", which is a RCG(TV_SRC) in MSM8960 and APQ8064. This isn't something the driver should access or configure. Instead of this, configure the "mdp_clk" (MDP_TV_CLK), a branch clock in MMCC that has the TV_SRC as its parent. Setting rate/enabling the "mdp_clk" will eventually configure "src_clk", which is what we want. - Rename "mdp_clk" to "tv_clk" because that's slightly less confusing. - Rename "mdp_axi_clk" to "bus_clk" because that's what we do elsewhere too. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Don't get source of MDP core clockArchit Taneja2016-07-162-6/+2
| | | | | | | | | | The driver expects DT to provide the parent to MDP core clock. The only operation done to the parent clock is to set a rate. This can be achieved by setting the rate on the core clock itsef. Don't try to get the parent clock anymore. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Print the correct virtual addresses in map/unmap funcsArchit Taneja2016-07-161-2/+2
| | | | | | | | The msm_iommu_map/unmap funcs have debug prints to show the list of VA:PA mappings. Use the correct variable to print the VAs. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Use correct type for physical addressesArchit Taneja2016-07-161-2/+2
| | | | | | | | | The u32 type used to pass the physical addresses to iommu_map can't accommodate 64 bit addresses. Move to dma_addr_t to ensure wrong addresses aren't provided to the IOMMU driver. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* Merge tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux into ↵Dave Airlie2016-07-165-44/+483
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drm-next This pull request brings in vc4 shader validation for branching, allowing GLSL shaders with non-unrolled loops. * tag 'drm-vc4-next-2016-07-15' of https://github.com/anholt/linux: drm/vc4: Fix a "the the" typo in a comment. drm/vc4: Fix definition of QPU_R_MS_REV_FLAGS drm/vc4: Add a getparam to signal support for branches. drm/vc4: Add support for branching in shader validation. drm/vc4: Add a bitmap of branch targets during shader validation. drm/vc4: Move validation's current/max ip into the validation struct. drm/vc4: Add a getparam ioctl for getting the V3D identity regs.
| * drm/vc4: Fix a "the the" typo in a comment.Eric Anholt2016-07-151-1/+1
| | | | | | | | Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Fix definition of QPU_R_MS_REV_FLAGSEric Anholt2016-07-151-1/+1
| | | | | | | | | | | | | | We don't use it in shader validation currently, so it had no effect, but best to fix it anyway in case we do some day. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Add a getparam to signal support for branches.Eric Anholt2016-07-151-0/+3
| | | | | | | | | | | | | | | | Userspace needs to know if it can create shaders that do branching. Otherwise, for backwards compatibility with old kernels it needs to lower if statements to conditional assignments. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Add support for branching in shader validation.Eric Anholt2016-07-154-17/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're already checking that branch instructions are between the start of the shader and the proper PROG_END sequence. The other thing we need to make branching safe is to verify that the shader doesn't read past the end of the uniforms stream. To do that, we require that at any basic block reading uniforms have the following instructions: load_imm temp, <next offset within uniform stream> add unif_addr, temp, unif The instructions are generated by userspace, and the kernel verifies that the load_imm is of the expected offset, and that the add adds it to a uniform. We track which uniform in the stream that is, and at draw call time fix up the uniform stream to have the address of the start of the shader's uniforms at that location. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Add a bitmap of branch targets during shader validation.Eric Anholt2016-07-152-2/+124
| | | | | | | | | | | | | | | | | | | | This isn't used yet, it's just a first step toward loop validation. During the main parsing of instructions, we need to know when we hit a new basic block so that we can reset validated state. v2: Fix a stray semicolon after an if block. (caught by kbuild test). Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Move validation's current/max ip into the validation struct.Eric Anholt2016-07-141-24/+30
| | | | | | | | | | | | | | Reduces the argument count for some of the functions, and will be used more with the upcoming looping support. Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/vc4: Add a getparam ioctl for getting the V3D identity regs.Eric Anholt2016-07-141-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | As I extend the driver to support different V3D revisions, userspace needs to know what version it's targeting. This is most easily detected using the V3D identity registers. v2: Make sure V3D is runtime PM on when reading the registers. v3: Switch to a 64-bit param value (suggested by Rob Clark in review) Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2) Reviewed-by: Rob Clark <robdclark@gmail.com> (v3, over irc)
* | Merge tag 'drm/panel/for-4.8-rc1' of ↵Dave Airlie2016-07-161-5/+161
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/panel: Changes for v4.8-rc1 This set of changes contains a few cleanups for existing panels as well as improved handling of certain backlights. In addition there's support for a few new simple panels. * tag 'drm/panel/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/panel: simple: Add support for Starry KR122EA0SRA panel dt-bindings: Add Starry KR122EA0SRA panel binding dt-bindings: Add vendor prefix for Starry dt-bindings: display: Add Sharp LQ101K1LY04 panel binding drm/panel: simple: Add support for Sharp LQ101K1LY04 drm/panel: simple: Add support for LG LP079QX1-SP0V panel dt-bindings: Add support for LG LP079QX1-SP0V panel drm/panel: simple: Add support for Sharp LQ123P1JX31 panel dt-bindings: Add Sharp LQ123P1JX31 panel binding drm/panel: simple: Add support for Samsung LSN122DL01-C01 panel dt-bindings: Add Samsung LSN122DL01-C01 panel binding drm/panel: simple: Add support for LG LP097QX1-SPA1 panel dt-bindings: Add LG LP097QX1-SPA1 panel binding drm/panel: simple: Update backlight state property drm/panel: simple: Remove gratuitous blank line drm/panel: simple: Fix a couple of physical sizes
| * | drm/panel: simple: Add support for Starry KR122EA0SRA panelDouglas Anderson2016-07-111-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected using eDP interfaces. EDID shows: Detailed mode: Clock 147.000 MHz, 263 mm x 164 mm 1920 1936 1952 1984 hborder 0 1200 1215 1217 1235 vborder 0 -hsync -vsync Manufacturer-specified data, tag 15 ASCII string: STARRY ASCII string: KR122EA0SRA Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for Sharp LQ101K1LY04Joshua Clayton2016-07-111-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | Add simple-panel support for the Sharp LQ101K1LY04, which is a 10" WXGA (1280x800) LVDS panel. Signed-off-by: Joshua Clayton <stillcompiling@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for LG LP079QX1-SP0V panelYakir Yang2016-07-111-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and 32 pins eDP interface. This module supports 1536x2048 mode. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for Sharp LQ123P1JX31 panelYakir Yang2016-07-111-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sharp LQ123P1JX31 is an 12.3", 2400x1600 TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for Samsung LSN122DL01-C01 panelYakir Yang2016-07-111-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Add support for LG LP097QX1-SPA1 panelYakir Yang2016-07-111-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel connected using eDP interfaces. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Update backlight state propertyThierry Reding2016-07-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Some backlight drivers ignore the power property and instead only use the state property. Fixup the panel driver to set the state property in addition to the power property. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Remove gratuitous blank lineThierry Reding2016-06-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | This blank line was introduced in commit c8521969dea2 ("drm/panel: simple: Add support for BOE TV080WUM-NL0"), likely by mistake. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | drm/panel: simple: Fix a couple of physical sizesThierry Reding2016-06-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Both the Innolux ZJ070NA-01P and Samsung LTN101NT05 were listing the horizontal and vertical resolutions in the size.width and size.height fields, whereas they should contain the physical dimensions of the panel. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | | Merge tag 'drm/tegra/for-4.8-rc1' of ↵Dave Airlie2016-07-169-567/+1351
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.8-rc1 This set of changes contains a bunch of cleanups to the host1x driver as well as the addition of a pin controller for DPAUX, which is required by boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C mode (for HDMI and DDC). Included is also a bit of rework of the SOR driver in preparation to add DisplayPort support as well as some refactoring and cleanup. Finally, all output drivers are converted to runtime PM, which greatly simplifies the handling of clocks and resets. * tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits) drm/tegra: sor: Reject HDMI 2.0 modes drm/tegra: sor: Prepare for generic PM domain support drm/tegra: dsi: Prepare for generic PM domain support drm/tegra: sor: Make XBAR configurable per SoC drm/tegra: sor: Use sor1_src clock to set parent for HDMI dt-bindings: display: tegra: Add source clock for SOR drm/tegra: sor: Implement sor1_brick clock drm/tegra: sor: Implement runtime PM drm/tegra: hdmi: Implement runtime PM drm/tegra: dsi: Implement runtime PM drm/tegra: dc: Implement runtime PM drm/tegra: hdmi: Enable audio over HDMI drm/tegra: sor: Do not support deep color modes drm/tegra: sor: Extract tegra_sor_mode_set() drm/tegra: sor: Split out tegra_sor_apply_config() drm/tegra: sor: Rename tegra_sor_calc_config() drm/tegra: sor: Factor out tegra_sor_set_parent_clock() drm/tegra: dpaux: Add pinctrl support dt-bindings: Add bindings for Tegra DPAUX pinctrl driver drm/tegra: Prepare DPAUX for supporting generic PM domains ...
| * | | drm/tegra: sor: Reject HDMI 2.0 modesThierry Reding2016-07-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling HDMI 2.0 modes requires extra programming and will not work with the current driver, so reject all those modes. Signed-off-by: Thierry Reding <treding@nvidia.com>
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