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path: root/drivers/gpu/drm
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* drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequenceJani Nikula2014-11-073-0/+60
* drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequenceJani Nikula2014-11-071-32/+31
* drm/i915/skl: Enable Gen9 RC6Zhe Wang2014-11-071-1/+51
* drm/i915/skl: Gen9 ForcewakeZhe Wang2014-11-073-2/+184
* drm/i915/skl: Log the order in which we flush the pipes in the WM codeDamien Lespiau2014-11-071-4/+7
* drm/i915/skl: Flush the WM configurationDamien Lespiau2014-11-071-0/+135
* drm/i915/skl: Stage the pipe DDB allocationDamien Lespiau2014-11-072-7/+8
* drm/i915/skl: Reduce the indentation level in skl_write_wm_values()Damien Lespiau2014-11-071-21/+21
* drm/i915/skl: Correctly align skl_compute_plane_wm() argumentsDamien Lespiau2014-11-071-5/+5
* drm/i915/skl: Rework when the transition WMs are computedDamien Lespiau2014-11-071-15/+31
* drm/i915/skl: Move all the WM compute functions in one placeDamien Lespiau2014-11-071-22/+22
* drm/i915/skl: Reduce the number of holes in struct skl_wm_levelDamien Lespiau2014-11-071-1/+1
* drm/i915/skl: Make res_blocks/lines intermediate values 32 bitsDamien Lespiau2014-11-071-16/+11
* drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm()Damien Lespiau2014-11-071-2/+2
* drm/i915/skl: Make 'end' of the DDB allocation entry exclusiveDamien Lespiau2014-11-072-15/+21
* drm/i915/skl: Check the DDB state at modesetDamien Lespiau2014-11-074-2/+64
* drm/i915/skl: Add a debugfs file to dump the DDB allocationDamien Lespiau2014-11-071-0/+37
* drm/i915/skl: Augment the latency debugfs files for SKLDamien Lespiau2014-11-071-14/+62
* drm/i915/skl: Read back the DDB allocation hw stateDamien Lespiau2014-11-071-0/+29
* drm/i915/skl: Store the new WM state at the very end of the updateDamien Lespiau2014-11-071-2/+3
* drm/i915/gen9: Disable WM if corresponding latency is 0Vandana Kannan2014-11-071-2/+12
* drm/i915/gen9: Add 2us read latency to WM levelVandana Kannan2014-11-071-0/+16
* drm/i915/skl: Read the pipe WM HW statePradeep Bhat2014-11-073-1/+108
* drm/i915/skl: Program the DDB allocationDamien Lespiau2014-11-072-0/+25
* drm/i915/skl: Allocate DDB portions for display planesDamien Lespiau2014-11-071-0/+148
* drm/i915/skl: SKL Watermark ComputationPradeep Bhat2014-11-072-1/+433
* drm/i915/skl: Add DDB allocation management structuresDamien Lespiau2014-11-071-0/+19
* drm/i915/skl: Definition of SKL WM param structs for pipe/planePradeep Bhat2014-11-073-0/+34
* drm/i915/skl: Register definitions and macros for SKL Watermark regsPradeep Bhat2014-11-071-0/+35
* drm/i915/skl: Read the Memory Latency Values for WM computationPradeep Bhat2014-11-073-6/+83
* drm/i915: rewrite hsw/bdw audio codec enable/disable sequencesJani Nikula2014-11-071-64/+51
* drm/i915: clean up and clarify audio related register definesJani Nikula2014-11-072-88/+89
* drm/i915: Report the actual swizzling back to userspaceChris Wilson2014-11-071-0/+1
* drm/i915: Request PIN_GLOBAL when pinning a vma for GTT relocationsChris Wilson2014-11-072-2/+5
* drm/i915: Only mark as map-and-fenceable when bound into the GGTTChris Wilson2014-11-071-14/+25
* drm/i915: Use vblank evade mechanism in mmio_flipAnder Conselvan de Oliveira2014-11-073-7/+39
* drm/i915: Remove modeset lock check from intel_pipe_update_start()Ander Conselvan de Oliveira2014-11-071-2/+0
* drm/i915: Add kerneldoc for intel_pipe_update_{start, end}Ander Conselvan de Oliveira2014-11-071-0/+25
* drm/i915: Remove redundant parameter to i915_gem_object_wait_rendering__tail()John Harrison2014-11-071-4/+3
* drm/i915: fix RPS on runtime suspendPaulo Zanoni2014-11-071-7/+3
* drm/i915: fix "Unexpected fault" error message line breakPaulo Zanoni2014-11-071-1/+1
* drm/i915: Kill leftover GTIIR writes from valleyview_irq_preinstall()Ville Syrjälä2014-11-071-4/+0
* drm/i915: Drop useless VLV_IIR writes from vlv_display_irq_postinstall()Ville Syrjälä2014-11-071-3/+0
* drm/i914: Refactor vlv_display_irq_postinstall()Ville Syrjälä2014-11-071-3/+8
* drm/i915: Refactor vlv_display_irq_reset()Ville Syrjälä2014-11-071-23/+17
* drm/i915: Make valleyview_display_irqs_(un)install() work for chvVille Syrjälä2014-11-071-10/+17
* drm/i915: Call gen5_gt_irq_reset() from valleyview_irq_uninstall()Ville Syrjälä2014-11-071-0/+2
* drm/i915: Use GEN5_IRQ_RESET() on vlv/chvVille Syrjälä2014-11-071-20/+5
* drm/i915: Use a consistent order between IIR, IER, IMR writes on vlv/chvVille Syrjälä2014-11-071-11/+18
* drm/i915: Drop the extra GEN8_PCU_IIR posting read from cherryview_irq_preins...Ville Syrjälä2014-11-071-2/+0
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