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path: root/drivers/gpu/drm/tegra/dpaux.c
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* drm/tegra: dpaux: Keep reset defaults for hybrid pad parametersThierry Reding2017-12-211-0/+3
| | | | | | | | Keep the reset values for the common mode voltage, output driver impedance control and output driver current control parameters. This fixes errors seen during SCDC communication with HDMI sinks. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Add Tegra186 supportThierry Reding2017-12-131-0/+1
| | | | | | | | DPAUX is the same as on previous generations. Supporting it is as simple as adding the compatible string so that the driver will bind to any of the devices. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Implement runtime PMThierry Reding2017-12-131-40/+76
| | | | | | | | Move clock and reset management into runtime PM callbacks and hook them up. This cleans up the code structure so that power management code does not clutter up the rest. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Trace register accessesThierry Reding2017-08-171-1/+7
| | | | | | Add tracepoint events for DPAUX controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Use unsigned int for register offsetsThierry Reding2017-08-171-2/+2
| | | | | | | Register offsets are usually fairly small numbers, so an unsigned int is more than enough to represent them. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Fix error handlingChristophe Jaillet2016-11-071-2/+2
| | | | | | | | | | | | | The devm_pinctrl_register() function returns an error pointer or a valid handle. So checking for NULL here is pointless and can never trigger. Check the returned value with IS_ERR instead and propagate this value as done in the other functions which call devm_pinctrl_register(). Fixes: 0751bb5c44fe ("drm/tegra: dpaux: Add pinctrl support") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Add pinctrl supportJon Hunter2016-06-301-3/+120
| | | | | | | | | | | The DPAUX pins are shared with an internal I2C controller. To allow these pins to be muxed to the I2C controller, register a pinctrl device for the DPAUX device. This is based upon work by Thierry Reding <treding@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Prepare DPAUX for supporting generic PM domainsJon Hunter2016-06-301-8/+17
| | | | | | | | | | | | | | | | | | | To utilise the DPAUX on Tegra, the SOR power partition must be enabled. Now that Tegra supports the generic PM domain framework we manage the SOR power partition via this framework for DPAUX. However, the sequence for gating/ungating the SOR power partition requires that the DPAUX reset is asserted/de-asserted at the time the SOR power partition is gated/ungated, respectively. Now that the reset control core assumes that resets are exclusive, the Tegra generic PM domain code and the DPAUX driver cannot request the same reset unless we mark the resets as shared. Sharing resets will not work in this case because we cannot guarantee that the reset will be asserted/de-asserted at the appropriate time. Therefore, given that the Tegra generic PM domain code will handle the DPAUX reset, do not request the reset in the DPAUX driver if the DPAUX device has a PM domain associated. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Add helpers for setting up padsJon Hunter2016-06-301-30/+53
| | | | | | | | | | | | | | | In preparation for adding pinctrl support for the DPAUX pads, add a couple of helpers functions to configure the pads and control their power. Please note that although a simple if-statement could be used instead of a case statement for configuring the pads as there are only two possible modes, a case statement is used because when integrating with the pinctrl framework, we need to be able to handle invalid modes that could be passed. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Clean-up on probe failureJon Hunter2016-06-301-6/+16
| | | | | | | | | If the probing of the DPAUX fails, then clocks are left enabled and the DPAUX reset de-asserted. Add code to perform the necessary clean-up on probe failure by disabling clocks and asserting the reset. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: sor: Operate on struct drm_dp_aux *Thierry Reding2015-12-141-18/+23
| | | | | | | | Instead of getting a pointer to the driver-specific wrapper of AUX channels, use the AUX channel objects directly to avoid hackish casting between the two types. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Handle I2C_WRITE_STATUS_UPDATE for address only writesVille Syrjälä2015-09-081-0/+1
| | | | | | | | | | | | A address-only I2C_WRITE can't be replied with a short i2c ack, but I suppose it could be replied with an i2c defer. So the code should be prepared for an address-only I2C_WRITE_STATUS_UPDATE. Cc: Thierry Reding <thierry.reding@gmail.com> Cc: "Terje Bergström" <tbergstrom@nvidia.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/dp: s/I2C_STATUS/I2C_WRITE_STATUS_UPDATE/Ville Syrjälä2015-09-081-1/+1
| | | | | | | | | | Rename the I2C_STATUS request to I2C_WRITE_STATUS_UPDATE to match the spec. Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
* drm/tegra: dpaux: Disable interrupt when detachedThierry Reding2015-08-131-1/+7
| | | | | | | | When the DPAUX isn't attached to an SOR the interrupts are not useful. This also prevents a race that could potentially cause a crash on driver removal. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Configure pads as I2C by defaultThierry Reding2015-08-131-0/+25
| | | | | | | | | | The DPAUX code paths already configure the pads in AUX mode, but there is no way to reconfigure them in I2C mode for HDMI (the DPAUX module is unused in that case). Enabling the pads in I2C mode by default is the quickest way to support HDMI. Eventually this may need an explicit call in the user drivers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Provide error message in probeThierry Reding2015-08-131-6/+24
| | | | | | | When probing the dpaux device fails, output proper error messages to help diagnose the cause of the failure. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Registers are 32-bitThierry Reding2015-06-121-11/+10
| | | | | | | | Use a sized unsigned 32-bit data type (u32) to store register contents. The DPAUX registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dpaux: Fix transfers larger than 4 bytesThierry Reding2015-06-121-10/+8
| | | | | | | | | The DPAUX read/write FIFO registers aren't sequential in the register space, causing transfers larger than 4 bytes to cause accesses to non- existing FIFO registers. Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support") Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Renaming DP training vswing pre emph definesSonika Jindal2014-09-031-2/+2
| | | | | | | | | | | | | | | | | | | | Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/tegra: add MODULE_DEVICE_TABLEsStephen Warren2014-08-041-0/+1
| | | | | | | | | | | | | | When tegra-drm.ko is built as a module, these MODULE_DEVICE_TABLEs allow the module to be auto-loaded since the module will match the devices instantiated from device tree. (Notes for stable: in 3.14+, just git rm any conflicting file, since they are added in later kernels. For 3.13 and below, manual merging will be needed) Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dp - Mark the connector as hotplug capableThierry Reding2014-06-051-0/+1
| | | | | | | Doing so allows the hotplug events generated by the connector to be properly handled by the DRM poll helpers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: dp - Implement hotplug detection in work queueThierry Reding2014-06-051-10/+20
| | | | | | | | Calling the drm_helper_hpd_irq_event() helper can sleep, so instead of invoking it directly from the interrupt handler, schedule a work queue and run it from there. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/dp: add a hw mutex around the transfer functions. (v2)Dave Airlie2014-06-051-2/+2
| | | | | | | | | This should avoid races between connector probing and HPD irqs in the future, currently mode_config.mutex blocks this possibility. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/tegra: dp: Support address-only I2C-over-AUX transactionsThierry Reding2014-04-081-13/+31
| | | | | | | | Certain types of I2C-over-AUX transactions require that only the address is transferred. Detect this by looking at the AUX message's size and set the address-only bit appropriately. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Add eDP supportThierry Reding2014-04-041-0/+544
Add support for eDP functionality found on Tegra124 and later SoCs. Only fast link training is currently supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
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