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path: root/drivers/gpu/drm/radeon/radeon.h
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* drm/radeon: update radeon_atom_is_voltage_gpio() for SIAlex Deucher2013-06-271-1/+2
| | | | | | SI uses a new atom table. Required for DPM on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/atom: add helper to calcuate mpll paramsAlex Deucher2013-06-271-0/+4
| | | | | | | There's a new table for calculating the memory pll parameters on SI. Required for SI DPM support. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: implement apci perf requestAlex Deucher2013-06-271-1/+1
| | | | | | | These functions use acpi methods to adjust the pcie gen speed. Used by DPM. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: remove broken dyn state remnantsAlex Deucher2013-06-271-1/+0
| | | | | | | Now that the proper fix has been implemented I can remove the last remnants of the initial implementation. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add new pre/post_set_power_state callbacksAlex Deucher2013-06-271-0/+4
| | | | | | Needed to properly handle dynamic state adjustment. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fixup dynamic state adjust for btc (v2)Alex Deucher2013-06-271-0/+13
| | | | | | | | | Use a dedicated copy of the current power state since we may have to adjust it on the fly. v2: fix up redundant state sets Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: fixup dynamic state adjust for sumoAlex Deucher2013-06-271-0/+1
| | | | | | | Use a dedicated copy of the current power state since we may have to adjust it on the fly. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: track whether we are on AC or batteryAlex Deucher2013-06-271-0/+1
| | | | | | Driver needs this information to validate power states. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add helpers for extended power tables (v2)Alex Deucher2013-06-271-0/+70
| | | | | | | | This data will be needed for dpm on newer asics. v2: fix typo in rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: enable UVD as needed (v9)Alex Deucher2013-06-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using UVD, the driver must switch to a special UVD power state. In the CS ioctl, switch to the power state and schedule work to change the power state back, when the work comes up, check if uvd is still busy and if not, switch back to the user state, otherwise, reschedule the work. Note: We really need some better way to decide when to switch out of the uvd power state. Switching power states while playback is active make uvd angry. V2: fix locking. V3: switch from timer to delayed work V4: check fence driver for UVD jobs, reduce timeout to 1 second and rearm timeout on activity v5: rebase on new dpm tree v6: rebase on interim uvd on demand changes v7: fix UVD when DPM is disabled v8: unify non-DPM and DPM UVD handling v9: remove leftover idle work struct Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
* drm/radeon/kms: add dpm support for evergreen (v4)Alex Deucher2013-06-271-0/+13
| | | | | | | | | | | | | | | | | This adds dpm support for evergreen asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) Set radeon.dpm=1 to enable. v2: reduce stack usage, rename ulv struct v3: fix thermal interrupt check notices by Jerome v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: add dpm support for rv7xx (v4)Alex Deucher2013-06-271-0/+1
| | | | | | | | | | | | | | | | | This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: add dpm support for rv6xx (v3)Alex Deucher2013-06-271-0/+3
| | | | | | | | | | | | | | | | | This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* drm/radeon/kms: add common r600 dpm functionsAlex Deucher2013-06-271-0/+13
| | | | | | These are shared by rs780/rs880, rv6xx, and newer chips. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: add common dpm infrastructureAlex Deucher2013-06-271-1/+99
| | | | | | | | | | | | This adds the common dpm (dynamic power management) infrastructure: - dpm callbacks - dpm init/fini/suspend/resume - dpm power state selection No device specific code is enabled yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: add atom helper functions for dpm (v3)Alex Deucher2013-06-271-0/+33
| | | | | | | | | | dpm needs access to atombios data and command tables for setup and calculation of a number of parameters. v2: endian fix v3: fix mc reg table bug Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: properly set up the RLC on ON/LN/TN (v3)Alex Deucher2013-06-271-3/+10
| | | | | | | | | This is required for certain advanced functionality. v2: save/restore list takes dword offsets v3: rebase on gpu reset changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: make get_temperature functions a callbackAlex Deucher2013-06-271-5/+2
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/evergreen: add indirect register accessors for CG registersAlex Deucher2013-06-271-0/+17
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: add accessors for RCU indirect spaceAlex Deucher2013-06-271-0/+17
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add cik tile mode array queryAlex Deucher2013-06-271-0/+1
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: Add support for compute queues (v4)Alex Deucher2013-06-271-0/+19
| | | | | | | | | | | | | | | | | | | | | On CIK, the compute rings work slightly differently than on previous asics, however the basic concepts are the same. The main differences: - New MEC engines for compute queues - Multiple queues per MEC: - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues - KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues - Queues can be allocated and scheduled by another queue - New doorbell aperture allows you to assign space in the aperture for the wptr which allows for userspace access to queues v2: add wptr shadow, fix eop setup v3: fix comment v4: switch to new callback method Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
* drm/radeon: implement simple doorbell page allocatorAlex Deucher2013-06-271-0/+21
| | | | | | | | | | | The doorbell aperture is a PCI BAR whose pages can be mapped to compute resources for things like wptrs for userspace queues. This patch maps the BAR and sets up a simple allocator to allocate pages from the BAR. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use callbacks for ring pointer handling (v3)Alex Deucher2013-06-271-0/+7
| | | | | | | | | | | | | | Add callbacks to the radeon_asic struct to handle rptr/wptr fetchs and wptr updates. We currently use one version for all rings, but this allows us to override with a ring specific versions. Needed for compute rings on CIK. v2: udpate as per Christian's comments v3: fix some rebase cruft Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add indirect register accessors for SMC registersAlex Deucher2013-06-261-0/+17
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: add hw cursor support (v2)Alex Deucher2013-06-261-0/+7
| | | | | | | | | | | CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit v2: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: handle the integrated thermal controller on CIAlex Deucher2013-06-261-0/+1
| | | | | | No support for reading the temperature yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: add support for sDMA dma engines (v8)Alex Deucher2013-06-251-0/+1
| | | | | | | | | | | | | | | | | | CIK has new asynchronous DMA engines called sDMA (system DMA). Each engine supports 1 ring buffer for kernel and gfx and 2 userspace queues for compute. TODO: fill in the compute setup. v2: update to the latest reset code v3: remove ib_parse v4: fix copy_dma() v5: drop WIP compute sDMA queues v6: rebase v7: endian fixes for IB v8: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add support for interrupts on CIK (v5)Alex Deucher2013-06-251-0/+11
| | | | | | | | | | | | Todo: - handle interrupts for compute queues v2: add documentation v3: update to latest reset code v4: update to latest illegal CP handling v5: fix missing break in interrupt handler switch statement Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add initial ucode loading for CIK (v5)Alex Deucher2013-06-251-0/+1
| | | | | | | | | | | | | | | | | Currently the driver required 6 sets of ucode: 1. pfp - pre-fetch parser, part of the GFX CP 2. me - micro engine, part of the GFX CP 3. ce - constant engine, part of the GFX CP 4. rlc - interrupt, etc. controller 5. mc - memory controller (discrete cards only) 6. mec - compute engines, part of Compute CP V2: add documentation V3: update MC ucode V4: rebase V5: update mc ucode Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add gpu init support for CIK (v9)Alex Deucher2013-06-251-0/+30
| | | | | | | | | | | | | v2: tiling fixes v3: more tiling fixes v4: more tiling fixes v5: additional register init v6: rebase v7: fix gb_addr_config for KV/KB v8: drop wip KV bits for now, add missing config reg v9: fix cu count on Bonaire Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add DCE8 macro for CIKAlex Deucher2013-06-251-0/+1
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add a reset work handlerAlex Deucher2013-06-251-0/+1
| | | | | | | | | | | | New asics support non-privileged IBs. This allows us to skip IB checking in the driver since the hardware will check the command buffers for us. When using non-privileged IBs, if the CP encounters an illegal register in the command stream, it will halt and generate an interrupt. The CP needs to be reset to continue. For now just do a full GPU reset when this happens. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: track which asics have UVDAlex Deucher2013-05-201-0/+1
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add chip family for HainanAlex Deucher2013-05-201-0/+1
| | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* drm/radeon: consolidate UVD clock programmingChristian König2013-05-021-0/+11
| | | | | | | | Instead of duplicating the code over and over again, just use a single function to handle the clock calculations. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* radeon: add bo tracking debugfsJerome Glisse2013-05-021-1/+4
| | | | | | | | | | | | This is to allow debugging of userspace program not freeing buffer after, which is basicly a memory leak. This print the list of all gem object along with their size and placement (VRAM,GTT,CPU) and with the pid of the task that created them. agd5f: add warning fix Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add helper function to support golden registersAlex Deucher2013-04-231-0/+3
| | | | | | | Golden registers are arrays of register settings from the hw team that need to be initialized at asic startup. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: switch audio handling to use callbacksAlex Deucher2013-04-231-5/+5
| | | | | | | | | Register audio callbacks for asic where we support audio. Cleans up the code and makes it easier to add support for newer asics. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: raise UVD clocks only on demandChristian König2013-04-231-0/+2
| | | | | | | | | That not only saves some power, but also solves problems with older chips where an idle UVD block on higher clocks can cause problems. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add helpers for masking and setting bits in regsRafał Miłecki2013-04-221-0/+2
| | | | | | Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add si tile mode array query v3Jerome Glisse2013-04-111-0/+1
| | | | | | | | | | | Allow userspace to query for the tile mode array so userspace can properly compute surface pitch and alignment requirement depending on tiling. v2: Make strict aliasing safer by casting to char when copying v3: merge fix from Christian Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORTAlex Deucher2013-04-091-2/+2
| | | | | | Avoid confusion with the *REG32_P mask macro. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add radeon_atom_get_clock_dividers helperChristian König2013-04-091-0/+5
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add pm callback for setting uvd clocksAlex Deucher2013-04-091-0/+2
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: UVD bringup v8Christian König2013-04-091-4/+37
| | | | | | | | | | | | | Just everything needed to decode videos using UVD. v6: just all the bugfixes and support for R7xx-SI merged in one patch v7: UVD_CGC_GATE is a write only register, lockup detection fix v8: split out VRAM fallback changes, remove support for RV770, add support for HEMLOCK, add buffer sizes checks Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rework fallback handling v2Christian König2013-04-091-2/+3
| | | | | | | | | | Let the CS module decide if we can fall back to VRAM or not. v2: remove unintended change Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Use direct mapping for fast fb access on RS690Samuel Li2013-04-091-0/+2
| | | | | | | | | | | | | | | This patch allows the CPU to map the stolen vram segment directly rather than going through the PCI BAR. This significantly improves performance for certain workloads with a properly patched ddx. Use radeon.fastfb=1 to enable it (disabled by default). Currently only supported on RS690, but support for RS780/880 and newer APUs may be added eventually. Signed-off-by: Samuel Li <samuel.li@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: clean up vram/gtt location handlingAlex Deucher2013-04-091-0/+1
| | | | | | | | | Add a per-asic MC (memory controller) mask which holds the mak address mask the asic is capable of. Use this when calculating the vram and gtt locations rather using asic specific functions or limiting everything to 32 bits. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'drm-next-3.9' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2013-02-211-0/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next More drm-next bits for radeon. Just bug fixes. * 'drm-next-3.9' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: properly validate the atpx interface drm/radeon: switch get_gpu_clock() to a callback (v2) drm/radeon: add a asic callback to get the xclk drm/radeon: Avoid NULL pointer dereference from atom_index_iio() allocation failure drm/radeon: remove overzealous warning in hdmi handling drm/radeon: fix multi-head power profile stability on BTC+ asics
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