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| * | Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2014-08-281-6/+4
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next More radeon changes for drm-next. Highlights: - UVD support for older asics - Reset rework in preparation for Maarten's fence patches I have a few more patches which depend on Christian's ttm changes, I'll send them out separately once you've merged the ttm changes. * 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: drop doing resets in a work item drm/radeon: drop RADEON_FENCE_SIGNALED_SEQ v2 drm/radeon: add timeout argument to radeon_fence_wait_seq v2 drm/radeon: handle lockup in delayed work, v5 drm/radeon: take exclusive_lock in read mode during ring tests, v5 drm/radeon: force fence completion only on problematic rings (v2) drm/radeon: wake up all fences on manual reset drm/radeon: add UVD fw names for older asic drm/radeon: enable RB_ARB before resetting the VCPU drm/radeon: 760G/780V/880V don't have UVD drm/radeon: implement UVD hw workarounds for R6xx v3 drm/radeon: add UVD support for older asics v4 drm/radeon: add set_uvd_clocks callback for r6xx v4 drm/radeon: properly init UVD MC bits on R600 drm/radeon: force UVD buffers into VRAM on RS[78]80 v2 drm/radeon: move the IB test after the AGP fallback
| | * | drm/radeon: drop doing resets in a work itemChristian König2014-08-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Blocking completely innocent processes with a GPU reset is a pretty bad idea. Just set needs_reset and let the next command submission or fence wait do the job. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | drm/radeon: drop RADEON_FENCE_SIGNALED_SEQ v2Christian König2014-08-271-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's causing issues with VMID handling and comparing the fence value two times actually doesn't make handling faster. v2: rebased on reset changes Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | drm/radeon: handle lockup in delayed work, v5Christian König2014-08-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v5 (chk): complete rework, start when the first fence is emitted, stop when the last fence is signalled, make it work correctly with GPU resets, cleanup radeon_fence_wait_seq Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | drm/radeon: take exclusive_lock in read mode during ring tests, v5Maarten Lankhorst2014-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed for the next commit, because the lockup detection will need the read lock to run. v4 (chk): split out forced fence completion, remove unrelated changes, add and handle in_reset flag v5 (agd5f): rebase fix Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | drm/radeon: force fence completion only on problematic rings (v2)Christian König2014-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of resetting all fence numbers, only reset the number of the problematic ring. Split out from a patch from Maarten Lankhorst <maarten.lankhorst@canonical.com> v2 (agd5f): rebase build fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | drm/ttm: move fpfn and lpfn into each placement v2Christian König2014-08-271-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | This allows us to more fine grained specify where to place the buffer object. v2: rebased on drm-next, add bochs changes as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| * | Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2014-08-261-0/+18
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next radeon userptr support. * 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: allow userptr write access under certain conditions drm/radeon: add userptr flag to register MMU notifier v3 drm/radeon: add userptr flag to directly validate the BO to GTT drm/radeon: add userptr flag to limit it to anonymous memory v2 drm/radeon: add userptr support v8 Conflicts: drivers/gpu/drm/radeon/radeon_prime.c
| | * | drm/radeon: add userptr flag to register MMU notifier v3Christian König2014-08-111-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whenever userspace mapping related to our userptr change we wait for it to become idle and unmap it from GTT. v2: rebased, fix mutex unlock in error path v3: improve commit message Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | drm/radeon: add userptr support v8Christian König2014-08-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an IOCTL for turning a pointer supplied by userspace into a buffer object. It imposes several restrictions upon the memory being mapped: 1. It must be page aligned (both start/end addresses, i.e ptr and size). 2. It must be normal system memory, not a pointer into another map of IO space (e.g. it must not be a GTT mmapping of another object). 3. The BO is mapped into GTT, so the maximum amount of memory mapped at all times is still the GTT limit. 4. The BO is only mapped readonly for now, so no write support. 5. List of backing pages is only acquired once, so they represent a snapshot of the first use. Exporting and sharing as well as mapping of buffer objects created by this function is forbidden and results in an -EPERM. v2: squash all previous changes into first public version v3: fix tabs, map readonly, don't use MM callback any more v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages, pin/unpin pages on bind/unbind instead of populate/unpopulate v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown flags, better handle READONLY flag, improve permission check v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin v7: add warning about it's availability in the API definition v8: drop access_ok check, fix VM mapping bits Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v4) Reviewed-by: Jérôme Glisse <jglisse@redhat.com> (v4) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | drm/radeon: add a module parameter for backlight control (v2)Alex Deucher2014-09-221-0/+1
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a module parameter to disable the radeon GPU backlight controller to override the automatic detection. Some laptops seems to indicate that they use the integrated controller, but appear to actually use an external controller. bug: https://bugs.freedesktop.org/show_bug.cgi?id=81382 v2: fix module parameter description Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/radeon: save/restore the PD addr on suspend/resumeChristian König2014-08-261-0/+2
|/ / | | | | | | | | | | | | This fixes a problem with GPU resets and TLB flushes on SI/CIK. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: Only flush HDP cache for indirect buffers from userspaceMichel Dänzer2014-08-181-3/+5
| | | | | | | | | | | | | | | | It isn't necessary for command streams generated by the kernel (at least not while we aren't storing ring or indirect buffers in VRAM). Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: add bapm module parameterAlex Deucher2014-08-151-0/+1
|/ | | | | | | | | | | | | Add a module paramter to enable bapm on APUs. It's disabled by default on certain APUs due to stability issues. This option makes it easier to test and to enable it on systems that are stable. bug: https://bugzilla.kernel.org/show_bug.cgi?id=81021 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: Use pflip irqs for pageflip completion if possible. (v2)Mario Kleiner2014-08-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Skip the "manual" pageflip completion checks via polling and guessing in the vblank handler radeon_crtc_handle_vblank() on asics which are known to reliably support hw pageflip completion irqs. Those pflip irqs are a more reliable and race-free method of handling pageflip completion detection, whereas the "classic" polling method has some small races in combination with dpm on, and with the reworked pageflip implementation since Linux 3.16. On old asics without pflip irqs, the classic method is used. On asics with known good pflip irqs, only pflip irqs are used by default, but a new module parameter "use_pflipirqs" allows to override this in case we encounter asics in the wild with unreliable or faulty pflip irqs. A module parameter of 0 allows to use the classic method only in such a case. A parameter of 1 allows to use both classic method and pflip irqs as additional band-aid to avoid some small races which could happen with the classic method alone. The setting 1 gives Linux 3.16 behaviour. Hw pflip irqs are available since R600. Tested on DCE-4, AMD Cedar - FirePro 2270. v2: agd5f: only enable pflip interrupts on DCE4+ as they are not reliable on older asics. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: split PT setup in more functionsChristian König2014-08-051-6/+19
| | | | | | | Move the decision what to use into the common VM code. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use an intervall tree to manage the VMA v2Alex Deucher2014-08-051-4/+3
| | | | | | | | | | Scales much better than scanning the address range linearly. v2: store pfn instead of address Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: invalidate moved BOs in the VM (v2)Christian König2014-08-051-1/+6
| | | | | | | | | | | Don't wait for the BO to be used again, just update the PT on the next VM use. v2: remove stray semicolon. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/atom: add new voltage fetch function for hawaiiAlex Deucher2014-08-051-0/+3
| | | | | | | | Some hawaii boards use a different method for fetching the voltage information from the vbios. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: Always flush the HDP cache before submitting a CS to the GPUMichel Dänzer2014-08-051-0/+1
| | | | | | | | | | | | | This ensures the GPU sees all previous CPU writes to VRAM, which makes it safe: * For userspace to stream data from CPU to GPU via VRAM instead of GTT * For IBs to be stored in VRAM instead of GTT * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush is performed via MMIO Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: s/ioctl_wait_idle/mmio_hpd_flush/Michel Dänzer2014-08-051-7/+2
| | | | | | | And clean up the function comment a little. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fix R600_PTE_GART handlingChristian König2014-08-051-3/+3
| | | | | | | That didn't worked correctly any more and opened up a security problem. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: remove discardable flag from radeon_gem_object_createChristian König2014-08-051-1/+1
| | | | | | | | Unused and unimplemented. Also fix specifying the kernel flag incorrectly at one occasion. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add a PX quirk listAlex Deucher2014-08-051-0/+1
| | | | | | | | | | | | Some PX laptops seems to have problems turning the dGPU on/off. Add a quirk list to disable runpm by default on those systems. Also convert the current PX d3 delay handling to a quirk. bug: https://bugzilla.kernel.org/show_bug.cgi?id=51381 https://bugzilla.kernel.org/show_bug.cgi?id=74551 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: remove visible vram size limit on bo allocation (v4)Alex Deucher2014-08-051-1/+1
| | | | | | | | | | | | | | | | Now that fallback to gtt is fixed for cpu access, we can remove this limit. bug: https://bugs.freedesktop.org/show_bug.cgi?id=78717 v2: use new gart_pin_size to accurately track available gtt. v3: fix comment v4: clarify comment Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* drm/radeon: track pinned memory (v2)Alex Deucher2014-08-051-0/+4
| | | | | | | | | | So we know how large an allocation we can allow. v2: incorporate Michel's comments Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* drm/radeon: Allow write-combined CPU mappings of BOs in GTT (v2)Michel Dänzer2014-08-051-1/+2
| | | | | | | | v2: fix rebase onto drm-fixes Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Pass GART page flags to radeon_gart_set_page() explicitlyMichel Dänzer2014-08-051-3/+9
| | | | | | Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Remove radeon_gart_restore()Michel Dänzer2014-08-051-1/+0
| | | | | | | | Doesn't seem necessary, the GART table memory should be persistent. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Inline r100_mm_rreg, -wreg, v3Lauri Kasanen2014-08-051-4/+36
| | | | | | | | | | | | | | | | | | | | | | | This was originally un-inlined by Andi Kleen in 2011 citing size concerns. Indeed, a first attempt at inlining it grew radeon.ko by 7%. However, 2% of cpu is spent in this function. Simply inlining it gave 1% more fps in Urban Terror. v2: We know the minimum MMIO size. Adding it to the if allows the compiler to optimize the branch out, improving both performance and size. The v2 patch decreases radeon.ko size by 2%. I didn't re-benchmark, but common sense says perf is now more than 1% better. v3: Also change _wreg, make the threshold a define. Inlining _wreg increased the size a bit compared to v2, so now radeon.ko is only 1% smaller. Signed-off-by: Lauri Kasanen <cand@gmx.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: Add support for new ucode format (v5)Alex Deucher2014-08-051-0/+1
| | | | | | | | | | | This adds CIK support for the new ucode format. v2: add size validation, integrate debug info v3: add support for MEC2 on KV v4: fix typos v4: update to latest format Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/si: Add support for new ucode format (v3)Alex Deucher2014-08-051-0/+1
| | | | | | | | | This adds SI support for the new ucode format. v2: add size validation, integrate debug info v3: update to latest version Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add support for SVI2 voltage for SIAlex Deucher2014-08-051-0/+3
| | | | | | | Some newer boards use SVI2 for voltage control rather than GPIO. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fix VM IB handlingChristian König2014-07-211-0/+2
| | | | | | | | Calling radeon_vm_bo_find on the IB BO during CS is illegal and can lead to an crash. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fix handling of radeon_vm_bo_rmv v3Christian König2014-07-211-4/+9
| | | | | | | | | | v3: completely rewritten. We now just remember which areas of the PT to clear and do so on the next command submission. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=79980 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Move pinning the BO back to radeon_crtc_page_flip()Michel Dänzer2014-07-171-2/+1
| | | | | | | | | | | As well as enabling the vblank interrupt. These shouldn't take any significant amount of time, but at least pinning the BO has actually been seen to fail in practice before, in which case we need to let userspace know about it. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use RADEON_MAX_CRTCS, RADEON_MAX_AFMT_BLOCKS (v2)Stefan Brüns2014-07-011-4/+0
| | | | | | | v2: agd5f: compile fix Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add a module parameter to control deep color supportAlex Deucher2014-07-011-0/+1
| | | | | | | | | | | | | | Some monitors seem to have problems with deep color enabled, even though they claim to support it. I'm not sure if the monitor need a quirk or if the driver is doing something the monitor doesn't like. At this point lets just disable deep color by default like we did for hdmi audio and work through the bugs so we can eventually enable it by default. bug: https://bugs.freedesktop.org/show_bug.cgi?id=80531 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add query for number of active CUsAlex Deucher2014-06-091-0/+6
| | | | | | | Query to find out how many compute units on a GPU. Useful for OpenCL usermode drivers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: make vm_block_size a module parameterChristian König2014-06-091-6/+2
| | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: make VM size a module parameter (v2)Christian König2014-06-091-0/+1
| | | | | | | v2: agd5f: simplify patch Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rename alt_domain to allowed_domainsChristian König2014-06-091-2/+2
| | | | | | | | | | And also domain to prefered_domains. That matches better what those values represent. Signed-off-by: Christian König <christian.koenig@amd.com> Cc: Marek Olšák <maraeo@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: remove range check from *_gart_set_pageChristian König2014-06-091-1/+2
| | | | | | | | | We never check the return value anyway and if the index isn't valid would crash way before calling the functions. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-nextDave Airlie2014-06-051-2/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | Merge drm-fixes into drm-next. Both i915 and radeon need this done for later patches. Conflicts: drivers/gpu/drm/drm_crtc_helper.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/i915_gem_execbuffer.c drivers/gpu/drm/i915/i915_gem_gtt.c
| * drm/radeon: fix DCE83 check for mullinsAlex Deucher2014-05-201-1/+2
| | | | | | | | | | | | | | | | Mullins is DCE83 just like Kabini. Set the proper number of endpoints on mullins. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
| * drm/radeon: check VCE relocation buffer range v3Leo Liu2014-05-201-1/+2
| | | | | | | | | | | | | | | | v2 (chk): fix image size storage v3 (chk): fix UV size calculation Signed-off-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
| * drm/radeon: use pflip irq on R600+ v2Christian König2014-05-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing the update pending bit directly after issuing an update is nonsense cause depending on the pixel clock the CRTC needs a bit of time to execute the flip even when we are in the VBLANK period. This is just a non invasive patch to solve the problem at hand, a more complete and cleaner solution should follow in the next merge window. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564 v2: fix source IDs for CRTC2-6 Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
* | drm/radeon: rework page flip handling v4Christian König2014-06-041-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling v4: update crtc->primary->fb when the flip actually happens Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | Revert "drm/radeon: rework page flip handling v3"Dave Airlie2014-06-041-9/+7
| | | | | | | | | | | | This reverts commit 1aab5514ca9604e0263f658a067da0189c86a35b. Apply the fixed up version instead.
* | drm/radeon: add define for flags used in R600+ GTTChristian König2014-06-021-0/+4
| | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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