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* drm/nouveau/falcon: add msgqueue interfaceAlexandre Courbot2017-03-071-0/+47
| | | | | | | | | | | | | | | | A message queue firmware implements a specific protocol allowing the host to send "commands" to a falcon, and the falcon to reply using "messages". This patch implements the common part of this protocol and defines the interface that the host can use. Due to the way the firmware is developped internally at NVIDIA (where kernel driver and firmware evolve in lockstep), firmwares taken at different points in time can have frustratingly subtle differences that must be taken into account. This code is architectured to make implementing such differences as easy as possible. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/falcon: protect against concurrent DMEM accessesAlexandre Courbot2017-03-071-0/+1
| | | | | | | | The falcon library may be used concurrently, especially after the introduction of the msgqueue interface. Make it safe to use it that way. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: make nvkm_secboot_falcon_name visibleAlexandre Courbot2017-03-071-0/+2
| | | | | | | | Make nvkm_secboot_falcon_name publicly visible as other subdevs will need to use it for debug messages. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tmr: provide backtrace when a timeout is hitBen Skeggs2017-02-171-4/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci/g92: Fix rearmKarol Herbst2017-02-171-0/+1
| | | | | | | | | | | 704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs. g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm. Reported-by: Andrew Randrianasulu <randrianasulu@gmail.com> Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
* drm/nouveau/iccsense: Parse max and crit power levelKarol Herbst2017-02-171-0/+3
| | | | | Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/power_budget: Add basic power budget parsingKarol Herbst2017-02-171-0/+26
| | | | | | | | | | | | | v2: Set entry to 0xff if not found Add cap entry for ver 0x30 tables Rework to fix memory leak v3: More error checks Simplify check for invalid entries v4: disable for ver 0x10 for now move assignments after the second last return Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/top: add function to translate subdev index to mmu fault idBen Skeggs2017-02-171-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add engine method to assist in determining chsw directionBen Skeggs2017-02-171-0/+2
| | | | | | | | | FIFO gives us load/save/switch status, and we need to be able to determine which direction a "switch" is failing during channel recovery. In order to do this, we apparently need to query the engine itself. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gf100-: provide notification to user if channel is killedBen Skeggs2017-02-173-0/+3
| | | | | | | | | | | | There are instances (such as non-recoverable GPU page faults) where NVKM decides that a channel's context is no longer viable, and will be removed from the runlist. This commit notifies the owner of the channel when this happens, so it has the opportunity to take some kind of recovery action instead of hanging. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/g84-: rename non-stall interrupt eventBen Skeggs2017-02-174-4/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: increase maximum number of notifies that a client can requestBen Skeggs2017-02-171-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci: Rename g94 to g92Karol Herbst2017-02-171-1/+1
| | | | | Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/memory: distinguish between coherent/non-coherent targetsBen Skeggs2017-02-171-3/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/mm: replace region list with next pointerBen Skeggs2017-02-172-2/+8
| | | | | | | | We never have any need for a double-linked list here, and as there's generally a large number of these objects, replace it with a single- linked list in order to save some memory. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/client: allow creation of subclientsBen Skeggs2017-02-174-3/+14
| | | | | | | | | | | | | | We want a supervisor client of NVKM (such as the DRM) to be able to allow sharing of resources (such as memory objects) between clients. To allow this, the supervisor creates all its clients as children of itself, and will use an upcoming ioctl to permit sharing. Currently it's not possible for indirect clients to use subclients. Supporting this will require an additional field in the main ioctl. This isn't important currently, but will need to be fixed for virt. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/client: pass notification callback to nvkm_client_newBen Skeggs2017-02-171-1/+3
| | | | | | Preparation for supporting subclients. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/client: use standard object dtor/init/fini pathsBen Skeggs2017-02-171-3/+0
| | | | | | Preparation for supporting subclients, and also good for consistency. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/client: modify prefix on nvif structures, for consistencyBen Skeggs2017-02-173-9/+14
| | | | | | Preparation for supporting subclients. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dma: lookup objects with nvkm_object_search()Ben Skeggs2017-02-172-6/+1
| | | | | | Custom code is no longer needed here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/client: lookup client objects with nvkm_object_search()Ben Skeggs2017-02-171-4/+0
| | | | | | Custom code is no longer needed here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core/object: support lookup of specific object typesBen Skeggs2017-02-171-0/+5
| | | | | | | | | | It turns out we have a nice and convenient way of looking up a specific object type already, by using the func pointer as a key. This will be used to remove the separate object trees for each type we need to be able to search for. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/nv50-mcp89: add defines for gr classesBen Skeggs2017-02-171-0/+12
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: split reset functionAlexandre Courbot2017-02-171-0/+5
| | | | | | | Split the reset function into more meaningful and reusable ones. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: reorganize into more filesAlexandre Courbot2017-02-171-5/+4
| | | | | | | | | | | | | | | | | | | | | | | Split the act of building the ACR blob from firmware files from the rest of the (chip-dependent) secure boot logic. ACR logic is moved into acr_rxxx.c files, where rxxx corresponds to the compatible release of the NVIDIA driver. At the moment r352 and r361 are supported since firmwares have been released for these versions. Some abstractions are added on top of r352 so r361 can easily be implemented on top of it by just overriding a few hooks. This split makes it possible and easy to reuse the same ACR version on different chips. It also hopefully makes the code much more readable as the different secure boot logics are separated. As more chips and firmware versions will be supported, this is a necessity to not get lost in code that is already quite complex. This is a big commit, but it essentially moves things around (and split the nvkm_secboot structure into two, nvkm_secboot and nvkm_acr). Code semantics should not be affected. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: remove nvkm_secboot_start()Alexandre Courbot2017-02-171-1/+0
| | | | | | | | Since GR has moved to using the falcon library to start the falcons, this function is not needed anymore. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: use falcon libraryAlexandre Courbot2017-02-171-3/+1
| | | | | | | | | Use the falcon library functions in secure boot. This removes a lot of code and makes the secure boot flow easier to understand as no register is directly accessed. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot: fix functions definitionsAlexandre Courbot2017-02-171-3/+3
| | | | | | | These functions should use the nvkm_secboot_falcon enum. Fix this. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gm20b: add dummy PMU deviceAlexandre Courbot2017-02-171-0/+1
| | | | | | | | | | | | | | Add a dummy PMU device so the PMU falcon is instanciated and can be used by secure boot. We could reuse gk20a's implementation here, but it would fight with secboot over PMU falcon's ownership and secboot will reset the PMU, preventing it from operating afterwards. Proper handout between secboot and pmu is coming along with the actual gm20b PMU implementation, so use this as a temporary solution. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu: instanciate the falcon in PMU deviceAlexandre Courbot2017-02-171-0/+2
| | | | | | | | Have an instance of nvkm_falcon in the PMU structure, ready to be used by other subdevs (i.e. secboot). Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add falcon library functionsAlexandre Courbot2017-02-171-4/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Falcon processors are used in various places of GPU chips. Although there exist different versions of the falcon, and some variants exist, the base set of actions performed on them is the same, which results in lots of duplicated code. This patch consolidates the current nvkm_falcon structure and extends it with the following features: * Ability for an engine to obtain and later release a given falcon, * Abstractions for basic operations (IMEM/DMEM access, start, etc) * Abstractions for secure operations if a falcon is secure Abstractions make it easy to e.g. start a falcon, without having to care about its details. For instance, falcons in secure mode need to be started by writing to a different register. Right now the abstractions variants only cover secure vs. non-secure falcon, but more will come as e.g. SEC2 support is added. This is still a WIP as other functions previously done by engine/falcon.c need to be reimplemented. However this first step allows to keep things simple and to discuss basic design. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: add nvkm_mc_enabled() functionAlexandre Courbot2017-02-171-0/+1
| | | | | | | | Add a function that allows us to query whether a given subdev is currently enabled or not. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: constify nv*_printk macrosAlexandre Courbot2017-02-173-4/+4
| | | | | | | | Constify the local variables declared in these macros so we can pass const pointers to them. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/volt: pointers are 32-bitBen Skeggs2016-11-281-4/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/vmap: pointers are 32-bitBen Skeggs2016-11-281-4/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/timing: pointers are 32-bitBen Skeggs2016-11-281-3/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/perf: pointers are 32-bitBen Skeggs2016-11-281-3/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/fan: pointers are 32-bitBen Skeggs2016-11-281-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/cstep: pointers are 32-bitBen Skeggs2016-11-281-6/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/boost: pointers are 32-bitBen Skeggs2016-11-281-6/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/gp102: rename from gp104Ben Skeggs2016-11-172-3/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ce/gp102: rename from gp104Ben Skeggs2016-11-171-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gp102: rename from gp104Ben Skeggs2016-11-171-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu/gp102: initial implementationBen Skeggs2016-11-171-0/+1
| | | | | | | GP102/GP104 require a harder reset of PMU prior to DEVINIT, or the IFR image will hang. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu/gp100: initial implementationBen Skeggs2016-11-171-0/+1
| | | | | | Just enough to hookup preinit reset(), which DEVINIT will depend on later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/sor/gf119-: add method to program mst payload informationBen Skeggs2016-11-071-0/+10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/sor/gf119-: add method to control mst enableBen Skeggs2016-11-071-0/+7
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: helper to match against supported class listBen Skeggs2016-11-071-0/+29
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: silence sparse warnings about symbols not being marked staticBen Skeggs2016-11-071-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb: add gm20b deviceAlexandre Courbot2016-11-071-0/+1
| | | | | | | | | | gm20b's FB has the same capabilities as gm200, minus the ability to allocate RAM. Create a device that reflects this instead of re-using the gk20a device which may be incorrect. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-By: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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