summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/include/nvkm/subdev
Commit message (Collapse)AuthorAgeFilesLines
...
* drm/nouveau/top: initial implementationBen Skeggs2016-05-201-0/+7
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add top plumbingBen Skeggs2016-05-201-0/+8
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/iccsense: split sensor into own structKarol Herbst2016-05-201-0/+1
| | | | | | | | v2: add list_del call, reword error message Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/iccsense: convert to linked listKarol Herbst2016-05-201-3/+1
| | | | | | | | v2: add list_del calls Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/iccsense: remove read functionKarol Herbst2016-05-201-1/+0
| | | | | | Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/devinit/gf100: make devinit on resume saferAlexandre Courbot2016-05-201-0/+1
| | | | | | | | | | | | | | | | | | In case of successful suspend, devinit will have to be run and this is the behavior currently hardcoded. However, as FD bug 94725 suggests, there might be cases where runtime suspend leaves the GPU powered, and in such cases devinit should not be run on resume. On GF100+ we have a reliable way to know whether we need to run devinit. Use it instead of blindly trusting the flag set by nvkm_devinit_fini(). The code around the NvForcePost also needs to be slightly reworked in order to keep working. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Suggested-by: Dave Airlie <airlied@redhat.com> Suggested-by: Karol Herbst <nouveau@karolherbst.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/clk/gm20b: add basic driverAlexandre Courbot2016-03-141-0/+1
| | | | | | | Add a basic clock driver that reuses the GK20A logic. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/volt: add GM20B driverAlexandre Courbot2016-03-141-0/+1
| | | | | | | Add basic GM20B volt driver that reuses the GK20A logic. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/iccsense: implement for ina209, ina219 and ina3221Karol Herbst2016-03-143-0/+41
| | | | | | | | | | | | | based on Martins initial work v3: fix ina2x9 calculations v4: don't kmalloc(0), fix the lsb/pga stuff v5: add a field to tell if the power reading may be invalid add nkvm_iccsense_read_all function check for the device on the i2c bus Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/nvbios/iccsense: add parsing of the SENSE tableMartin Peres2016-03-141-0/+16
| | | | | | | | | Karol Herbst: v4: don't kmalloc(0) v5: stricter validation Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/subdev/iccsense: add new subdev for power sensorsMartin Peres2016-03-141-0/+10
| | | | | Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/secboot/gm20b: add secure boot supportAlexandre Courbot2016-03-141-0/+1
| | | | | | | | | | | | Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot/gm200: add secure-boot supportAlexandre Courbot2016-03-141-0/+2
| | | | | | | | | | | | | Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. v2. use proper memory target function Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add support for secure bootAlexandre Courbot2016-03-141-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | On GM200 and later GPUs, firmware for some essential falcons (notably GR ones) must be authenticated by a NVIDIA-produced signature and loaded by a high-secure falcon in order to be able to access privileged registers, in a process known as Secure Boot. Secure Boot requires building a binary blob containing the firmwares and signatures of the falcons to be loaded. This blob is then given to a high-secure falcon running a signed loader firmware that copies the blob into a write-protected region, checks that the signatures are valid, and finally loads the verified firmware into the managed falcons and switches them to privileged mode. This patch adds infrastructure code to support this process on chips that require it. v2: - The IRQ mask of the PMU falcon was left - replace it with the proper irq_mask variable. - The falcon reset procedure expecting a falcon in an initialized state, which was accidentally provided by the PMU subdev. Make sure that secboot can manage the falcon on its own. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: s/gm204/gm200/ in a number of placesBen Skeggs2016-03-144-4/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/perf: add fields for pci speed and width and use it for the pstatesKarol Herbst2016-01-111-0/+3
| | | | Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/bios/perf: parse the pci speed from the bios for tesla and newer ↵Karol Herbst2016-01-111-0/+2
| | | | | | cards Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/pci: implement generic code for pcie speed changeKarol Herbst2016-01-111-0/+14
| | | | | | | | | | | | v2: rename and group functions v4: change copyright information move printing of pcie speeds into oneinit, rename all pcie functions to nvkm_pcie_* don't try to raise the pcie version when no higher one is supported v5: revert Copyright changes and rename nvkm_pcie_raise_version to nvkm_pcie_set_version v6: remove some useless pci_is_pcie checks and rework messages Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/pci: add gk104 variantKarol Herbst2016-01-111-0/+1
| | | | | | | | v2: change email used in header v4: change Copyright information v5: revert Copyright changes Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/pci: add gf106 variantKarol Herbst2016-01-111-0/+1
| | | | | | | | v2: change email used in header v4: change Copyright information v5: revert Copyright changes Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/clk: remove references to "daemon"Ben Skeggs2016-01-111-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc/gm204: split implementation from gm107Ben Skeggs2016-01-111-0/+1
| | | | | | | | Differences from GM10x: - GM20x LTC count detection differs from GM10x - GM20x init doesn't require large page size setting Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ibus/gm204: split implementation from gk104Ben Skeggs2016-01-111-0/+1
| | | | | | GM20x doesn't require the priv ring timeout bumps that GK/GM10x have. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/instmem: protect instobj list with a spinlockBen Skeggs2015-11-251-0/+1
| | | | | | | | | No locking is required for the traversal of this list, as it only happens during suspend/resume where nothing else can be executing. Fixes some of the issues noticed during parallel piglit runs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristicRoy Spliet2015-11-031-0/+1
| | | | | | | | | Avoids waiting for VBLANKS that never arrive on headless or otherwise unconventional set-ups. Strategy taken from MEMX. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for itRoy Spliet2015-11-031-0/+1
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/rammap: Identify DLLoff for >= GF100Roy Spliet2015-11-031-1/+0
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci: Handle 5-bit and 8-bit tag fieldPierre Moreau2015-11-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the hardware supports extended tag field (8-bit ones), then enable it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible number of requests to 32. Apparently bits 7:0 of 0x08841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 v2: Restrict changes to chipsets >= 0x84 v3: * Add nvkm_pci_mask to pci.h * Mask bit 8 before setting it v4: * Rename `add` argument of nvkm_pci_mask to `value` * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset checks v5: * Rebase code on latest PCI structure * Restore PCIe check * Fix namings in nvkm_pci_mask * Rephrase part of the commit message Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: remove unused functionSudip Mukherjee2015-11-031-2/+0
| | | | | | | | | | coverity.com reported that memset was using a buffer of size 0, on checking the code it turned out that the function was not being used. So remove it. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by defaultBen Skeggs2015-11-031-1/+1
| | | | | | | | Was not able to obtain a trace of NVRM due to kernel version annoyances, however, experimentally confirmed that the WAR we use on NV50/G8x boards works here too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci/g94: split implementation from nv40Ben Skeggs2015-11-031-0/+1
| | | | | | | An upcoming patch will implement functionality that we don't use on any NV40 chipset. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci/g84: split implementation from nv50Ben Skeggs2015-11-031-0/+1
| | | | | | | An upcoming patch will implement functionality that we don't use on the original NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ibus/gf100: increase wait timeout to avoid read faultsSamuel Pitoiset2015-11-031-0/+1
| | | | | | | | | | | | Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/volt/gk104: add support for pwm and gpio modesMartin Peres2015-11-032-0/+2
| | | | | | | | | | | | | Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/bios/volt: add support for pwm-based volt managementMartin Peres2015-11-031-1/+14
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc/gf100: add flush/invalidate functionsAlexandre Courbot2015-11-031-0/+1
| | | | | | | | Allow clients to manually flush and invalidate L2. This will be useful for Tegra systems for which we want to write instmem using the CPU. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc: add hooks for invalidate and flushAlexandre Courbot2015-11-031-0/+3
| | | | | | | | These are useful for systems without a coherent CPU/GPU bus. For such systems we may need to maintain the L2 ourselves. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/timer: re-introduce nvkm_wait_xsec macrosAlexandre Courbot2015-11-031-0/+10
| | | | | | | | | Reintroduce macros allowing us to test a register against a certain mask, since this is the most common usage pattern for the more generic nvkm_xsec macros and makes the code more concise and readable. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci: merge agp handling from nouveau drmBen Skeggs2015-08-281-0/+11
| | | | | | | This commit reinstates the pre-DEVINIT AGP fiddling that was broken in an earlier commit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: move device irq handling to platform-specific codeBen Skeggs2015-08-282-9/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: abstract interface to master intr registersBen Skeggs2015-08-281-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci: new subdevBen Skeggs2015-08-281-0/+21
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: remove the remainder of the previous styleBen Skeggs2015-08-281-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/volt: convert to new-style nvkm_subdevBen Skeggs2015-08-281-41/+5
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tmr: convert to new-style nvkm_subdevBen Skeggs2015-08-281-35/+19
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/therm: convert to new-style nvkm_subdevBen Skeggs2015-08-281-42/+62
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu: convert to new-style nvkm_subdevBen Skeggs2015-08-281-16/+13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mxm: convert to new-style nvkm_subdevBen Skeggs2015-08-281-29/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mmu: convert to new-style nvkm_subdevBen Skeggs2015-08-281-56/+15
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: convert to new-style nvkm_subdevBen Skeggs2015-08-281-17/+14
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
OpenPOWER on IntegriCloud