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* drm/i915/skl: Double RC6 WRL always onMika Kuoppala2015-12-081-2/+1
| | | | | | | | | | | | | WaRsDoubleRc6WrlWithCoarsePowerGating should be enabled for all Skylakes. Make it so. Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449505785-20812-2-git-send-email-mika.kuoppala@intel.com (cherry picked from commit e7674b8c31717dd0c58b3a9493d43249722071eb) Cc: stable@vger.kernel.org # v4.3+ Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915/skl: Disable coarse power gating up until F0Mika Kuoppala2015-12-081-1/+1
| | | | | | | | | | | | | | | | | | There is conflicting info between E0 and F0 steppings for this workarounds. Trust more authoritative source and be conservative and extend also for F0. This prevents numerous (>50) gpu hangs with SKL GT4e during piglit run. References: HSD: gen9lp/2134184 Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449505785-20812-1-git-send-email-mika.kuoppala@intel.com (cherry picked from commit 6686ece19f7446f0e29c77d9e0402e1d0ce10c48) Cc: stable@vger.kernel.org # v4.3+ Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: Fix gpu frequency change tracingMika Kuoppala2015-11-181-1/+1
| | | | | | | | | | | | | | | | | With gen < 9 we have had always 50Mhz units as our hw ratio. With gen >= 9 the hw ratio changed to 16.667Mhz (50/3). The result was that our gpu frequency tracing started to output values 3 times larger than expected due to hardcoded scaling value. Fix this by using Use intel_gpu_freq() when generating Mhz value from ratio for 'intel_gpu_freq_change' trace event. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92591 Cc: stable@vger.kernel.org # v4.3+ Reported-by: Eero Tamminen <eero.t.tamminen@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447776866-29384-1-git-send-email-mika.kuoppala@intel.com
* drm/i915: Fix GT frequency roundingMika Kuoppala2015-11-161-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we set and later readback a frequency value through sysfs interface, igt/pm_rpm assumes that we get same value back if it matches hw granularity. On bxt we have found out that this is not always the case. Currently frequency - hw ratio - frequency conversions round down, with few exceptions on platforms that have more specific conversions. On bxt the supported range can be for example from 100Mhz to 650Mhz. Midpoint is then calculated by test to be 375 which pm_rps uses to find a closest hw supported frequency. That is 366 (ratio 22), which it then writes back. But as the rounding down kicks in, driver actually sets 350 instead of 366, as 366 is 2/3 below 22 * 50/3. Fix this by rounding to closest instead of rounding down in freq-ratio-freq conversions. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92768 Testcase: igt/pm_rps/basic-api Tested-by: Bob Paauwe <bob.j.paauwe@intel.com> Cc: Bob Paauwe <bob.j.paauwe@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447435781-23416-1-git-send-email-mika.kuoppala@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915/skl: Prevent unclaimed register writes on skylake.Maarten Lankhorst2015-11-021-0/+5
| | | | | | | | | | | | | I'm getting unclaimed register writes when checking the WM registers after the crtc is disabled. So I would imagine those are guarded by the crtc power well. Fix this by not reading out wm state when the power well is off. Cc: stable@vger.kernel.org # v4.3 Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181 Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: Fix maxfifo watermark calc on vlv cursor planesThomas Daniel2015-10-271-1/+1
| | | | | | | | | | A typo resulted in the watermarks for cursor planes not being calculated correctly. Fixed the typo. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* drm/i915: Move skl/bxt gt specific workarounds to ring initMika Kuoppala2015-10-131-60/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some registers are, naturally, lost in gpu reset/suspend cycle. And some registers, for example in display domain, are not subject to gpu reset so they retain their contents. As hang recovery triggers a reset, recoverable gpu hang can currently flush out essential workarounds and cause havoc later on. When register GEN8_GARBNTL is missing the WaEnableGapsTsvCreditFix:skl, it can cause random system hangs [1]. This workaround was added in: commit 245d96670d26 ("drm/i915:skl: Add WaEnableGapsTsvCreditFix") But another set of system hangs were observed and the failure pattern indicated that there was random gpu hang preceding the system hang [2]. This lead to the realization that we lose this workaround and BDW_SCRATCH1 on reset. Add these workarounds setup in display init to skl/bxt ring init where LRI workarounds are also setup. This way their setup is not dependent on display side init. References: [1] https://bugs.freedesktop.org/show_bug.cgi?id=90854 References: [2] https://bugs.freedesktop.org/show_bug.cgi?id=92315 Reported-by: Tomi Sarvela <tomix.p.sarvela@intel.com> Cc: Tomi Sarvela <tomix.p.sarvela@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Tomi Sarvela <tomix.p.sarvela@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: revert a few more watermark commitsPaulo Zanoni2015-10-131-163/+256
| | | | | | | | | | | | | | | | | | | | | | | This is a squash of the following commits: Revert "drm/i915: Drop intel_update_sprite_watermarks" This reverts commit 47c99438b52d12df50e182583634a4cfede3c920. Revert "drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a to atomic check" This reverts commit 7809e5ae35b9d8d0710f0874b2e3f10be144e38b. Revert "drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3)" This reverts commit 3a05f5e2e78eab7ffe816abb59b6769e331a1957. With these reverts, SKL finally stops failing every single FBC test with FIFO underrun error messages. After some brief testing, it also seems that this commit prevents the machine from completely freezing when we run igt/kms_fbc_crc (see fd.o #92355). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92355 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Partial revert of atomic watermark seriesMatt Roper2015-10-091-103/+129
| | | | | | | | | | | | | | | | | | | It's been reported that the atomic watermark series triggers some regressions on SKL, which we haven't been able to track down yet. Let's temporarily revert these patches while we track down the root cause. This commit squashes the reverts of: 76305b1 drm/i915: Calculate watermark configuration during atomic check (v2) a4611e4 drm/i915: Don't set plane visible during HW readout if CRTC is off a28170f drm/i915: Calculate ILK-style watermarks during atomic check (v3) de4a9f8 drm/i915: Calculate pipe watermarks into CRTC state (v3) de165e0 drm/i915: Refactor ilk_update_wm (v3) Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077190.html Cc: "Zanoni, Paulo R" <paulo.r.zanoni@intel.com> Cc: "Vetter, Daniel" <daniel.vetter@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/chv: remove pre-production hardware workaroundsJani Nikula2015-10-071-34/+22
| | | | | | | Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Appease gcc and remove the unused variable.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Update Promotion timer for RC6 TO ModeSagar Arun Kamble2015-10-061-4/+6
| | | | | | | | | | | | | | When using RC6 timeout mode, the timeout value should be written to GEN6_RC6_THRESHOLD. v2: Updated commit message. (Tom) v3: Rebase over whitespace differences. (Daniel) Cc: Tom O'Rourke <Tom.O'Rourke@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Calculate watermark configuration during atomic check (v2)Matt Roper2015-09-301-52/+12
| | | | | | | | | v2: Don't forget to actually check the cstate->active value when tallying up the number of active CRTC's. (Ander) Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Calculate ILK-style watermarks during atomic check (v3)Matt Roper2015-09-301-45/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calculate pipe watermarks during atomic calculation phase, based on the contents of the atomic transaction's state structure. We still program the watermarks at the same time we did before, but the computation now happens much earlier. While this patch isn't too exciting by itself, it paves the way for future patches. The eventual goal (which will be realized in future patches in this series) is to calculate multiple sets up watermark values up front, and then program them at different times (pre- vs post-vblank) on the platforms that need a two-step watermark update. While we're at it, s/intel_compute_pipe_wm/ilk_compute_pipe_wm/ since this function only applies to ILK-style watermarks and we have a completely different function for SKL-style watermarks. Note that the original code had a memcmp() in ilk_update_wm() to avoid calling ilk_program_watermarks() if the watermarks hadn't changed. This memcmp vanishes here, which means we may do some unnecessary result generation and merging in cases where watermarks didn't change, but the lower-level function ilk_write_wm_values already makes sure that we don't actually try to program the watermark registers again. v2: Squash a few commits from the original series together; no longer leave pre-calculated wm's in a separate temporary structure since it's easier to follow the logic if we just cut over to using the pre-calculated values directly. v3: - Pass intel_crtc instead of drm_crtc to .compute_pipe_wm() entrypoint and use intel_atomic_get_crtc_state() to avoid need for extra casting. (Ander) - Drop unused intel_check_crtc() function prototype. (Ander) Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Calculate pipe watermarks into CRTC state (v3)Matt Roper2015-09-301-17/+27
| | | | | | | | | | | | | | | | | | | A future patch will calculate these during the atomic 'check' phase rather than at WM programming time, so let's store the watermark values we're planning to use in the CRTC state; the values actually active on the hardware remains in intel_crtc. While we're at it, do some minor restructuring to keep ILK and SKL values in a union. v2: Don't move cxsr_allowed to state (Maarten) v3: Only calculate watermarks in state. Still keep active watermarks in intel_crtc itself. (Ville) Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Refactor ilk_update_wm (v3)Ville Syrjälä2015-09-301-29/+35
| | | | | | | | | | | | | | Split ilk_update_wm() into two parts; one doing the programming and the other the calculations. v2: Fix typo in commit message v3 (by Matt): Heavily rebased for current codebase. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Drop intel_update_sprite_watermarksMatt Roper2015-09-301-58/+0
| | | | | | | | | | | | | | | | The only platform that still has an update_sprite_wm entrypoint is SKL; on SKL, intel_update_sprite_watermarks just updates intel_plane->wm and then performs a regular watermark update. However intel_plane->wm is only used to update a couple fields in intel_wm_config, and those fields are never used by the SKL code, so on SKL an update_sprite_wm is effectively identical to an update_wm call. Since we're already ensuring that the regular intel_update_wm is called any time we'd try to call intel_update_sprite_watermarks, the whole call is redundant and can be dropped. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a to atomic checkMatt Roper2015-09-301-23/+12
| | | | | | | | | | | | | | | Determine whether we need to apply this workaround at atomic check time and just set a flag that will be used by the main watermark update routine. Moving this workaround into the atomic framework reduces ilk_update_sprite_wm() to just a standard watermark update, so drop it completely and just ensure that ilk_update_wm() is called whenever a sprite plane is updated in a way that would affect watermarks. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3)Matt Roper2015-09-301-175/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | Just pull the info out of the state structures rather than staging it in an additional set of structures. To make this more straightforward, we change the signature of several internal WM functions to take the crtc state as a parameter. v2: - Don't forget to skip cursor planes on a loop in the DDB allocation function to match original behavior. (Ander) - Change a use of intel_crtc->active to cstate->active. They should be identical, but it's better to be consistent. (Ander) - Rework more function signatures to pass states rather than crtc for consistency. (Ander) v3: - Add missing "+ 1" to skl_wm_plane_id()'s 'overlay' case. (Maarten) - Packed formats should pass '0' to drm_format_plane_cpp(), not 1. (Maarten) - Drop unwanted WARN_ON() for disabled planes when calculating data rate for SKL. (Maarten) Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/skl: Simplify wm structures slightly (v2)Matt Roper2015-09-301-45/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A bunch of SKL watermark-related structures have the cursor plane as a separate entry from the rest of the planes. Since a previous patch updated I915_MAX_PLANES such that those plane arrays now have a slot for the cursor, update the code to use the new slot in the existing plane arrays and kill off the cursor-specific structures. There shouldn't be any functional change here; this is just shuffling around how the data is stored in some of the data structures. The whole patch is generated with Coccinelle via the following semantic patch: @@ struct skl_pipe_wm_parameters WMP; @@ - WMP.cursor + WMP.plane[PLANE_CURSOR] @@ struct skl_pipe_wm_parameters *WMP; @@ - WMP->cursor + WMP->plane[PLANE_CURSOR] @@ @@ struct skl_pipe_wm_parameters { ... - struct intel_plane_wm_parameters cursor; ... }; @@ struct skl_ddb_allocation DDB; expression E; @@ - DDB.cursor[E] + DDB.plane[E][PLANE_CURSOR] @@ struct skl_ddb_allocation *DDB; expression E; @@ - DDB->cursor[E] + DDB->plane[E][PLANE_CURSOR] @@ @@ struct skl_ddb_allocation { ... - struct skl_ddb_entry cursor[I915_MAX_PIPES]; ... }; @@ struct skl_wm_values WMV; expression E1, E2; @@ ( - WMV.cursor[E1][E2] + WMV.plane[E1][PLANE_CURSOR][E2] | - WMV.cursor_trans[E1] + WMV.plane_trans[E1][PLANE_CURSOR] ) @@ struct skl_wm_values *WMV; expression E1, E2; @@ ( - WMV->cursor[E1][E2] + WMV->plane[E1][PLANE_CURSOR][E2] | - WMV->cursor_trans[E1] + WMV->plane_trans[E1][PLANE_CURSOR] ) @@ @@ struct skl_wm_values { ... - uint32_t cursor[I915_MAX_PIPES][8]; ... - uint32_t cursor_trans[I915_MAX_PIPES]; ... }; @@ struct skl_wm_level WML; @@ ( - WML.cursor_en + WML.plane_en[PLANE_CURSOR] | - WML.cursor_res_b + WML.plane_res_b[PLANE_CURSOR] | - WML.cursor_res_l + WML.plane_res_l[PLANE_CURSOR] ) @@ struct skl_wm_level *WML; @@ ( - WML->cursor_en + WML->plane_en[PLANE_CURSOR] | - WML->cursor_res_b + WML->plane_res_b[PLANE_CURSOR] | - WML->cursor_res_l + WML->plane_res_l[PLANE_CURSOR] ) @@ @@ struct skl_wm_level { ... - bool cursor_en; ... - uint16_t cursor_res_b; - uint8_t cursor_res_l; ... }; v2: Use a PLANE_CURSOR enum entry rather than making the code reference I915_MAX_PLANES or I915_MAX_PLANES+1, which was confusing. (Ander) Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Eliminate usage of pipe_wm_parameters from ILK-style WM (v2)Matt Roper2015-09-301-55/+29
| | | | | | | | | | | | | | | | | | | Just pull the info out of the CRTC state structure rather than staging it in an additional structure. Note that we use cstate->active rather than intel_crtc->active which may appear to be a change in behavior. However since we're no longer trying to recalculate watermarks during the "pipe off" stage of a modeset, intel_crtc->active and cstate->active should always be identical when watermarks are calculated (at least for ILK-style platforms). v2: Clarify reasoning for cstate->active and add a WARN_ON to the code to assert that it really is always identical to intel_crtc->active as expected. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2)Matt Roper2015-09-301-63/+70
| | | | | | | | | | | | | Just pull the info out of the plane state structure rather than staging it in an additional structure. v2: Add 'visible' condition to sprites_scaled so that we don't limit the WM level when the sprite isn't enabled. (Ville) Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by(v1): Ander Conselvan de Oliveira <conselvan2@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: s/_TRANSA_CHICKEN/TRANS_CHICKEN(PIPE_A)/Ville Syrjälä2015-09-301-2/+2
| | | | | | Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Read czclk from CCK on vlv/chvVille Syrjälä2015-09-301-20/+5
| | | | | | | | | | | | | | | | As with the cdclk, read out czclk from CCK as well. This gives us the real current value and avoids having to decode fuses and whatnot. Also store it in kHz under dev_priv like we do for cdlck since it's not just an rps related clock, and having it in kHz is more standard/convenient for some things. Imre also pointed out that we currently fail to read czclk on VLV, which means the PFI credit programming isn't working as expected. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/skl: Remove WaDisableVFUnitClockGatingArun Siluvery2015-09-301-6/+0
| | | | | | | | | | Dropping it because it is for pre-production stepping, also removed bit definition in i915_reg.h as it is not used anywhere else. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Keep #define as Ville suggested.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/skl: Remove WaSetGAPSunitClckGateDisableArun Siluvery2015-09-301-6/+0
| | | | | | | | | | Dropping it because it is for pre-production stepping, also removed bit definition in i915_reg as it is not used anywhere else. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Keep define as Ville suggested.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/skl: Remove WaDisableSDEUnitClockGatingArun Siluvery2015-09-301-3/+1
| | | | | | | | Dropping it because it is for pre-production stepping. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/bxt: Add WaStoreMultiplePTEenable nameArun Siluvery2015-09-301-6/+3
| | | | | | | | Updated WA with the name. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Constify adjusted_modeVille Syrjälä2015-09-301-6/+3
| | | | | | | | | | | Make adjusted_mode const whereever we don't have to modify it. This only covers cases when we have a local adjusted_mode variable, and doesn't make any difference for cases where we just dereference pipe_config->adjusted_mode. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915: Always call the adjusted mode 'adjusted_mode'Ville Syrjälä2015-09-301-8/+6
| | | | | | | | | | | | | | | | | | | | | | | Always name any variable pointing at the adjusted mode as 'adjustead_mode'. This will make it much easier to identify when we should use the crtc_ timings and when we shoudln't. Conversion was performed with coccinelle: @@ expression E; identifier I; @@ - struct drm_display_mode *I = &E.adjusted_mode; + struct drm_display_mode *adjusted_mode = &E.adjusted_mode; <... - I + adjusted_mode ...> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> [danvet: Fixup conflicts.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* Merge remote-tracking branch 'airlied/drm-next' into drm-intel-nextDaniel Vetter2015-09-301-13/+29
|\ | | | | | | | | | | | | Backmerge to catch up with 4.3. slightly more involved conflict in the irq code, but nothing beyond adjacent changes. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
| * drm/i915: Don't try to use DDR DVFS on CHV when disabled in the BIOSVille Syrjälä2015-09-101-13/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If one disables DDR DVFS in the BIOS, Punit will apparently ignores all DDR DVFS request. Currently we assume that DDR DVFS is always operational, which leads to errors in dmesg when the DDR DVFS requests time out. Fix the problem by gently prodding Punit during driver load to find out whether it will respond to DDR DVFS requests. If the request times out, we assume that DDR DVFS has been permanenly disabled in the BIOS and no longer perster the Punit about it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91629 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Tested-by: Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
* | drm/i915: Replace raw numbers with the approproate register name in ILK ↵Ville Syrjälä2015-09-231-3/+3
| | | | | | | | | | | | | | | | turbo code Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Parametrize ILK turbo registersVille Syrjälä2015-09-231-7/+7
| | | | | | | | | | | | Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Program GuC MAX IDLE CountSagar Arun Kamble2015-09-231-0/+4
| | | | | | | | | | | | | | | | | | Cc: Alex Dai <yu.dai@intel.com> Cc: Tom O'Rourke <Tom.O'Rourke@intel.com> Cc: Akash Goel <akash.goel@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: WaRsDoubleRc6WrlWithCoarsePowerGatingSagar Arun Kamble2015-09-231-1/+7
| | | | | | | | | | | | | | | | | | Cc: Tom O'Rourke <Tom.O'Rourke@intel.com> Cc: Akash Goel <akash.goel@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Alex Dai <yu.dai@intel.com> [danvet: Fix continuation alignment.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: WaRsUseTimeoutModeSagar Arun Kamble2015-09-231-3/+10
| | | | | | | | | | | | | | | | | | | | | | Enable TO mode for RC6 for SKL till D0 and BXT till A0. Cc: Tom O'Rourke <Tom.O'Rourke@intel.com> Cc: Akash Goel <akash.goel@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Alex Dai <yu.dai@intel.com> [danvet: Fixup line continuation alignment.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: WaRsDisableCoarsePowerGatingSagar Arun Kamble2015-09-231-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0. v2: Added GT3/GT4 Check. Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Alex Dai <yu.dai@intel.com> [danvet: Align continuation properly.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915/bxt: WaGsvDisableTurboSagar Arun Kamble2015-09-231-0/+10
| | | | | | | | | | | | | | | | | | Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD exit. Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed by: Alex Dai <yu.dai@intel.com>. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915/skl: Don't clear all watermarks when updating. (v2)Bob Paauwe2015-09-221-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clearing the watermarks for all pipes/planes when updating the watermarks for a single CRTC change seems like the wrong thing to do here. As is, this code will ony update any pipe/plane watermarks that need updating and leave the remaining set to zero. Later, the watermark checks in check_wm_state() will flag these zero'd out pipe/plane watermarks and throw errors. By clearing only the watermark values associated with the specific crtc the other watermark values may remain unchanged. v2: Make sure all the dirty flags are cleared. Damien Clear all values assoicated with crtc/pipe being updated. Damien Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915/bxt: Add WaSetClckGatingDisableMediaArun Siluvery2015-09-141-0/+6
| | | | | | | | | | | | Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915/bxt: Clean up bxt_init_clock_gatingNick Hoath2015-09-071-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add stepping check for A0 workarounds, and remove the associated FIXME tags. Split out unrelated WAs for later condition checking. v2: Fixed format (PeterL) v3: Corrected stepping check for WaDisableSDEUnitClockGating - Ignoring comment, following hardware spec instead. (ChrisH) Added description for TILECTL setting (JonB) Cc: Peter Lawthers <peter.lawthers@intel.com> Cc: Chris Harris <chris.harris@intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: use the yesno helper for loggingJani Nikula2015-09-041-2/+2
| | | | | | | | | | | | Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915/skl: Avoid using un-initialized bits_per_pixelKumar, Mahesh2015-09-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | Don't rely on fb->bits_per_pixel as intel_framebuffer_init is not filling bits_per_pixel field of fb-struct for YUV pixel format. This leads to divide by zero error during watermark calculation. Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com> Cc: Konduru, Chandra <chandra.konduru@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/i915: Add HAS_PCH_LPT_LP() macroVille Syrjälä2015-09-021-2/+2
|/ | | | | | | | | Make LPT:LP checks look neater by wrapping the details in a new HAS_PCH_LPT_LP() macro. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* Merge tag 'topic/drm-misc-2015-07-28' into drm-intel-next-queuedDaniel Vetter2015-08-061-1/+1
|\ | | | | | | | | | | | | We need a few core drm patches to be able to merge Maarten's series to convert DPMS over to atomic. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
| * drm: Simplify drm_for_each_legacy_plane argumentsDaniel Vetter2015-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | No need to pass the planelist when everyone just uses dev->mode_config.plane_list anyway. I want to add a pile more of iterators with unified (obj, dev) arguments. This is just prep. Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
* | drm/i915:skl: Add WaEnableGapsTsvCreditFixArun Siluvery2015-08-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | Cc: Ben Widawsky <benjamin.widawsky@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Tested-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90854 Tested-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | Partially revert "drm/i915: s/mdelay/msleep/" in ilk rps codeDaniel Vetter2015-07-201-3/+3
|/ | | | | | | | | | | | | | This reverts commit 6adfb1ef106bfe4b5ecb8bd75c4d037741d28a48. Ironlake RPS code runs under an irqsave spinlock and hence sleeping isn't allowed. Not a this long delay while blocking irqs isn't great at all, but fixing the locking scheme is a lot more involved. So just revert for now. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reported-by: kernel test robot <ying.huang@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
* drm/i915: Fix divide by zero on watermark updateMika Kuoppala2015-07-171-1/+3
| | | | | | | | | | | | | | | | | Fix divide by zero if we end up updating the watermarks with zero dotclock. This is a stop gap measure to allow module load in cases where our state keeping fails. v2: WARN_ON added (Paulo) Cc: Paulo Zanoni <przanoni@gmail.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaroundArun Siluvery2015-07-151-0/+3
| | | | | | | | | | | | | | | | | In Indirect context w/a batch buffer, +WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt v2: address static checker warning where unsigned value was checked for less than zero which is never true (Dan Carpenter). v3: The WA uses default value of GEN8_L3SQCREG4 during flush but that disables some other WA; update default value to retain it and document dependency (Mika). Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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