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path: root/drivers/gpu/drm/i915/intel_display.c
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* Merge remote branch 'anholt/drm-intel-next' into drm-linusDave Airlie2009-12-081-348/+681
|\ | | | | | | | | | | | | | | | | | | | | This merges the upstream Intel tree and fixes up numerous conflicts due to patches merged into Linus tree later in -rc cycle. Conflicts: drivers/char/agp/intel-agp.c drivers/gpu/drm/drm_dp_i2c_helper.c drivers/gpu/drm/i915/i915_irq.c drivers/gpu/drm/i915/i915_suspend.c
| * drm/i915: Fix product names and #definesAdam Jackson2009-12-071-205/+203
| | | | | | | | | | | | | | | | | | IGD* isn't a useful name. Replace with the codenames, as sourced from pci.ids. Signed-off-by: Adam Jackson <ajax@redhat.com> [anholt: Fixed up for merge with pineview/ironlake changes] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: warn if Pineview CxSR can't be enabledJesse Barnes2009-12-071-0/+7
| | | | | | | | | | If we don't detect a supported memory configuration, we can't enable CxSR. Warn the user in this case so they can file a bug.
| * drm/i915: pageflip fixesJesse Barnes2009-12-071-3/+13
| | | | | | | | | | | | | | | | | | | | This patch brings the tree up to date with some fixes that were in a more recent version of the page flipping patch you applied. It fixes pre-965 flip support, removes a leftover hack that forced alignment, and initializes the pipe & plane CRTC mappings. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix sync to vblank when VGA output is turned offLi Peng2009-12-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current vblank-wait implementation, if we turn off VGA output, drm_wait_vblank will still wait on the disabled pipe until timeout, because vblank on the pipe is assumed be enabled. This would cause slow system response on some system such as moblin. This patch resolve the issue by adding a drm helper function drm_vblank_off which explicitly clear vblank_enabled[crtc], wake up any waiting queue and save last vblank counter before turning off crtc. It also slightly change drm_vblank_get to ensure that we will will return immediately if trying to wait on a disabled pipe. Signed-off-by: Li Peng <peng.li@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: hand-applied for conflicts with overlay changes] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Don't update the render-clock for every bo.Chris Wilson2009-12-011-2/+7
| | | | | | | | | | | | | | | | | | | | Only update the render-clock on transition from busy to idle and vice versa, or else we burn a significant percentage of the cpu just rewriting the register -- not quite as power-friendly as intended ;-) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix warning introduced with the page flipping ioctl.Eric Anholt2009-12-011-1/+0
| | | | | | | | Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Add intel implementation of the pageflip ioctlKristian Høgsberg2009-12-011-32/+196
| | | | | | | | | | | | | | | | | | Acked-by: Jakob Bornecrantz <jakob@vmware.com> Acked-by: Thomas Hellström <thomas@shipmail.org> Review-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse "Orange Smoothie" Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: PineView only has LVDS and CRT portsZhenyu Wang2009-12-011-3/+3
| | | | | | | | | | | | | | | | | | PineView only has 2 ports for LVDS and CRT. Don't enable other ports for it. Cc: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Disable pwrctx before unpin and freeKristian Høgsberg2009-11-301-0/+5
| | | | | | | | | | | | | | | | Otherwise the chip may scribble over free memory. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Hold struct_mutex while unreffing pwrctx objectKristian Høgsberg2009-11-301-2/+2
| | | | | | | | | | | | | | | | This also extends the mutex to cover fbc disabling, which is safe. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: use msleep for intel_wait_for_vblankShaohua Li2009-11-301-1/+1
| | | | | | | | | | | | | | | | | | 20ms delay is quite big and the routine isn't called in atomic context. better use msleep to let other tasks run. This can reduce cpu time used by Xorg, so potentially boost boot. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Fix LVDS stability issue on IronlakeZhenyu Wang2009-11-251-19/+41
| | | | | | | | | | | | | | | | | | | | | | | | In disable sequence, all output ports on PCH have to be disabled before PCH transcoder, but LVDS port was left always enabled. This one fixes that by disable LVDS port properly during pipe disable process, and resolved stability issue seen on Ironlake. Also move panel fitting disable time just after pipe disable to align with the spec. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Restore the DPLL calculation logic for 9xx platformZhao Yakui2009-11-251-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DPLL calculation logic for 9xx platform is changed in: commit 652c393a3368af84359da37c45afc35a91144960 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Mon Aug 17 13:31:43 2009 -0700 drm/i915: add dynamic clock frequency control Maybe we will get the different M/N/P combination with that by using the previous dpll calculation logic. So restore the DPLL calculation logic for 9xx platform. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Enable LVDS downclock feature through EDID.Zhao Yakui2009-11-251-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If more than one mode with the same resolution defined in EDID has different refresh rate, it is thought that the downclock is found for LVDS. We will program the different FPx0/1 register so that we can select dynamically between the low and high frequency. On the g4x platform we will use the CxSR feature to switch the different refresh rate if the LVDS downclock feature is supported. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: fix get_core_clock_speed for G33 class desktop chipsDaniel Vetter2009-11-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Somehow the case for G33 got dropped while porting from ums code. This made a 400MHz chip into a 133MHz one which resulted in the unnecessary enabling of double wide pipe mode which in turn screwed up the overlay code. Nothing else (than the overlay code) seems to be affected. This fixes fdo.org bug #24835 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: enable self-refresh on 965Jesse Barnes2009-11-051-4/+28
| | | | | | | | | | | | | | Need to calculate the SR watermark and enable it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Support 30 bit depth modesKristian Høgsberg2009-11-051-1/+4
| | | | | | | | | | Signed-off-by: Kristian Høgsberg <krh@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMSZhao Yakui2009-11-051-58/+66
| | | | | | | | | | | | | | Replace the DRM_DEBUG with DRM_DEBUG_KMS in output device code. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: Replace DRM_DEBUG with DRM_DEBUG_DRIVERZhao Yakui2009-11-051-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | Replace the DRM_DEBUG with DRM_DEBUG_DRIVER in generic i915 driver. Then the debug info can be obtained by adding the boot option of "drm.debug=0x02". At the same time the debug info in increase/decrease clock is also printed by using DRM_DEBUG_DRIVER instead of DRM_DEBUG_KMS. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: implement interruptible sleeps in the overlay codeDaniel Vetter2009-11-051-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | At least for the common case of userspace ioctls. When doing a modeset operation, the wait is still uninterruptible. But considering that failing to turn off the overlay when switching off the crtc it's running on hangs the chip, it doesn't complicate matters _very_ much. There's just an unkillable X in addition to a black screen. BUG() about it and explain in the code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: implement drmmode overlay support v4Daniel Vetter2009-11-051-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements intel overlay support for kms via a device-specific ioctl. Thomas Hellstrom brought up the idea of a general ioctl (on dri-devel). We've reached the conclusion that such an infrastructure only makes sense when multiple kms overlay implementations exists, which atm don't (and it doesn't look like this is gonna change). Open issues: - Runs in sync with the gpu, i.e. unnecessary waiting. I've decided to wait on this because the hw tends to hang when changing something in this area. I left some dummy functions as infrastructure. - polyphase filtering uses a static table. - uses uninterruptible sleeps. Unfortunately the alternatives may unnecessarily wedged the hw if/when we timeout too early (and userspace only overloaded the batch buffers with stuff worth a few secs of gpu time). Changes since v1: - fix off-by-one misconception on my side. This fixes fullscreen playback. Changes since v2: - add underrun detection as spec'ed for i965. - flush caches properly, fixing visual corruptions. Changes since v4: - fix up cache flushing of overlay memory regs. - killed require_pipe_a logic - it hangs the chip. Tested-By: diego.abelenda@gmail.com (on a 865G) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [anholt: Resolved against the MADVISE ioctl going in before this one] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: kill superflous IS_I855 macroDaniel Vetter2009-11-051-2/+2
| | | | | | | | | | | | | | | | It is identical to I85X. Use that one instead. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [anholt: fix conflicts against the display function pointer stuff] Signed-off-by: Eric Anholt <eric@anholt.net>
| * drm/i915: add render standby supportJesse Barnes2009-11-051-0/+41
| | | | | | | | | | | | | | | | | | | | Render standy allows the GPU to power down the render unit when idle. In order for this to work, it needs a page of graphics memory to save state. This patch allocates that page and enables the feature on supported chipsets. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | Merge branch 'drm-core-next' into drm-linusDave Airlie2009-12-081-1/+1
|\ \ | |/ |/| | | | | | | | | | | Bring all core drm changes into 2.6.32 tree and resolve the conflict that occurs. Conflicts: drivers/gpu/drm/drm_fb_helper.c
| * drm/intel: refactor DP i2c support and DP common header to drm helperDave Airlie2009-12-081-1/+1
| | | | | | | | | | | | | | | | | | | | Both radeon and nouveau can re-use this code so move it up a level so they can. However the hw interfaces for aux ch are different enough that the code to translate from mode, address, bytes to actual hw interfaces isn't generic, so move that code into the Intel driver. Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/i915: Fix and cleanup DPLL calculation for IronlakeZhenyu Wang2009-11-051-9/+6
|/ | | | | | | | | | When the ideal error range can't be reached, this will safely use a most closed one. Clean up some dumb codes in DPLL function too. This fixes DPLL clock issue against one monitor at 1680x1050@60hz. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: kill warning in intel_find_pll_g4x_dpJesse Barnes2009-10-231-0/+1
| | | | | | | Initialize clock.vco to silence gcc. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: update watermarks before enabling PLLsJesse Barnes2009-10-231-1/+2
| | | | | | | | | | When coming back from DPMS or turning on a display, make sure we have the watermarks set up before turning on the display plane, otherwise we may get underruns. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Dirk Hohndel <hohndel@infradead.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: add FIFO watermark support for G4xJesse Barnes2009-10-231-8/+72
| | | | | | | | | Turns out G4x needs to have sensible watermarks set, especially for self-refresh enabled modes. Add support for it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Dirk Hohndel <hohndel@infradead.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix panel fitting filter coefficient select for IronlakeZhenyu Wang2009-10-191-1/+1
| | | | | | | | | | | Must set filter selection as hardcoded coefficients for medium 3x3 filtering, which matches vbios setting for Ironlake. This fixes display corrupt issue on HP arrandale with new vbios. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix to setup display reference clock control on IronlakeZhenyu Wang2009-10-191-0/+40
| | | | | | | | | | | | | | For new stepping of PCH, the display reference clock is fully under driver's control. This one trys to setup all needed reference clock for different outputs. Older stepping of PCH chipset should be ignoring this. This fixes output failure issue on newer PCH which requires driver to take control of reference clock enabling. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Install a fence register for fbc on g4xChris Wilson2009-10-151-3/+5
| | | | | | | | | | | | | | To enable framebuffer compression on a g4x, we not only need the buffer to tiled (X only), we also need to hold a fence register for the buffer. Currently we only install a fence register for pre-i965s when setting up the scanout buffer. Rather than adding some convoluted logic to g4x_enable_fbc() to acquire a fence register, and perhaps to g4x_disable_fbc() to release it again, we can extend the acquisition during setup to all chipsets. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix FDI M/N setting according with correct color depthZhenyu Wang2009-10-131-4/+27
| | | | | | | | | | | | | | FDI M/N calculation hasn't taken the current pipe color depth into account, but always set as 24bpp. This one checks current pipe color depth setting, and change FDI M/N calculation a little to use bits_per_pixel first, then convert to bytes_per_pixel later. This fixes display corrupt issue on Arrandle LVDS with 1600x900 panel in 18bpp dual-channel mode. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: disable powersave feature for Ironlake currentlyZhenyu Wang2009-10-131-2/+9
| | | | | | | | | | | Until we figure out the right setting for powersave features on Ironlake, disable it for now. Also disable watermark update, which has new registers for it on Ironlake too. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [anholt: Resolved against the Pineview FBC changes] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Set the LVDS_BORDER when using LVDS scaling modeZhao Yakui2009-10-131-0/+2
| | | | | | | | | | | | | | | | | | According to the spec the LVDS_BORDER_ENABLE bit decides whether the border data should be included in the active display and data sent to the panel. Border should be used when in VGA centered (un-scaled) mode or when scaling a 4:3 source image to a wide screen panel (typical 16:9). So when the LVDS scaling is used, decide whether the LVDS_BORDER should be enabled or not according to the current scaling mode. At the same time fix the typo error in LVDS center scaling mode. https://bugs.freedesktop.org/show_bug.cgi?id=23789 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> tested-by: Zhao Jian <jian.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* Merge branch 'drm-intel-next' of ↵Linus Torvalds2009-10-091-4/+0
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: drm/i915: Initialize HDMI outputs as HDMI connectors, not DVI. drm/i915: Multiply the refresh by 1000 in TV mode validatiion drm/i915: Enable irq to trace batch buffer completion. drm/i915: batch submit seqno off-by-one. drm/i915: Record device minor rather than pointer in TRACE_EVENT drm/i915: Don't call intel_update_fbc from intel_crtc_cursor_set
| * drm/i915: Don't call intel_update_fbc from intel_crtc_cursor_setBrian Rogers2009-09-281-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 74dff282 exposed this unnecessary call by causing a change in the failure path on i965 where framebuffer compression will be turned on and off on every cursor update. If you don't have the xf86-video-intel fix to avoid the blinking cursor effect, this is very slow. Symptoms were a far more noticeable cursor blink with every cursor image change combined with severe slowdown for animated cursors. Signed-off-by: Brian Rogers <brian@xyzw.org> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* | Merge branch 'drm-next' of ../drm-next into drm-linusDave Airlie2009-10-081-0/+11
|\ \ | |/ |/| | | | | | | | | | | | | conflict in radeon since new init path merged with vga arb code. Conflicts: drivers/gpu/drm/radeon/radeon.h drivers/gpu/drm/radeon/radeon_asic.h drivers/gpu/drm/radeon/radeon_device.c
| * drm/fb: add more correct 8/16/24/32 bpp fb support.Dave Airlie2009-10-061-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | The previous patches had some unwanted side effects, I've fixed the lack of 32bpp working, and fixed up 16bpp so it should also work. this also adds the interface to allow the driver to set a preferred console depth so for example low memory rn50 can set it to 8bpp. It also catches 24bpp on cards that can't do it and forces 32bpp. Tested on r100/r600/i945. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * drm/fb: add setcmap and fix 8-bit support.Dave Airlie2009-10-051-0/+1
| | | | | | | | | | | | | | | | This adds support for the setcmap api and fixes the 8bpp support at least on radeon hardware. It adds a new load_lut hook which can be called once the color map is setup. Signed-off-by: Dave Airlie <airlied@redhat.com>
* | Merge branch 'drm-intel-next' of ↵Linus Torvalds2009-09-241-107/+509
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (57 commits) drm/i915: Handle ERESTARTSYS during page fault drm/i915: Warn before mmaping a purgeable buffer. drm/i915: Track purged state. drm/i915: Remove eviction debug spam drm/i915: Immediately discard any backing storage for uneeded objects drm/i915: Do not mis-classify clean objects as purgeable drm/i915: Whitespace correction for madv drm/i915: BUG_ON page refleak during unbind drm/i915: Search harder for a reusable object drm/i915: Clean up evict from list. drm/i915: Add tracepoints drm/i915: framebuffer compression for GM45+ drm/i915: split display functions by chip type drm/i915: Skip the sanity checks if the current relocation is valid drm/i915: Check that the relocation points to within the target drm/i915: correct FBC update when pipe base update occurs drm/i915: blacklist Acer AspireOne lid status ACPI: make ACPI button funcs no-ops if not built in drm/i915: prevent FIFO calculation overflows on 32 bits with high dotclocks drm/i915: intel_display.c handle latency variable efficiently ... Fix up trivial conflicts in drivers/gpu/drm/i915/{i915_dma.c|i915_drv.h}
| * | drm/i915: framebuffer compression for GM45+Jesse Barnes2009-09-211-7/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for framebuffer compression on GM45 and above. Removes some unnecessary I915_HAS_FBC checks as well (this is now part of the FBC display function). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: split display functions by chip typeJesse Barnes2009-09-211-98/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch splits out several of the display functions into a separate display function table to avoid tons of chipset specific if..else if..else if blocks all over. There are more opportunities for this (some noted in the structure defintition); so more cleanup patches will follow. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | drm/i915: correct FBC update when pipe base update occursJesse Barnes2009-09-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | We usually don't have an SAREA, and we always want to update the FBC status anyway, so move the update up above the various master/sarea checks. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: prevent FIFO calculation overflows on 32 bits with high dotclocksJesse Barnes2009-09-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A very high dotclock (e.g. 229500kHz as reported by Anton) can cause the entries_required variable to overflow, potentially leading to a FIFO watermark value that's too low to support the given mode. Split the division across the calculation to avoid this. Cc: stable@kernel.org Reported-by: Anton Khirnov <wyskas@gmail.com> Tested-by: Anton Khirnov <wyskas@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: intel_display.c handle latency variable efficientlyJaswinder Singh Rajput2009-09-171-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By handling latency variable efficiently we also get rid of this warning : CC [M] drivers/gpu/drm/i915/intel_display.o drivers/gpu/drm/i915/intel_display.c: In function ‘igd_enable_cxsr’: drivers/gpu/drm/i915/intel_display.c:1918: warning: ‘latency’ may be used uninitialized in this function Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: fix startup hang on some non-mobile platformsJesse Barnes2009-09-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to a bogus FBC support check and failing to check for FBC support in the right places, mode setting on non-mobile platforms could fail and hang in the FBC disable routine. Fix it up. This fix highlights the need for cleanups in this area (function pointers and better feature support checks). Patches for that to follow. Tested-by: Kenny Graunke <kenny@whitecape.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: Fix LVDS panel fitting on ArrandaleZhenyu Wang2009-09-171-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arrandale has new window based method for panel fitting. This one enables full screen aspect scaling on LVDS. It fixes standard mode display failure on LVDS for Arrandale. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | drm/i915: Fix typo for wrong LVDS clock setting on IGDNGZhenyu Wang2009-09-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New register for PCH LVDS on IGDNG should be used. This is a copy-n-paste typo. This fixes possible dual channel LVDS panel failure on IGDNG. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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