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| | * drm/amd/display: Update extended timeout support for DCN20 and DCN21abdoulaye berthe2019-12-182-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] DCN21 and DCN2 extended timeout support cap is not set correctly. [How] Set extended timeout support for ASIC families to their right values. Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Fix update_bw_bounding_box CalcsSung Lee2019-12-181-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Previously update_bw_bounding_box for RN was commented out due to incorrect values causing BSOD on Hybrid Graphics. However, commenting out this function also may cause issues such as underflow in certain cases such as 2x4K displays. [How] Fix dram_speed_mts calculations. Update from proper index of clock_limits[] Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Use absolute time stamp to follow the eDP T7 spec requirementDale Zhao2019-12-181-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why]: According to eDP spec, max T7 delay should be 50 ms. Current code uses 300 retry counters may not be accurate enough for different panels. [How]: Use absolute time stamp to achive accurate delay. Signed-off-by: Dale Zhao <dale.zhao@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: 3.2.64Aric Cyr2019-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: fix 270 degree rotation for mixed-SLS modeSamson Tam2019-12-181-3/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] When we rotate 270 in mixed SLS mode, the recouts occupy the right side of the display. So all the recout_skip_v values are relative to the left side of the display. This causes adjust_vp_and_init_for_seamless_clip() to incorrectly increase the data->viewport.height for that recout. The rotation looks like the bottom half is duplicated twice. [How] recout.x values are being adjusted based on stream->timing.h_border_left. Instead of using h_border_left, use dst.x to represent the border. Shift dst.x by the amount of stream->timing.h_border_left and set stream->timing.h_border_left to 0. Do all the calculations and then revert stream->timing.h_border_left and stream->dst.x back to their original values. When calculating pipe_ctx->plane_res.scl_data.h_active, make sure to use the original stream->timing.h_border_left value. Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Get cache window sizes from DMCUB firmwareNicholas Kazlauskas2019-12-184-44/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Firmware state and tracebuffer shouldn't be considered stable API between firmware versions. Driver shouldn't be querying anything from firmware state or tracebuffer outside of debugging. Commands are the stable API for this once we have the outbox. [How] Add metadata struct to the end of the data firmware that describes fw_state_size and some reserved area for future use. Drop the tracebuffer and firmware state headers since they can differ per version. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Remove reliance on pipe indexingNoah Abradjian2019-12-182-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] In certain instances, there was a reliance on pipe indexing being accurate. However, this assumption fails with harvesting of pipes 1 or 2, which can occur in production B6 parts. HW hang would occur as a result. [How] Use hubp index for mpcc, and do mpc_init for all theoretical pipes (including disabled ones). Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Specified VR patch skip to reset segment to 0Derek Lai2019-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] After read the 3rd Edid blocks, we will reset segment to 0, which causes this VR fail to read Edid successfully. [How] Skip to reset segment to 0 for this VR device. Signed-off-by: Derek Lai <Derek.Lai@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: check link status before disable streamPaul Hsieh2019-12-182-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] 1. Set second screen only then unplug external monitor 2. Enter to S4 then plug in external monitor 3. Resume from S4, eDP will not turn off when OS set second screen only Sometimes OS will not set eDP power up cause eDP dpms_off keep true then driver skipp disable stream [How] When drvier try to disable stream, add link status condition Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: disable lttpr for NaviHugo Hu2019-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Perform DMUB hw_init on resumeNicholas Kazlauskas2019-12-182-75/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The DMUB is put into reset on suspend and is not running on resume, disabling PSR/ABM features. [How] Move the allocation of the framebuffer to sw_init. Do DMUB hardware init and framebuffer filling only from hw_init. On resume the contents of the framebuffer will be invalid so those should be cleared. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Map ODM memory correctly when doing ODM combineNikola Cornij2019-12-181-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Up to 4 ODM memory pieces are required per ODM combine and cannot overlap, i.e. each ODM "session" has to use its own memory pieces. The ODM-memory mapping is currently broken for generic case. The maximum number of memory pieces is ASIC-dependent, but it's always big enough to satisfy maximum number of ODM combines. Memory pieces are mapped as a bit-map, i.e. one memory piece corresponds to one bit. The OPTC doing ODM needs to select memory pieces by setting the corresponding bits, making sure there's no overlap with other OPTC instances that might be doing ODM. The current mapping works only for OPTC instance indexes smaller than 3. For instance indexes 3 and up it practically maps no ODM memory, causing black, gray or white screen in display configs that include ODM on OPTC instance 3 or up. [how] Statically map two unique ODM memory pieces for each OPTC instance and piece them together when programming ODM combine mode. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Add warmup escape call supportCharlene Liu2019-12-187-30/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add warmup escape support, for diags, in a way that is possible to choose a new or an existing sequence. For achieving this goal, this commit adds separated MCIF buffer as VCN request. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: fix regamma build optimizationJosip Pavic2019-12-181-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] When the global variable pow_buffer_ptr is set to -1, by definition optimizations should not be used to build the regamma. Since translate_from_linear_space unconditionally increments this global, it inadvertently enables the optimization. [How] Increment pow_buffer_ptr only if it is not -1. Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: scaling changes should also be a full updateAric Cyr2019-12-181-4/+4
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: 3.2.63Aric Cyr2019-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Remove integer scaling code from DC and fix cursorAric Cyr2019-12-182-45/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Scaling better handled by upper layers before pipe splitting. [How] Remove DC code for integer scaling and force cursor update if viewport or scaling changes occur to prevent underflow from invalid cursor position. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Enable Seamless Boot Transition for Multiple StreamsMartin Leung2019-12-185-11/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] dc previously had bugs that interfered with the ability to inherit a timing from a device with multiple streams (without flash/blanking). After this fix there is still a dependency on UEFI support. [how] fixed 3 bugs: loaded MPC state, changed bw_optimize flag to a counter instead of a boolean, and reading dpp/disp clk from HW to ensure we don't raise the clock's when we're not supposed to. Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Default max bpc to 16 for eDPRoman Li2019-12-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Some 10bit eDP panels don't lightup after we cap bpc to 8. [How] Set default max_bpc to 16 for edp connector type. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Collapse resource arrays when pipe is disabledNoah Abradjian2019-12-181-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Currently, pipe resources are assigned to an index that matches the pipe position. However, if pipe 1 or 2 is disabled, there will be a gap in the arrays which causes a crash when iterating based on pipe_count. [How] Fix resource construct to assign resources to minimum available array index. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: update chroma viewport waEric Yang2019-12-187-41/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Need previously implemented chroma vp wa to work for rotation cases. [How] Implement rotation specific wa. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Use pipe_count for num of oppsNoah Abradjian2019-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There is one opp per pipe. For certain RN parts, the fourth pipe is disabled, so there is no opp for it. res_cap->num_opp is hardcoded to 4, so if we use that to iterate over opps we will crash. [How] Use the pipe_count value instead, which is not hardcoded and so will have the correct number. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Reinstate LFC optimizationAmanda Liu2019-12-182-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] We want to streamline the calculations made when entering LFC. Previously, the optimizations led to screen tearing and were backed out to unblock development. [how] Integrate other calculations parameters, as well as screen tearing, fixes with the original LFC calculation optimizations. Signed-off-by: Amanda Liu <amanda.liu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: AVI info package change due to spec updateQingqing Zhuo2019-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | YQ should be limited range for all cases. Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Add definition for number of backlight data pointsCamille Cho2019-12-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] A hardcoded number is used today [How] Add definition for number of BL data points Signed-off-by: Camille Cho <Camille.Cho@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Add interface to adjust DSC max target bpp limitJoshua Aberback2019-12-182-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] For some use cases we need to be able to adjust the maximum target bpp allowed by DSC policy. [How] New interface dc_dsc_policy_set_max_target_bpp_limit Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Disable integerscaling for downscale and MPOAidan Yang2019-12-181-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Integer scaling is applied to MPO planes when downscaling, MPO planes use variable taps and integer scaling sets taps=1 [How] Disable integer scaling on MPO planes, Disable integer scaling for downscaling planes Signed-off-by: Aidan Yang <Aidan.Yang@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Use physical addressing for DMCUB on both dcn20/21Nicholas Kazlauskas2019-12-184-125/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] CW0 and CW1 need to use physical addressing mode for dcn20 and dcn21. The current code for dcn20 is using virtual. [How] We already program the DMCUB like this on dcn21 so we should just use the same sequence for both. Copy the dcn21 sequences into the dmjub_dcn20.c file and rename them. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Get DMUB registers from ASIC specific structsNicholas Kazlauskas2019-12-187-6/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] These values can differ per ASIC and should follow the full DC style register programming model. [How] Define a common list and fill in the common list separately for dcn20 and dcn21. Unlike DC we're not using designated initializers for better compiler compatibility since this resides in the DMUB service. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Add wait for flip not pending on pipe unlockNoah Abradjian2019-12-181-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Lack of proper timing caused intermittent underflow on unplug external DP. A previous fix was invalid and caused S0i3 regression, so had to be reverted. [How] When unlocking pipe, wait for no pipes to have flip pending before unlocking. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: disable lttpr for RNabdoulaye berthe2019-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: HDMI 2.x audio bandwidth checkCharlene Liu2019-12-185-2/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add HDMI 2.x audio bandwidth check Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/vcn: remove JPEG related code from idle handler and begin useLeo Liu2019-12-181-23/+5
| | | | | | | | | | | | | | | | | | | | | | | | For VCN2.0 and above, VCN has been separated from JPEG Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/vcn1.0: use its own idle handler and begin use funcsLeo Liu2019-12-185-6/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because VCN1.0 power management and DPG mode are managed together with JPEG1.0 under both HW and FW, so separated them from general VCN code. Also the multiple instances case got removed, since VCN1.0 HW just have a single instance. v2: override work func with vcn1.0's own Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: enable gfxoff for raven1 refreshchangzhu2019-12-181-11/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When smu version is larger than 0x41e2b, it will load raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads raven_kicker_rlc.bin. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/sriov: Tonga sriov also need load firmware with smuEmily Deng2019-12-182-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix Tonga sriov load driver fail issue. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewd-by Yintian Tao <Yintian.tao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: drop useless BACO arg in amdgpu_ras_reset_gpuGuchun Chen2019-12-186-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BACO reset mode strategy is determined by latter func when calling amdgpu_ras_reset_gpu. So not to confuse audience, drop it. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: add missing dcn link encoder regsRoman Li2019-12-185-6/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The earlier change: "check phy dpalt lane count config" uses link encoder registers not defined properly. That caused regression with mst-enabled display not lighting up. [How] Add missing reg definitions. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add dpcs20 registersRoman Li2019-12-182-0/+4559
| | | | | | | | | | | | | | | | | | | | | | | | add reg headers to dpcs includes Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: move dpcs headers to dpcs includesRoman Li2019-12-182-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | - create dpcs directory for dpcs asic_reg headers - move dpcs21 reg headers from dcn to dpcs directory Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Add CU info print logYong Zhao2019-12-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The log will be useful for easily getting the CU info on various emulation models or ASICs. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdkfd: Use Arcturus specific set_vm_context_page_table_base()Yong Zhao2019-12-183-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since Arcturus has it own function pointer, we can move Arcturus specific logic to there rather than leaving it entangled with other GFX9 chips. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/powerplay: fix various dereferences of a pointer before it is null ↵Colin Ian King2019-12-182-15/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | checked There are several occurrances of the pointer hwmgr being dereferenced before it is null checked. Fix these by performing the dereference of hwmgr after it has been null checked. Addresses-Coverity: ("Dereference before null check") Fixes: c9ffa427db34e6 ("drm/amd/powerplay: enable pp one vf mode for vega10") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdkfd: queue kfd interrupt work to different CPUPhilip Yang2019-12-181-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because queue_work schedule the work on the same CPU the interrupt handler is running, if there are many interrupts pending, it takes longer time for work queue to start, or even worse system will hang. v2: queue work to same NUMA node for better cache locality v3: handle cpumask_next wraparound case Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * amdgpu: Wrap FPU dependent functions in dc20Timothy Pearson2019-12-181-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dc20 containes several FPU-dependent functions without proper FPU kernel mode enable/disable wrappers. Add the required wrappers for both x86 and POWER. This enables Navi DC20 support for POWER systems. v2: fix compilation Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * amdgpu: Enable initial DCN support on POWERTimothy Pearson2019-12-188-1/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCN requires floating point support to operate. Add the appropriate x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN. Note that the current DC20 code doesn't contain all required FPU wrappers on x86 or POWER, so this patch is insufficient to fully enable DC20 on POWER. v2: s/X86_64/X86/g to retain previous behavior. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * amdgpu: Prepare DCN floating point macros for generic arch supportTimothy Pearson2019-12-184-16/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce DC_FP_START()/DC_FP_END() macros to help enable floating point kernel mode support across various architectures. v2: move copyright update to commit which adds the changes Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/display: use msleep rather than udelay for HDCPAlex Deucher2019-12-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM has a 2000us limit for udelay. Switch to msleep. This code executes in a worker thread so shouldn't be an atomic context. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191217204707.2258744-2-alexander.deucher@amd.com
| * | drm/amdgpu/display: include delay.hAlex Deucher2019-12-191-0/+2
| |/ | | | | | | | | | | | | | | | | For udelay. This is needed for some platforms. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazluaskas@amd.om> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191217204707.2258744-1-alexander.deucher@amd.com
| * Merge tag 'drm-next-5.6-2019-12-11' of ↵Daniel Vetter2019-12-17366-6482/+15987
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~agd5f/linux into drm-next drm-next-5.6-2019-12-11: amdgpu: - Add MST atomic routines - Add support for DMCUB (new helper microengine for displays) - Add OEM i2c support in DC - Use vstartup for vblank events on DCN - Simplify Kconfig for DC - Renoir fixes for DC - Clean up function pointers in DC - Initial support for HDCP 2.x - Misc code cleanups - GFX10 fixes - Rework JPEG engine handling for VCN - Add clock and power gating support for JPEG - BACO support for Arcturus - Cleanup PSP ring handling - Add framework for using BACO with runtime pm to save power - Move core pci state handling out of the driver for pm ops - Allow guest power control in 1 VF case with SR-IOV - SR-IOV fixes - RAS fixes - Support for power metrics on renoir - Golden settings updates for gfx10 - Enable gfxoff on supported navi10 skus - Update MAINTAINERS amdkfd: - Clean up generational gfx code - Fixes for gfx10 - DIQ fixes - Share more code with amdgpu radeon: - PPC DMA fix - Register checker fixes for r1xx/r2xx - Misc cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191211223020.7510-1-alexander.deucher@amd.com
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