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* | | drm/amd/display: Add DC build_id to determine build typeJun Lei2018-10-092-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Sometimes there are indications that the incorrect driver is being loaded in automated tests. This change adds the ability for builds to be tagged with a string, and picked up by the test infrastructure. [how] dc.c will allocate const for build id, which is init-ed with default value, indicating production build. For test builds, build server will find/replace this value. The test machine will then verify this value. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVDAkshu Agrawal2018-10-091-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We observe black lines (underflow) on display when playing a 4K video with UVD. On Disabling Low memory P state this issue is not seen. Multiple runs of power measurement shows no imapct. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* | | drm/amd/pp: Remove wrong code in fiji_start_smuRex Zhu2018-10-091-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | HW CG feature will be enabled after hw ip initialized Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/pp: Remove uncessary extra vcn pg cntl in smuRex Zhu2018-10-091-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | the vcn power will be controlled by VCN. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Move out power up/down sdma out of smuRex Zhu2018-10-093-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | smu only expose interface to other ip blocks. in order to reduce dependence between smu and other ip blocks Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/pp: Expose the smu support for SDMA PG cntlRex Zhu2018-10-093-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | SDMA IP can be power up/down via smu message Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/pp: Avoid divide-by-zero in fan_ctrl_set_fan_speed_rpmRex Zhu2018-10-092-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The minRPM speed maybe equal to zero. so need to check input RPM not equal to 0, otherwise cause divide-by-zero driver crash. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/pp: Fix fan's RPM setting not work on VI/Vega10Rex Zhu2018-10-092-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | set the target rpm value to wrong register. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Fix comments error in sdma_v4_1_update_power_gatingRex Zhu2018-10-091-1/+1
| | | | | | | | | | | | | | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: enable MGPU fan boost feature on Vega20Evan Quan2018-10-091-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added Vega20 specific implementation for MGPU fan boost feature. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: helper interfaces for MGPU fan boost featureEvan Quan2018-10-095-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | MGPU fan boost feature is enabled only when two or more dGPUs in the system. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: added AMD GPU instance counting V2Evan Quan2018-10-093-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Count all GPU instances from AMD(including iGPUs and dGPUs) in the system. V2: drop unnecessary initialization for other gpu_info members except mutex Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vega20: make power profile output more consistentAlex Deucher2018-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the profile name line match previous generations more closely. E.g., 0 3D_FULL_SCREEN : vs: 0(3D_FULL_SCREEN ) Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: change Raven always on CUs to 4Evan Quan2018-10-091-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | For Vega10 and Vega20, the always on CUs are 12. For Raven, it's 4. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: added vega20 LBPW support v2Evan Quan2018-10-091-1/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable LBPW support on vega20. v2: squash in warning fix (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2Evan Quan2018-10-095-4/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Manual fan RPM and pwm setting on vega20 are available now. V2: correct the register for fan speed setting and avoid divide-by-zero Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay/vega20: tell the correct gfx voltage V2Evan Quan2018-10-093-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the correct gfx voltage by hwmon interface. V2: update the register naming for consistency Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay/vega20: correct the hwmon interface ppt limit outputEvan Quan2018-10-092-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ppt limit read out by hwmon interface is always 0. Correct this hwmon interface output. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | BackMerge v4.19-rc6 into drm-nextDave Airlie2018-10-048-28/+142
|\| | | | | | | | | | | | | | | | | I have some pulls based on rc6, and I prefer to have an explicit backmerge. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/amd/display: Fix Edid emulation for linuxBhawanpreet Lakha2018-09-273-7/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] EDID emulation didn't work properly for linux, as we stop programming if nothing is connected physically. [How] We get a flag from DRM when we want to do edid emulation. We check if this flag is true and nothing is connected physically, if so we only program the front end using VIRTUAL_SIGNAL. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/display: Fix Vega10 lightup on S3 resumeRoman Li2018-09-273-18/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There have been a few reports of Vega10 display remaining blank after S3 resume. The regression is caused by workaround for mode change on Vega10 - skip set_bandwidth if stream count is 0. As a result we skipped dispclk reset on suspend, thus on resume we may skip the clock update assuming it hasn't been changed. On some systems it causes display blank or 'out of range'. [How] Revert "drm/amd/display: Fix Vega10 black screen after mode change" Verified that it hadn't cause mode change regression. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Fix vce work queue was not cancelled when suspendRex Zhu2018-09-272-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vce cancel_delayed_work_sync never be called. driver call the function in error path. This caused the A+A suspend hang when runtime pm enebled. As we will visit the smu in the idle queue. this will cause smu hang because the dgpu has been suspend, and the dgpu also will be waked up. As the smu has been hang, so the dgpu resume will failed. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* | | drm/amd/powerplay: Change id parameter type in ↵Nathan Chancellor2018-09-272-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pp_atomfwctrl_get_clk_information_by_clkid Clang generates warnings when one enumerated type is implicitly converted to another. drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomfwctrl.c:532:57: warning: implicit conversion from enumeration type 'enum atom_smu11_syspll0_clock_id' to different enumeration type 'BIOS_CLKID' (aka 'enum atom_smu9_syspll0_clock_id') [-Wenum-conversion] if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, &frequency)) In this case, that is expected behavior. To make that clear to Clang without explicitly casting these values, change id's type to uint8_t in pp_atomfwctrl_get_clk_information_by_clkid so no conversion happens. Reported-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdkfd: Remove the requirement for atomic Ops on vg20Shaoyun Liu2018-09-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Firmware have the workaround to replace the atomic Ops with read-modify-write on CP side. User should not expect atomic Ops on system memory works normally if system didn't not support it. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-By: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/vcn: whitespace cleanupAlex Deucher2018-09-261-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | Fix some indentation issues. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/soc15: fix warnings in register macroAlex Deucher2018-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | expects argument of type ‘unsigned int’ has type ‘long int’ Fixes: 52e211c1f04 ("drm/amdgpu:Add error message when register failed to reach expected value") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:Enable DPG mode on PCOJames Zhu2018-09-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:Add DPG pause mode supportJames Zhu2018-09-261-2/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add functions to support VCN DPG pause mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:Add DPG pause stateJames Zhu2018-09-261-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DPG pause state to support VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:Add DPG mode support for vcn 1.0James Zhu2018-09-261-6/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DPG mode start/stop/mc_resume/clock_gating to support vcn 1.0 DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:Add DPG mode read/write macroJames Zhu2018-09-261-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some registers read/write needs program through SDRAM pool under DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:Add DPG support flagJames Zhu2018-09-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DPG support flag for VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:Add new register offset/mask to support VCN DPG modeJames Zhu2018-09-262-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New register offset/mask need to be added to support VCN DPG mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib testJames Zhu2018-09-261-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers can't be directly accessed under DPG(Dynamic Power Gate) mode. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: move more defines into amdgpu_irq.hChristian König2018-09-2635-95/+94
| | | | | | | | | | | | | | | | | | | | | | | | Everything that isn't related to the IH ring. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: move more interrupt processing into amdgpu_irq.cChristian König2018-09-263-21/+38
| | | | | | | | | | | | | | | | | | | | | | | | Add a callback to amdgpu_ih_process to remove most of the IV logic. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Move fence SW fallback warning v3Andrey Grodzovsky2018-09-262-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_process to let amdgpu_fence_fallback know fences were actually processed and then print the warning. v3: Always return true if seq != last_seq Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: cleanup amdgpu_ih.cChristian König2018-09-269-102/+84
| | | | | | | | | | | | | | | | | | | | | | | | Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: make function pointers mandatoryChristian König2018-09-2620-90/+55
| | | | | | | | | | | | | | | | | | | | | | | | We always want those to be setup correctly. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: drop extra newline in amdgpu_iv traceChristian König2018-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | That is superflous here. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: fix the page fault of raven2Huang Rui2018-09-262-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/pp: Disable dpm features on smu7/8 when suspendRex Zhu2018-09-262-18/+32
| | | | | | | | | | | | | | | | | | | | | | | | Need to disable dpm features before halt rlc. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Remove redundant code in gfx_v8_0.cRex Zhu2018-09-261-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the CG related registers have been programed in golden setting PG register default value is 0. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hang Zhou <hang.zhou@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Halt rlc/cp in rlc_safe_modeRex Zhu2018-09-261-27/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | before halt rlc/cp, need to 1. enter rlc safe mode 2. wait rlc/cp idle Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Hang Zhou <hang.zhou@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Refine function nameRex Zhu2018-09-264-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | change function name gfx_v6/7/8/9_0_gpu_init to gfx_v6/7/8/9_0_constants_init. this function is just for init gfx constants such as max pipes, render backends... Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: Deactivate SW interrupt fallback in amdgpu_fence_process v2Andrey Grodzovsky2018-09-261-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deactivate SW interrupt fallback when all emited fences are completed. Also switch interrupt SW fallback message from INFO to WARN. v2: shorten the warning message a bit and only re-activate the timer during processing if it was already activated before. (Christian) Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Christian Konig <Christian.Koenig@amd.com> Reviewed-and-Tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdkfd: Vega20 bring up on amdkfd sideShaoyun Liu2018-09-268-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Vega20 device IDs, device info and enable it in KFD. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
* | | drm/amdgpu: Add vega20 support on kfd probeShaoyun Liu2018-09-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Vega20 support in amdgpu_amdkfd_device_probe. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
* | | drm/amd: Interface change to support 64 bit page_table_baseShaoyun Liu2018-09-269-23/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | amdgpu_gpuvm_get_process_page_dir should return the page table address in the format expected by the pm4_map_process packet for all ASIC generations. Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdkfd: Make the number of SDMA queues variableShaoyun Liu2018-09-264-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vega20 supports 8 SDMA queues per engine Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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