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* | | drm/amd/powerplay: add function set_thermal_fan_table for navi10Kevin Wang2019-06-211-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | add callback function set_thermal_fan_table for navi10 asic Signed-off-by:Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function is_dpm_running for navi10Kevin Wang2019-06-211-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | add callback function is_dpm_running for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move read sensor of UVD[VCE]_POWER to amdgpu_smu fileKevin Wang2019-06-212-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | This part of code is asic unrelated and moves to top code level. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function get_current_activity_percent for navi10Kevin Wang2019-06-211-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | add callback function get_current_activity_percent for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function get_gpu_power for navi10Kevin Wang2019-06-211-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | add callback function get_gpu_power for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function unforce_dpm_levels for navi10Kevin Wang2019-06-211-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | add callback function unforce_dpm_levels for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add funciton force_dpm_limit for navi10Kevin Wang2019-06-211-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | add callback function force_dpm_limit for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function display_configuration_changed for navi10Kevin Wang2019-06-213-11/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | 1.add callback function to support navi10 asic. 2.Remove unnecessary logical code. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function pre_display_config_changed for navi10Kevin Wang2019-06-211-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | add callback function pre_display_config_changed for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10Kevin Wang2019-06-213-9/+44
| | | | | | | | | | | | | | | | | | | | | | | | add callback function get_clock_by_type_with_latency for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function populate_umd_state_clk for navi10Kevin Wang2019-06-211-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | add callback function populate_umd_state_clk for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function force_clk_levels for navi10Kevin Wang2019-06-213-11/+48
| | | | | | | | | | | | | | | | | | | | | | | | add sysfs interface of force_clk_levels sysfs for navi10. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add helper function of smu_set_hard_freq_rangeKevin Wang2019-06-212-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | add this function to get dpm clock information. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add helper function of smu_set_soft_freq_rangeKevin Wang2019-06-212-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | add this helper function to get dpm clk information. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add helper function of smu_get_dpm_freq_rangeKevin Wang2019-06-212-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | add this helper function to get dpm clk information (min, max); Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function print_clk_levels for navi10Kevin Wang2019-06-213-14/+65
| | | | | | | | | | | | | | | | | | | | | | | | add sysfs interface of print_clk_levels sysfs for navi10. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add helper function to get dpm freq informationsKevin Wang2019-06-212-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | this function can help driver to get ppclk informations Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function get current clock freq interface for navi10Kevin Wang2019-06-213-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | add function of get_current_clk_freq_by_table for navi10. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: RLC must be disabled after SMU when S3 on naviJack Xiao2019-06-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | SMU requires to interact with RLC when disable all features, so RLC shouldn't be disabled ahead of SMU. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabledJack Xiao2019-06-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | MP1 cannot access clock IP during MP1 FW reload, disable PLL shutdown as a workaround. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: disable uclk dpm by defaulttiancyin2019-06-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] The uclk dpm feature is not supported by some certain navi10 board like 18202, while supported by some board like 18201. It causes modprobe failure on 18202 board. [how] Disabled this feature by default, it can be enabled by module parameter uclk_dpm_support=1. Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | amd/powerplay: enable uclk dpmKenneth Feng2019-06-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable uclk dpm on navi10 as the result of removing fast switch setting. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | amd/powerplay: fix the issue of uclk dpmKenneth Feng2019-06-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPSMC_MSG_SetUclkFastSwitch message can be applied on vega20, but can't on navi10. This is the prerequisite of uclk dpm on navi10. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context (v2)Hawking Zhang2019-06-211-10/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's not needed for navi. v2: remove unused variable (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add new interface for vcn powergatingKenneth Feng2019-06-212-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add new interface for vcn powrergating and vcn dpm as well. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: enable vcn powergating v2Kenneth Feng2019-06-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable vcn powergating in driver for navi10 v2: set vcn pg bit according to AMD_PG_SUPPORT_VCN flag Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpmHuang Rui2019-06-211-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm doesn't work so far and we needs to enable the sysfs interfaces. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: update smu11_driver_if_navi10.hKenneth Feng2019-06-211-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.15.0 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN DPM is workableHuang Rui2019-06-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This dpm_enabled flag will be recognized as the VCN DPM enabled as well. In fact VCN/DCN DPM on Navi10 is not good so far, so we cannot enable it for now. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: fix the incorrect type of pptableKenneth Feng2019-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to fix the incorrect type of pptable, otherwise, the data will be totally wrong in parsing phase. Signed-off-by: Kenneth Feng <Kenneth.Feng@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: don't include the smu11 driver if header in smu v11 (v2)Huang Rui2019-06-213-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This header is actually for each asic, so we should not include in smu_v11_0.c. And rename the one for navi10. v2: add hack for XGMI (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move getting MAX_FAN_RPM value to asic levelHuang Rui2019-06-212-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to asic level. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: introduce smu power source type to handle AC/DC source ↵Huang Rui2019-06-215-1/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for each asic This patch introduces new smu power source type, it's to handle the different AC/DC source defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move Watermarks_t uses into asic levelHuang Rui2019-06-213-61/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the rest of Watermarks_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move SmuMetrics_t uses into asic levelHuang Rui2019-06-213-50/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move PPTable_t uses into asic levelHuang Rui2019-06-213-32/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the rest of PPTable_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: use the table size member in the structure instead of ↵Huang Rui2019-06-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getting directly This patch uses the table size member in the structure instead of getting directly, because the table is different in each asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx as the inputHuang Rui2019-06-212-14/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Table id may be different for each asic, so it's good to use this as the input for common interface. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay/smu11: remove smu_update_table_with_argAlex Deucher2019-06-212-7/+3
| | | | | | | | | | | | | | | | | | | | | Nothing was using it. Just replace with smu_update_table which is what everything was using via a wrapper anyway. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add tables_init interface for each asicHuang Rui2019-06-215-15/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The smc tables defines should be in the asic level. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: init table_count for smu tables on asic levelHuang Rui2019-06-213-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TABLE_COUNT should be inited in asic level. Because the value may be different on each asic even on the same ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: introduce smu table id type to handle the smu table for ↵Huang Rui2019-06-214-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | each asic This patch introduces new smu table type, it's to handle the different smu table defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: introduce smu feature type to handle feature mask for ↵Huang Rui2019-06-217-61/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | each asic This patch introduces new smu feature type, it's to handle the different feature mask defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: introduce smu clk type to handle ppclk for each asicHuang Rui2019-06-215-35/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces new smu clk type, it's to handle the different ppclk defines for each asic with the same smu ip. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu: enable sw smu driver for navi10 by defaultHawking Zhang2019-06-211-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Navi10 will use sw smu driver for dynamic power managment, while vega20 could also use sw smu driver when amdgpu_dpm is set to 2 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: enable DCEFCLK dpm supportKenneth Feng2019-06-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enabale DCEFCLK dpm on navi10 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: gfxoff-seperate the Vega20 caseKenneth Feng2019-06-211-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | seperate the Vega20 case from navi10 for gfxoff so that gfxoff won't be allowed on Vega20 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/amdgpu: fw version check with gfxoffKenneth Feng2019-06-212-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. check the firmware version when enabling gfxoff 2. overwrite the pptable to make sure gfxoff is really enabled on navi10 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd: add gfxoff support on navi10Kenneth Feng2019-06-212-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | add the gfxoff interface to navi10,it's disabled by default. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add allowed feature mask for navi10Kevin Wang2019-06-211-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add smu feature mask: 1.FEATURE_DPM_PREFETCHER_BIT 2.FEATURE_DPM_PREFETCHER_BIT 3.FEATURE_ATHUB_PG Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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