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path: root/drivers/gpu/drm/amd/powerplay
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* | | drm/amdgpu: fix modprobe failure for uvd_4/5/6Hawking Zhang2019-06-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For uvd_4/5/6, amdgpu driver will only power on them when there are jobs assigned to decode/enc rings.uvd_4/5/6 dpm was broken since amdgpu_dpm_set_powergating_by_smu only covers gfx block. The change would add more IP block support in amdgpu_dpm_set_powergating_by_smu For GFX/UVD/VCN/VCE, if the new SMU driver is supported, invoke new power gate helper function smu_dpm_set_power_gate, otherwise, fallback to legacy powerplay helper function pp_set_powergating_by_smu. For other IP blocks always invoke legacy powerplay helper function. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add interface to get uclk dpm tablehersen wu2019-06-221-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | dc needs get uclk dpm table for bandwidth calculation Signed-off-by: hersen wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powrplay: add interface for dc to get max clock valueshersen wu2019-06-222-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dc (display component) needs maximum clock values of uclock, socclk, dcefclk, to calculate display bandwidth. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: notify smu with active display counthersen wu2019-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: allow dc request uclk changehersen wu2019-06-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: remove unsupport function set_thermal_fan_table for navi10Kevin Wang2019-06-211-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: enable BACO feature as WARJack Xiao2019-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It would hit SMU fw bug without BACO enablement when audio driver put audio device to D3 state. Before the bug in SMU fw get fixed, enable BACO feature as WAR. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabledKevin Wang2019-06-211-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | the uclk dpm feature is not work well on all navi10 asic, use pp feature mask module parameter to control it. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add ppt interface version logtiancyin2019-06-211-2/+4
| | | | | | | | | | | | | | | | | | | | | Include the interface version as well. Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay/vega20: use correct table indexAlex Deucher2019-06-211-5/+5
| | | | | | | | | | | | | | | | | | Use the SMU_* variant so we look up the correct index. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: disable fw dstate when gfxoff is enabledJack Xiao2019-06-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | SMU FW has bug that it would cause hung when both fw dstate and gfxoff are enabled at the same time. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: update smu11_driver_if_navi10.hJack Xiao2019-06-211-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.23 Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: simplified od_settings for each asicKevin Wang2019-06-214-87/+77
| | | | | | | | | | | | | | | | | | | | | | | | the od_settings is asic related data, so move it to asic file. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move od_default_setting callback to asic fileKevin Wang2019-06-214-50/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | the set default od_setting is asic related function, so move thic code to vega20_ppt file. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move od8_setting helper function to vega20_pptKevin Wang2019-06-213-39/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | these callback functions is only used for vega20 asic, to be compatible other asics,need to move this code to vega20_ppt file Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: fix clk type name error OD_SCLK OD_MCLKKevin Wang2019-06-212-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | use sw-smu clk type name to replace legacy clk type name Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: fix deadlock issue for smu_force_performance_levelKevin Wang2019-06-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | the smu->mutex is internal lock resource in sw-smu, some functions will use it at the same time, so it maybe will cause deadlock issue. this patch fix this issue in smu_force_performance_level function. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amdgpu/powerplay: add license to smu11 headerAlex Deucher2019-06-211-0/+22
| | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add interface to get uclk dpm tablehersen wu2019-06-212-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | dc needs get uclk dpm table for bandwidth calculation Signed-off-by: hersen wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: wake up azalia from d3 by sending smu messagehersen wu2019-06-214-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this is hw workaround to wake up azalia from d3. display asic and azalia are two different pci devices. while display asic wake from d3, current hw does not send signal to azalia. workaround: display driver ask smu send message to azalia device to let azalia wake up. Defintion of SMU message, like PPSMC_MSG_BacroAudioD3PME, is per asic. It is shared by different OS. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: notify smu with active display counthersen wu2019-06-213-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: allow dc request uclk changehersen wu2019-06-211-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)Kevin Wang2019-06-213-97/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | remove smu callback: get_mclk, get_sclk. because the function smu_get_dpm_freq_range has the same function. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: remove smu mutex lock in smu_hw_initKevin Wang2019-06-211-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | the smu mutex lock is unnecessary in smu hw init. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add thermal ctf support for navi10Kevin Wang2019-06-214-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | add sw-CTF support for navi10 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: fix no statements in function returning non-voidHawking Zhang2019-06-211-0/+2
| | | | | | | | | | | | | | | | | | | | | Add missing return (rebase fix). Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move get_thermal_temperature_range to ppt funcsHawking Zhang2019-06-213-81/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | The thermal policy could be ASIC specific ones and depends on structures in pptable. As a result, get_thermal_temperature_range should be implemented as ppt funcs instead of smu funcs Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move function thermal_get_temperature to veag20_pptKevin Wang2019-06-212-7/+48
| | | | | | | | | | | | | | | | | | | | | | | | the fcuntion thermal_get_temperature will be access SmuMetrics_t data, the data structure is asic related, so move vega20_ppt to implement. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move function get_metrics_table to vega20_pptKevin Wang2019-06-214-39/+42
| | | | | | | | | | | | | | | | | | | | | | | | the SmuMetrics_t table is asic related data structure. so move vega20_ppt file to implement. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: move power_dpm_force_performance_level to amdgpu_smu fileKevin Wang2019-06-213-48/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | because this callback is not asic related function, so move it to top code level to support more asic (eg: navi10) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: enable uclk dpm default on navi10Kevin Wang2019-06-211-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | enable uclk (mclk) dpm by default on navi10 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: enable ac/dc feature on navi10Kenneth Feng2019-06-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | enable ac/dc feature on navi10. currently we don't have the case to verify it. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: enable gfxclk ds,dcefclk ds and fw dstate on navi10Kenneth Feng2019-06-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on navi10, by default the below four features are enabled. gfxclk deep sleep: enabled and verified fw dstate: enabled and then soc ulv is verified dcefclk deep sleep: enabled and verified. notice that on different boards, due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk deep sleep kicking in. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add sclk sysfs interface support for navi10Kevin Wang2019-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | miss sclk support in force_clk_levels function Signed-off-by: Kevin Wang <kevin1.Wang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay/smu11: disable some pp features on navi10 A0 secure boardTao Zhou2019-06-211-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | disable DPM UCLK and SOC DS on A0 secure board Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay/smu11: add secure board check function (v2)Tao Zhou2019-06-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To determine whether the board is secure or not. v2: rebase (Alex) Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay/smu11: enable ds socclk by defaultTao Zhou2019-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable soc clk deep sleep. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: fix amdgpu_pm_info show gpu load errorKevin Wang2019-06-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | due to the smu dma/RTOS restriction, the interval of catching smu metric table should be more than 1ms. otherwise it will cause the gpu activity data corruption. Signed-off-by:Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: simplify the interface of get_gpu_powerKevin Wang2019-06-214-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | this callback function is only call in read_sensor in smu_v11_0.c, so move this code to {asic}_ppt.c to implement as asic related function. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: simplify the interface of get_current_activity_percentKevin Wang2019-06-214-34/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | this callback function is only call in read_sensor in smu_v11_0.c, so move this code to {asic}_ppt.c to implement as asic related function. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: fix dpm freq unit error (10KHz -> Mhz)Kevin Wang2019-06-212-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | the interface smu_v11_0_get_current_clk_freq should be return 10Khz not Mhz unit to adapt vega20 and navi10 asic at the same time. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | amd/powerplay: update the vcn pgKenneth Feng2019-06-212-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | update the vcn pg function in navi10. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function read_sensor for navi10Kevin Wang2019-06-211-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | add callback function read_sensor for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function set_watermarks_table function for navi10Kevin Wang2019-06-211-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | add callback function set_watermarks_table for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function notify_smc_display_config_change for navi10Kevin Wang2019-06-211-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | add callback function notify_smc_display_config_change for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function get_profiling_clk_mask for navi10Kevin Wang2019-06-211-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | add callback function get_profiling_clk_mask for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add funciton get[set]_power_profile_mode for navi10 (v2)Kevin Wang2019-06-211-0/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add callback function get[set]_power_profile_mode for navi10 asic v2: fix smu_update_table for rebase (Alex) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function get_workload_type_map for swsmuKevin Wang2019-06-214-37/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | 1.add new callback function get_workload_byte for smu 2.remove old workload map function Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: remove upload_dpm_level function for vega20Kevin Wang2019-06-212-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | the function upload_dpm_level is an internal function, so remove public interface. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | drm/amd/powerplay: add function get_fan_speed_percent for navi10Kevin Wang2019-06-211-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | add callback function get_fan_speed_percent for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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