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* drm/amd/powerplay: print the pptable providerXiaojie Yuan2019-11-061-0/+2
| | | | | | | | So we know where the tables came from. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2Evan Quan2019-11-064-4/+35
| | | | | | | | | | Add xgmi pstate setting on powerplay routine. V2: split the change of is_support_sw_smu_xgmi into a separate patch Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update is_sw_smu_xgmi checkEvan Quan2019-11-061-1/+1
| | | | | | | | | Add check for is_sw_smu routine and drop check for amdgpu_dpm which seems non-sense. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Make two functions staticYueHaibing2019-10-281-2/+2
| | | | | | | | | | | | | Fix sparse warnings: drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2050:5: warning: symbol 'arcturus_i2c_eeprom_control_init' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2068:6: warning: symbol 'arcturus_i2c_eeprom_control_fini' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay/vega10: allow undervolting in p7Pelle van Gils2019-10-281-3/+1
| | | | | | | | | | | The vega10_odn_update_soc_table() function does not allow the SCLK dependent voltage to be set for power-state 7 to a value below the default in pptable. Change the for-loop condition to allow undervolting in the highest state. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205277 Signed-off-by: Pelle van Gils <pelle@vangils.xyz> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Disable gfx CGPG when suspend smuchen gong2019-10-281-0/+2
| | | | | | | | | | | | | | | | | if no disable gfx CGPG when suspend smu, enabling gfx CGPG will fail when resume smu. Platform: Renoir dmesg log information: [ 151.844110 ] amdgpu: [powerplay] SMU is resuming... [ 151.844116 ] amdgpu: [powerplay] dpm has been disabled [ 151.844604 ] amdgpu: [powerplay] Failed to send message 0x2f,response 0xfffffffb param 0x1 [ 151.844605 ] amdgpu: [powerplay] SMU is resumed successfully! Signed-off-by: chen gong <curry.gong@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: modify the parameters of SMU_MSG_PowerUpVcn to 0chen gong2019-10-251-1/+1
| | | | | | | | The parameters what SMU_MSG_PowerUpVcn need is 0, not 1 Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: correct current clock level label for ArcturusEvan Quan2019-10-251-8/+16
| | | | | | | | | For dpm disabled case, it's assumed the only one support clock level is always current clock level. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: skip unsupported clock limit settings on Arcturus V2Evan Quan2019-10-251-116/+26
| | | | | | | | | | | For Arcturus, clock limit settings on uclk/socclk/fclk domains are not supported. V2: simplify the code to support both SGPU and MGPU cases Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Add EEPROM I2C read/write support to Arcturus.Andrey Grodzovsky2019-10-251-0/+229
| | | | | | | | | | | The communication is done through SMU table and hence the code is in powerplay. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Add interface for I2C transactions to SMU.Andrey Grodzovsky2019-10-251-0/+9
| | | | | | | | | | Will be used by Arcturus support for RAS page retirement. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: clear the swSMU code layerEvan Quan2019-10-2511-297/+498
| | | | | | | | | | | With this cleanup, the APIs from amdgpu_smu.c will map to ASIC specific ones directly. Those can be shared around all SMU V11/V12 ASICs will be put in smu_v11_0.c and smu_v12_0.c respectively. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: split out those internal used swSMU APIs V2Evan Quan2019-10-259-160/+212
| | | | | | | | | | | | Those swSMU APIs used internally are moved to smu_internal.h while others are kept in amdgpu_smu.h. V2: give a better name smu_internal.h for the place to hold those internal APIs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add lock protection for swSMU APIs V2Evan Quan2019-10-258-177/+762
| | | | | | | | | | | | | | | | This is a quick and low risk fix. Those APIs which are exposed to other IPs or to support sysfs/hwmon interfaces or DAL will have lock protection. Meanwhile no lock protection is enforced for swSMU internal used APIs. Future optimization is needed. V2: strip the lock protection for all swSMU internal APIs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update Arcturus driver smu interface XGMI link partEvan Quan2019-10-252-9/+21
| | | | | | | | To fit the latest SMU firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: use local renoir array sizes for clock fetchingAlex Deucher2019-10-251-4/+4
| | | | | | | | To avoid walking past the end of the arrays since the PP_SMU defines don't match the renoir defines. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vi: silence an uninitialized variable warningDan Carpenter2019-10-251-0/+1
| | | | | | | | | | | | Smatch complains that we need to initialized "*cap" otherwise it can lead to an uninitialized variable bug in the caller. This seems like a reasonable warning and it doesn't hurt to silence it at least. drivers/gpu/drm/amd/amdgpu/vi.c:767 vi_asic_reset_method() error: uninitialized symbol 'baco_reset'. Fixes: 425db2553e43 ("drm/amdgpu: expose BACO interfaces to upper level from PP") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: implement interface pp_power_profile_modePrike Liang2019-10-171-0/+34
| | | | | | | | implement get_power_profile_mode for getting power profile mode status. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: No need to check gfxoff status after enable gfxoff featurechen gong2019-10-171-9/+0
| | | | | | | | | | | | | | smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch. As to when GPU get into "GFXoff" will be up to drawing load. So we can not sure which state GPU should be in after enable gfxoff feature. Signed-off-by: chen gong <curry.gong@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: bug fix for memory clock request from displayKenneth Feng2019-10-171-0/+2
| | | | | | | | | | | | In some cases, display fixes memory clock frequency to a high value rather than the natural memory clock switching. When we comes back from s3 resume, the request from display is not reset, this causes the bug which makes the memory clock goes into a low value. Then due to the insuffcient memory clock, the screen flicks. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix S3 failed as RLC safe mode entry stucked in polloing gfx acqPrike Liang2019-10-171-0/+4
| | | | | | | | | Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response. The patch can fix VCN IB test failed and DAL get dispaly count failed issue. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: wire up BACO to powerplay API for smu7Alex Deucher2019-10-151-0/+4
| | | | | | | | Wire up the powerplay callbacks for for BACO for smu7 devices. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: split out common smu7 BACO codeAlex Deucher2019-10-1511-149/+132
| | | | | | | | | Several of the BACO functions are common across smu7-based asics. Split the common code out. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add support for BACO on CIAlex Deucher2019-10-153-1/+261
| | | | | | | | This adds BACO support for CI asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add support for BACO on FijiAlex Deucher2019-10-153-1/+261
| | | | | | | | This adds BACO support for Fiji asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add support for BACO on VegaMAlex Deucher2019-10-151-3/+39
| | | | | | | | This adds BACO support for VegaM asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add support for BACO on polarisAlex Deucher2019-10-153-1/+251
| | | | | | | | This adds BACO support for Polaris asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add support for BACO on IcelandAlex Deucher2019-10-151-6/+48
| | | | | | | | This adds BACO support for Iceland asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add support for BACO on tongaAlex Deucher2019-10-153-1/+254
| | | | | | | | This adds BACO support for Tonga. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add core support for pre-SOC15 bacoAlex Deucher2019-10-152-0/+32
| | | | | | | | This adds core support for BACO on pre-vega asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: remove in_baco_reset hackAlex Deucher2019-10-151-2/+2
| | | | | | | | It was a vega20 specific hack. Check if we are in reset and what reset method we are using. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add renoir funcs to support dcHersen Wu2019-10-154-48/+138
| | | | | | | | | | | | there are two paths for renoir dc access smu. one dc access smu directly using bios smc interface: set disply, dprefclk, etc. another goes through pplib for get dpm clock table and set watermmark. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable Arcturus runtime VCN dpm on/offEvan Quan2019-10-151-0/+30
| | | | | | | | Enable runtime VCN DPM on/off on Arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: bug fix for pcie parameters overrideKenneth Feng2019-10-155-44/+98
| | | | | | | | | | | | | | | | | | | | | Bug fix for pcie paramerers override on swsmu. Below is a scenario to have this problem. pptable definition on pcie dpm: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:4, pcie lanes: *16 Then if we have a system only have the capbility: pcie gen speed: 3, pcie lanes: *8, we will override dpm 1 to pcie gen speed 3, pcie lanes *8. But the code skips the dpm 0 configuration. So the real pcie dpm parameters are: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:3, pcie lanes: *8 Then the wrong pcie lanes will be toggled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add BACO platformCaps for VEGA20Le Ma2019-10-151-0/+3
| | | | | | | | | BACO reset is needed for RAS recovery. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: send EnterBaco msg with argument as RAS recovery flagLe Ma2019-10-151-3/+8
| | | | | | | | | 1 indicates RAS recovery flag in SMU FW. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: avoid disabling ECC if RAS is enabled for VEGA20Le Ma2019-10-151-5/+7
| | | | | | | | | | | Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting for ECC supported SKU. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: re-enable FW_DSTATE feature bitXiaojie Yuan2019-10-151-4/+1
| | | | | | | | | SMU firmware has fix the bug, so remove this workaround. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swSMU: custom UMD pstate peak clock for navi14Kevin Wang2019-10-152-14/+45
| | | | | | | | | | | | | | add navi14 umd pstate peak clock support. NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK 1670 MHz NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK 1448 MHz NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK 1181 MHz NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK 1717 MHz NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK 1448 MHz Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable df cstate control on swSMU routineEvan Quan2019-10-154-1/+51
| | | | | | | | | Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable df cstate control on powerplay routineEvan Quan2019-10-154-1/+40
| | | | | | | | | Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/swSMU/navi: add feature toggles for more thingsAlex Deucher2019-10-101-6/+18
| | | | | | | | Add toggles for more power features. Helpful in debugging. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: Use swap() where appropriateVille Syrjälä2019-10-102-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | @swap@ identifier TEMP; expression A,B; @@ - TEMP = A; - A = B; - B = TEMP; + swap(A, B); @@ type T; identifier swap.TEMP; @@ ( - T TEMP; | - T TEMP = {...}; ) ... when != TEMP Cc: Rex Zhu <rex.zhu@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add more feature bitsXiaojie Yuan2019-10-101-1/+4
| | | | | | | | | Additional features that can be enabled in the SMU. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: fix typo in mvdd table setupAlex Deucher2019-10-102-2/+2
| | | | | | | | | | | | | | Polaris and vegam use count for the value rather than level. This looks like a copy paste typo from when the code was adapted from previous asics. I'm not sure that the SMU actually uses this value, so I don't know that it actually is a bug per se. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609 Reported-by: Robert Strube <rstrube@gmail.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Fix error handling in smu_init_fb_allocations()Dan Carpenter2019-10-071-3/+2
| | | | | | | | | | | | | | | The error handling is off by one. We should not free the first "tables[i].bo" without decrementing "i" because that might result in a double free. The second problem is that when an error occurs, then the zeroth element "tables[0].bo" isn't freed. I had make "i" signed int for the error handling to work, so I just updated "ret" as well as a clean up. Fixes: f96357a991b9 ("drm/amd/powerplay: implement smu_init(fini)_fb_allocations function") Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: unlock on error in smu_resume()Dan Carpenter2019-10-071-1/+1
| | | | | | | | | This function needs to drop the mutex before returning. Fixes: f7e3a5776fa6 ("drm/amd/powerplay: check SMU engine readiness before proceeding on S3 resume") Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Drop unused variable and statementAustin Kim2019-10-031-2/+0
| | | | | | | | | | | | | | | | | | Even though 'smu8_smu' is declared, it is not used after below statement. smu8_smu = hwmgr->smu_backend; So 'unused variable' could be safely removed to stop warning message as below: drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu8_smumgr.c:180:22: warning: variable ‘smu8_smu’ set but not used [-Wunused-but-set-variable] struct smu8_smumgr *smu8_smu; ^ Signed-off-by: Austin Kim <austindh.kim@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: initlialize smu->is_apu is false by defaultKevin Wang2019-10-031-0/+1
| | | | | | | | | | | | | | | the member of is_apu in smu_context need to initlialize by default. set default value is false (dGPU) for patch: drm/amd/powerplay: bypass dpm_context null pointer check guard for some smu series Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: update the interface for getting dpm full scale clock ↵Prike Liang2019-10-033-17/+34
| | | | | | | | | | frequency Update get_dpm_uclk_limited to get more clock type full scale dpm frequency. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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