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* drm/amdgpu: implement querying ras error count for mmhubTao Zhou2019-08-152-0/+243
| | | | | | | | get mmhub ea ras error count by accessing EDC_CNT register Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add renoir header files (v2)Huang Rui2019-08-122-0/+1202
| | | | | | | | | | | This patch add all renoir header files. v2: clean up headers (Alex) Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan2019-08-022-0/+41
| | | | | | | gc 10.1.2 introduced this new register Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add ip offset header for navi12 (v2)Xiaojie Yuan2019-08-021-0/+1119
| | | | | | | | | | This adds the absolute offsets of each IP regiser block. v2: Squash in MP1 update Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdkfd: Extend CU mask to 8 SEs (v3)Jay Cornwall2019-08-021-4/+4
| | | | | | | | | | | Following bitmap layout logic introduced by: "drm/amdgpu: support get_cu_info for Arcturus". v2: squash in fixup for gfx_v9_0.c (Alex) v3: squash in debug print output fix Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Update NBIO headers to add TXCLK3/4Kent Russell2019-08-022-0/+36
| | | | | | | | These are added for VG20, and are needed for PCIe bandwidth. Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include: add define of TCP_EDC_CNT_NEWDennis Li2019-07-311-0/+2
| | | | | | | Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include: add bitfield define for EDC registersDennis Li2019-07-311-0/+157
| | | | | | | | | Add EDC registers to support VEGA20 RAS Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add umc v6_1_1 IP headersHawking Zhang2019-07-312-0/+122
| | | | | | | | the change introduces IP headers for unified memory controller (umc) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add rsmu v_0_0_2 ip headersHawking Zhang2019-07-312-0/+59
| | | | | | | | | remote smu (rsmu) is a sub-block used as ip register interface, error handling, reset generation.etc Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add new sensor type for VCN powergate statusEvan Quan2019-07-301-0/+1
| | | | | | | | | VCN is widely used in new ASICs and different from tranditional UVD and VCE. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/include: adjust base offset of SMUIO and THM for ArcturusLe Ma2019-07-301-6/+2
| | | | | | | | | | Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20 reusable for Arcturus, align this base offset with Vega20. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add smcdpminfo table v4_6 supportEvan Quan2019-07-301-0/+86
| | | | | | | | New smcdpminfo table used in arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add a new interface to set the mp1 stateAlex Deucher2019-07-301-0/+8
| | | | | | | | | This is required for certain cases such as various GPU resets (mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into the appropriate state for when the hw is re-initialized. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: exposing fica registers to df offsetsJonathan Kim2019-07-181-0/+4
| | | | | | | | | exposing fica registers to poll df pie data for xgmi error counters for vega20. Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: correct SW SMU valid mapping checkEvan Quan2019-07-181-0/+1
| | | | | | | | | Current implementation is not actually able to detect invalid message/table/workload mapping. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/: add clientID for 2nd vcn instanceJames Zhu2019-07-181-1/+1
| | | | | | | | add clientID for 2nd vcn instance, remove unused SOC15_IH_CLIENTID_SYSHUB. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VMC1 interrupt client id for ArcturusLe Ma2019-07-181-0/+1
| | | | | | | | New IH client id for VMC1. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add SDMA 2~7 interrupt client id for ArcturusLe Ma2019-07-181-1/+7
| | | | | | | | Add new client ids. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add Arcturus ip_offset header (v3)Le Ma2019-07-181-0/+1654
| | | | | | | | | | | | Provides the absolute offsets of the IP register blocks. v2: update chip name in source code v3: squash in MP offset updates (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VCN2.5 headersLeo Liu2019-07-182-0/+4588
| | | | | | | | VCN is the multi-media block. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add sdma 4.2.2 header files for ArcturusLe Ma2019-07-1816-0/+32046
| | | | | | | | SDMA is the system DMA block. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add mmhub 9.4.1 header files for AcrturusLe Ma2019-07-183-0/+56570
| | | | | | | | mmhub is the GPU memory hub used by SDMA and VCN. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/soc15: initialize reg base for navi14 (v2)Xiaojie Yuan2019-07-181-0/+1119
| | | | | | | | | | | Initialize the IP register base offsets for navi14. v2: squash in MP, CLK, THM updates Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: increase the SMU msg response waiting timeEvan Quan2019-07-111-1/+1
| | | | | | | | | | This is expected to fix some mode1 reset failures. And this affects SMU part only as the timeout setting for other parts is controlled by a different macro. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: make athub pg bit configured by pg_flagsHuang Rui2019-06-251-1/+2
| | | | | | | | | The athub pg features enabling should be indicated by pg_flags. Reported-by: Lijo Lazar <Lijo.Lazar@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Create DWB resource for DCN2Charlene Liu2019-06-222-0/+20
| | | | | | | | | | | [Description] dcn20 has num_dwb =1 in the res cap, but not created. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Duke Du <Duke.Du@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/mes10.1: add ip block mes10.1 (v2)Jack Xiao2019-06-211-1/+2
| | | | | | | | | | | MES takes over the scheduling capability of GFX and SDMA, add MES as a standalone ip. v2: squash in updates (Alex) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/discovery: update definition for struct die_headerXiaojie Yuan2019-06-211-2/+2
| | | | | | | | Update to latest spec. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/discovery: add harvest info data tableXiaojie Yuan2019-06-211-1/+17
| | | | | | | | Add support for the harvest tables. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/discovery: update definitions of table_info and binary_headerXiaojie Yuan2019-06-211-0/+4
| | | | | | | | Use the proper definitions. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/discovery: add ip discovery initial supportXiaojie Yuan2019-06-211-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IP discovery table lists is populated by the psp at power on and includes all of the hw details on the board: - List of IPs and MMIO offsets - IP harvest details - IP configuration details v2: prefix struct and function names with 'amdgpu' v3: read table binary from vram using mmMM_INDEX and mmMM_DATA update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR) add 'instance_number' field per ip info consider endianness and replace uint8/16/32_t with u8/16/32 initialize register base addresses initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw get major and minor version using a single api don't expose internal data structures in amdgpu_discovery.h v4: RCC_CONFIG_MEMSIZE is in MB units hold mmio_idx_lock while reading ip discovery binary v5: pick out discovery.h as a cross-OS header do structure pointer cast directly consider endianness while using the member of structure convert base addresses to dword at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the top of the frame buffer (just below the reserved regions for PSP & SMU). ip discovery data table includes the collection of each ip's identification number, base addresses, version number, and harvest setting placeholder. gc data table includes gfx info structure. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/Hawking Zhang2019-06-201-0/+0
| | | | | | | | interrupt source packet definitions for the display block (DCN). Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add irq sources for vcn v2_0 (v2)Hawking Zhang2019-06-201-0/+32
| | | | | | | | | | Add the interrupt source packet definitions. v2: update (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add irq sources for sdma v5_0Hawking Zhang2019-06-202-0/+87
| | | | | | | | Add the interrupt source packet definitions. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add irq sources for gfx v10_1Hawking Zhang2019-06-201-0/+53
| | | | | | | | Add the interrupt source packet definitions. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/athub2: enable athub2 clock gatingJack Xiao2019-06-201-0/+2
| | | | | | | | | Enable athub2 clock gating and light sleep Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add flag to support IH clock gatingHawking Zhang2019-06-201-0/+1
| | | | | | | | Add new flag for IH (interrupt handler) clockgating. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add new HDP CG flagsHawking Zhang2019-06-201-0/+2
| | | | | | | | | | | | | HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/ DS (Deep Sleep)/SD (Shut Down) modes are supported. However, only one of these modes can be enabled at one time. There is no dynamic power mode switch support. clock/power gating has to be disabled before making any power mode change. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add v10 structs header (v2)Huang Rui2019-06-201-0/+1258
| | | | | | | | | | Header for CP structures (MQD, etc.) V2: squash in updates Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add navi10 ip offset headerHawking Zhang2019-06-202-1/+858
| | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: atomfirmware.h updates for navi10Hawking Zhang2019-06-201-8/+180
| | | | | | | Updated tables for Navi10. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add navi10 enums headerHawking Zhang2019-06-201-0/+22764
| | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add SMUIO 11.0 register headersHawking Zhang2019-06-202-0/+1012
| | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add OSS 5.0 register headersHawking Zhang2019-06-202-0/+1658
| | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add MMHUB 2.0 register headersHawking Zhang2019-06-203-0/+10293
| | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add GC 10.1 register headers (v4)Hawking Zhang2019-06-203-0/+61330
| | | | | | | | | v2: Update regs (Alex) v3: More updates (Alex) v4: more updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VCN 2.0 register headersHawking Zhang2019-06-202-0/+4823
| | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add NBIO 2.3 register headersHawking Zhang2019-06-203-0/+153523
| | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add MP 11.0 register headersHawking Zhang2019-06-201-0/+429
| | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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