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* | | | | drm/amd/display: add i2c_hw_Status check to make sure as HW I2c in useDerek Lai2019-06-112-27/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add i2c_hw_Status check to make sure when HW i2c is in use. 2. Don't reset HW engine in is_hw_busy() and instead do this in process_transaction() because SW i2c does not check if hw i2c is in use Signed-off-by: Derek Lai <Derek.Lai@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Dont aser if DP_DPHY_INTERNAL_CTRLEric Bernstein2019-06-111-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to assert just return Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: 3.2.33Aric Cyr2019-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: add some math functions for dcn_calc_mathCharlene Liu2019-06-113-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement floor, ceil, and fabs Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Copy stream updates onto streamsNicholas Kazlauskas2019-06-111-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Almost every function in DC that works with stream state expects that the current state on the stream is the one that it should be writing out. These functions are typically triggered by specifying a particular stream update - but the actual contents of the stream update itself are ignored, leaving it to the DM to actually update the stream state itself. The problem with doing this in DM is a matter of timing. On Linux most of this is incorrectly done in atomic check, when we actually want it to be done during atomic commit tail while access to DC is locked. To give an example, a commit requesting to modify color management state for DM could come in, be rejected, but still have modified the actual system state for the stream since it's shared memory. The next time color management gets programmed it'll use the rejected color management info - which might not even still be around if it's a custom transfer function. So a reasonable place to perform this is within DC itself and this is the model that's currently in use for surface updates. DC can even compare the current system state to the incoming surface update to determine update level, something that can't currnetly be done with the framework for stream updates. [How] Duplicate the framework used for surface updates for stream updates as well. Copy all the updates after checking the update type. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Update link rate from DPCD 10Wesley Chalmers2019-06-111-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] Some panels return a link rate of 0 (unknown) in DPCD 0. In this case, an appropriate mode cannot be set, and certain panels will show corruption as they are forced to use a mode they do not support. [HOW] Read DPCD 10 in the case where supported link rate from DPCD 0 is unknown, and pass that value on to the reported link rate. This re-introduces behaviour present in previous versions that appears to have been accidentally removed. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: fix resource saving missing when power state switchTao.Huang2019-06-111-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tao.Huang <Tao.Huang@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Set default ABM level to module parameterNicholas Kazlauskas2019-06-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The module parameter to specify the default ABM level is now defined, so hook it up in DM. [How] On connector reset specify the default level. DC will program this as part of the modeset since it gets passed onto the stream in dm_update_crtc_state. It's only set for eDP connectors, but it doesn't matter if this is specified for connectors or hardware that doesn't support ABM. It's DC's responsibility to check that ABM can be set or adjusted, and DC does check that the DMCU firmware is running and if there's backlight control available. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Enable fast plane updates when state->allow_modeset = trueNicholas Kazlauskas2019-06-111-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Whenever the a modeset is allowed (but not neccessarily required) we currently recreate all the planes in the state. Most IGT tests and legacy IOCTLs create atomic commits with this flag set, so the pipes are often unnecessarily reprogrammed. Poor performance and stuttering can occur when many of these commits are frequently issued. This flag was needed when the appropriate conditions for checking whether the planes needed a reset were not in place, but should_reset_plane should cover everything needed now. [How] Drop the check for state->allow_modeset in should_reset_plane. All planes on a CRTC should reset in the following conditions: - The CRTC needs a modeset - The CRTC degamma changes - Planes are added or removed to the CRTC These conditions are all covered in should_reset_plane. We still can't drop the format change check in should_reset_plane since fill_dc_plane_info_and_addr isn't called when validating the state, so we can't tell if a FULL update is needed or not. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Use current connector state if NULL when checking bpcNicholas Kazlauskas2019-06-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The old logic for checking which output depth to use relied on using the current connector state rather than the new proposed state. This was a problem when performing atomic commits since we weren't verifying it against the incoming max_requested_bpc. But switching this to only use the new state and not the current state breaks filtering modes - it'll always assume that the maximum bpc supported by the display is in use, which will cause certain modes like 1440p@144Hz to be filtered even when using 8bpc. [How] Still use the connector->state if we aren't passed an explicit state. This will respect the max_bpc the user currently has when filtering modes. Also remember to reset the default max_requested_bpc to 8 whenever connector reset is called to retain old behavior when using the new property. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110845 Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Always allocate initial connector state stateNicholas Kazlauskas2019-06-111-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Unlike our regular connectors, MST connectors don't start off with an initial connector state. This causes a NULL pointer dereference to occur when attaching the bpc property since it tries to modify the connector state. We need an initial connector state on the connector to avoid the crash. [How] Use our reset helper to allocate an initial state and reset the values to their defaults. We were already doing this before, just not for MST connectors. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Add connector debugfs for "output_bpc"Nicholas Kazlauskas2019-06-111-2/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] This will be useful for verifying whether we enter the correct output color depth from IGT. [How] Locks the connector and associated CRTC if available and outputs the current and maximum output bpc values. Example: cat /sys/kernel/debug/dri/0/DP-1/output_bpc Current: 8 Maximum: 10 v2: Drop unneeded connector status check Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Add back missing hw translate init for DCN1_01Nicholas Kazlauskas2019-06-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] DCN_VERSION_1_01 is no longer handled in the dal_hw_translate_init switch since it was inadvertently dropped in the patch that removed the unnecessary DCN1_01 guards. This caused numerous regressions on DCN1_01 when loading the driver. [How] Add it back. Fixes: 97df424fe7a7 ("drm/amd/display: Drop DCN1_01 guards") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | drm/amd/display: Don't set mode_changed=false if the stream was removedNicholas Kazlauskas2019-06-111-1/+11
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] When switching from vt to desktop with EDID emulation we can receive an atomic commit such that we have a crtc where mode_changed = true. During the dm_update_crtc_state disable pass we remove the stream from the context and free it on the dm_new_crtc_state. During the enable pass we compare the new provisional stream to the dm_old_crtc_state->stream and determine that the stream is unchanged and no scaling has been changed. Following this, new_crtc_state->mode_changed is then set to false. The connectors haven't changed and the CRTC active state hasn't changed so drm_atomic_crtc_needs_modeset returns false, so we jump to skip_modeset and we hit: BUG_ON(dm_new_crtc_state->stream == NULL); ...since the old stream is gone from the context and the new stream is also still NULL. [How] Ensure that we still a stream to reuse before checking if we can reuse the old stream without a full modeset. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | Merge branch 'drm-next-5.3' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2019-06-0669-1917/+2773
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next amdgpu: - Revert timeline support until KHR is ready - Various driver reload fixes - Refactor clock handling in DC - Aux fixes for DC - Bandwidth calculation updates for DC - Fix documentation due to file rename - RAS fix - Fix race in late_init ttm: - Allow for better forward progress when there is heavy memory contention Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190606032537.6939-1-alexander.deucher@amd.com
| * | | | drm/amdgpu/display: Drop some new CONFIG_DRM_AMD_DC_DCN1_01 guardsAlex Deucher2019-06-052-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These got added back by subsequent merges accidently. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: use ttm_eu_reserve_buffers instead of amdgpu_bo_reserve v2Chunming Zhou2019-05-311-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add ticket for display bo, so that it can preempt busy bo. v2: fix stupid rebase error Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/display: Fix reload driver errorEmily Deng2019-05-311-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue: Will have follow error when reload driver: [ 3986.567739] sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:07.0/drm_dp_aux_dev' [ 3986.567743] CPU: 6 PID: 1767 Comm: modprobe Tainted: G OE 5.0.0-rc1-custom #1 [ 3986.567745] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 3986.567746] Call Trace: ...... [ 3986.567808] drm_dp_aux_register_devnode+0xdc/0x140 [drm_kms_helper] ...... [ 3986.569081] kobject_add_internal failed for drm_dp_aux_dev with -EEXIST, don't try to register things with the same name in the same directory. Reproduce sequences: 1.modprobe amdgpu 2.modprobe -r amdgpu 3.modprobe amdgpu Root cause: When unload driver, it doesn't unregister aux. v2: Don't use has_aux Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: program manual trigger only for bottom most pipeAric Cyr2019-05-311-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We only want to manual trigger end-of-frame when the bottom-most pipe is flipped to prevent overlays from ending the frame too early. [How] Check that the manual trigger is only firing on bottom plane. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: CS_TFM_1D only applied post EOTFKrunoslav Kovac2019-05-311-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There's some unnecessary mem allocation for CS_TFM_ID. What's worse, it depends on LUT size and since it's 4K for CS_TFM_1D, it is 16x bigger than in regular case when it's actually needed. This leads to some crashes in stress conditions. [How] Skip ramp combining designed for RGB256 and DXGI gamma with CS_TFM_1D. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Reset planes for color management changesNicholas Kazlauskas2019-05-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] For commits with allow_modeset=false and CRTC degamma changes the planes aren't reset. This results in incorrect rendering. [How] Reset the planes when color management has changed on the CRTC. Technically this will include regamma changes as well, but it doesn't really after legacy userspace since those commit with allow_modeset=true. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Increase Backlight Gain Step SizeEryk Brol2019-05-312-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Some backlight tests fail due to backlight settling taking too long. This happens because the step size used to change backlight levels is too small. [How] 1. Change the size of the backlight gain step size 2. Change how DMCU firmware gets the step size value so that it is passed in by driver during DMCU initn Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: fix issues with bad AUX reply on some displaysAnthony Koo2019-05-311-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Some displays take some time to power up AUX CH once they are put into D3 state via write to DPCD 600h=2. Interestingly enough, some display may simply NACK, but some might also ACK with a bunch of 0s, which can cause issues with receiver cap retrieval. Note that not all DPCD address return 0s, but in particular it has been observed on some higher DPCD address such as DPCD 2200h, etc. [How] Based on spec, receiver will monitor differential signal while in D3 and AUX CH is in low power mode. When detected, it may allow up to 1 ms to power up AUX CH and reply. If we read Sink power state D3, we should add 1 ms delay to satisfy this spec requirement. Signed-off-by: Anthony Koo <anthony.koo@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Refactor DIO stream encoderEric Bernstein2019-05-314-30/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Pull duplicate audio_clock_info struct to stream_encoder.h * Generalize sec_gsp7* to sec_gsp_pps* * Expose enc1 and enc2 stream encoder audio funcs Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Modified AUX_DPHY_RX_CONTROL0Daniel He2019-05-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Description] This is cause by failing to read link caps from driver. Signed-off-by: Daniel He <daniel.he@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Add writeback_config to VBA varsIlya Bakoulin2019-05-311-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding writeback_config enum to vba_vars_st, replacing old flag. Initialize to dm_normal. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Refactor clk_mgr functionsEric Yang2019-05-315-52/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] * Pull get_active_display_cnt out to clk_mgr. * Pull out shared logic in set_dispclk and set_dprefclk Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Fix type of pp_smu_wm_set_range structEric Yang2019-05-311-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Value read from SMU is 16 bits, not 32. [How] Fix type, and add wm_type enum in preparation for future interfaces. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: do not power on eDP power rail earlyAnthony Koo2019-05-312-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Modern Standby may toggle display adapter state between D0 and D3 state unpredictably. But events that cause transition to D0 are not always resulting in a display light up scenario. Modern eDP panels should be able to power on panel logic quickly upon VDD going high. Based on spec, the T3 time between VDD on and HPD high can be between 0 and 80 ms. Doing any tricky sorts of optimization by powering on panel VDD early during D0 transition on can negatively impact other features due to unnecessary power drain and toggling when final system state does not intend for the panel to be lit up. We need OEMs to source higher end panels that have T3 time close to 0 if they want quick S3/Modern Standby resume times. [How] Remove panel VDD power on in init_hw Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: fix crash on setmode when mode is close to bw limitSu Sung Chung2019-05-311-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] during It's possible to call dcn_validate_bandwidth with no plane. In that case, as we are only intersted in if output timing is supported or not, even if we cannot support native resolution, we still want to support lower resolution if it is valid [how] if there exist no surface, make viewport/rec_out size at max 1080p. It is already known that 1080p x 6(max # of pipes) is supported, so if we fail validation, it is because of the stream Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: fix calculation of total_data_read_bandwidthSu Sung Chung2019-05-311-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] by adding fast_validate flag, we are skipping some portion of dcn_validate_bandwidth code that is not necessary for mode validation. However we have a bug where it does not calculate v->total_data_read_bandwidth, which is one of the factors determines the result of the validation, and therefore report false positive during mode validation. [how] add calculation of v->total_data_read_bandwidth outside of the region that is guarded by fast_validate flag Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: 3.2.32Aric Cyr2019-05-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Move link functions from dc to dc_linkChris Park2019-05-312-123/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] link-specific functions should reside in dc_link.c [How] Move them there. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Add min_dcfclk_mhz field to bb overridesJun Lei2019-05-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add min_dcfclk_mhz to bounding box overrides. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: move clk_mgr files to right placeEric Yang2019-05-3122-21/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Better organization [How] Move clk_mgr files under dc/clk_mgr Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: disable PSR/ABM before destroy DMCU structPaul Hsieh2019-05-315-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] 1. DMCU is not running on some platform but driver still send ABM command. It may cause assert due to DMCU is not alive. 2. To make sure PSR disable when driver disable [How] 1. Add dmcu_is_running in ABM struct, driver can check this flag to determine driver should send ABM command or not. 2. Send PSR disable command when destroy PSR Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Ensure DRR triggers in BPEryk Brol2019-05-317-22/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP. [How] 1. Remove DRR programming during flip 2. Setup manual trigger for DRR event and trigger it after surface programming is complete Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Add GSL source select registersKrunoslav Kovac2019-05-311-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GSL is a form of locking that can be used to synchronize pipes in a pipe-split configurations when async flip is used. Add the registers here. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Disable audio stream only if it's currently enabledEryk Brol2019-05-312-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Previously there were 2 consecutive calls being made to disable audio stream. The first one disabled the audio stream, and the second one went through and also tried to disable the audio stream causing BACO entry issues due to the ASIC appearing busy. [How] 1. Add a status field to the audio struct which stores enabled/disabled info 2. In the calls to enable/disable audio stream check if we're already in the desired state before executing the function Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: assign new stream id in dc_copy_streamWenjing Liu2019-05-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] stream id should uniquely identify an instance of stream. the copy constructor should be treated as a new stream instance. [how] assign a new stream id in this copy constructor. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Move CLK_BASE_INNER macroEric Yang2019-05-312-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This macro is specificly used by RV1. Move it to the appropriate location. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Implement CM dealpha and bias interfacesGary Kattan2019-05-312-14/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add vtable entries for de-alpha and bias color management interfaces. Move piece-wise transfer function registers to a helper list for future reuse. Signed-off-by: Gary Kattan <gary.kattan@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: Don't use ROM for output TF if GAMMA_CS_TFM_1DHugo Hu2019-05-311-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can’t use hardcoded SRGB ROM for output TF if we have GAMMA_CS_TFM_1D (unless we know 1D LUT is identity), so we never want to return here early. We apply the LUT part of ColorTransform3x4 only in apply_lut_1d() which is called near the end of that function. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: make clk mgr soc specificEric Yang2019-05-3143-1175/+1674
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool. [How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | | | | Merge tag 'drm-misc-next-2019-06-05' of ↵Dave Airlie2019-06-061-4/+151
|\ \ \ \ \ | |/ / / / |/| / / / | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.3: UAPI Changes: Cross-subsystem Changes: - Add devicetree bindings for new panels. - Convert allwinner's DT bindings to a schema. - Drop video/hdmi static functions from kernel docs. - Discard old fence when reserving space in reservation_object_get_fences_rcu. Core Changes: - Add missing -ENOMEM handling in edid loading. - Fix null pointer deref in scheduler. - Header cleanups, making them self-contained. - Remove drmP.h inclusion from core. - Fix make htmldocs warning in scheduler and HDR metadata. - Fix a few warnings in the uapi header and add a doc section for it. - Small MST sideband error handling fix. - Clarify userspace review requirements. - Clarify implicit/explicit fencing in docs. - Flush output polling on shutdown. Driver Changes: - Small cleanups to stm. - Add new driver for ST-Ericsson MCDE - Kconfig fix for meson HDMI. - Add support for Armadeus ST0700 Adapt panel. - Add KOE tx14d24vm1bpa panel. - Update timings for st7701. - Fix compile error in mcde. - Big series of tc358767 fixes, and enabling support for IRQ and HPD handling. - Assorted fixes to sii902x, and implementing HDMI audio support. - Enable HDR metadata support on amdgpu. - Assorted fixes to atmel-hlcdc, and add sam9x60 LCD controller support. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6c43ffa9-11ff-5354-d772-c20fd4d1e3d9@linux.intel.com
| * | | drm/amd/display: Only force modesets when toggling HDRNicholas Kazlauskas2019-06-031-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We can issue HDR static metadata as part of stream updates for non-modesets as long as we force a modeset when entering or exiting HDR. This avoids unnecessary blanking for simple metadata updates. [How] When changing scaling and abm for the stream also check if HDR has changed and send the stream update. This will only happen in non-modeset cases. Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528190836.10738-3-nicholas.kazlauskas@amd.com
| * | | drm/amd/display: Expose HDR output metadata for supported connectorsNicholas Kazlauskas2019-06-031-0/+125
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] For userspace to send static HDR metadata to the display we need to attach the property on the connector and send it to DC. [How] The property is attached to HDMI and DP connectors. Since the metadata isn't actually available when creating the connector this isn't a property we can dynamically support based on the extension block being available or not. When the HDR metadata is changed a modeset will be forced for now. We need to switch from 8bpc to 10bpc in most cases anyway, and we want to fully exit HDR mode when userspace gives us a NULL metadata, so this isn't completely unnecessary. The requirement can later be reduced to just entering and exiting HDR or switching max bpc. Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528190836.10738-2-nicholas.kazlauskas@amd.com
* | | Merge branch 'drm-next-5.3' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2019-05-3164-664/+1384
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next New stuff for 5.3: - Add new thermal sensors for vega asics - Various RAS fixes - Add sysfs interface for memory interface utilization - Use HMM rather than mmu notifier for user pages - Expose xgmi topology via kfd - SR-IOV fixes - Fixes for manual driver reload - Add unique identifier for vega asics - Clean up user fence handling with UVD/VCE/VCN blocks - Convert DC to use core bpc attribute rather than a custom one - Add GWS support for KFD - Vega powerplay improvements - Add CRC support for DCE 12 - SR-IOV support for new security policy - Various cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190529220944.14464-1-alexander.deucher@amd.com
| * | drm/amdgpu: fix unload driver failEmily Deng2019-05-281-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | dc_destroy should be called amdgpu_cgs_destroy_device, as it will use cgs context to read or write registers. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: sort probed modes before adding common modesYogesh Mohan Marimuthu2019-05-241-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There are monitors which can have more than one preferred mode set. There are chances in these monitors that if common modes are added in function amdgpu_dm_connector_add_common_modes(), these common modes can be calculated with different preferred mode than the one used in function decide_crtc_timing_for_drm_display_mode(). The preferred mode can be different because after common modes are added, the mode list is sorted and this changes the order of preferred modes in the list. The first mode in the list with preferred flag set is selected as preferred mode. Due to this the preferred mode selected varies. If same preferred mode is not selected in common mode calculation and crtc timing, then during mode set instead of setting preferred timing, common mode timing will be applied which can cause "out of range" message in the monitor with monitor blanking out. [How] Sort the modes before adding common modes. The same sorting function is called during common mode addition and deciding crtc timing. Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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