summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/display/dc
Commit message (Collapse)AuthorAgeFilesLines
...
* | drm/amd/display: add dcn21 core DC changesBhawanpreet Lakha2019-08-294-0/+11
| | | | | | | | | | | | | | | | | | Add missing parameters, to make dcn21 compile without errors Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: call update_bw_bounding_boxBhawanpreet Lakha2019-08-292-0/+10
| | | | | | | | | | | | | | | | call update_bw_bounding_box in DC construct Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Handle Renoir in DCBhawanpreet Lakha2019-08-292-0/+17
| | | | | | | | | | | | | | | | add Renoir DCN version in DC and handle it Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix register namesBhawanpreet Lakha2019-08-291-2/+2
| | | | | | | | | | | | | | | | | | rename VM_CONTEXT0 to MMVM_CONTEXT0 as that is the name defined in the register files Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir DMLBhawanpreet Lakha2019-08-296-0/+8058
| | | | | | | | | | | | | | | | | | DML provides the display configuration validation as provided by the hw teams. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir GPIOBhawanpreet Lakha2019-08-297-0/+687
| | | | | | | | | | | | | | | | Misc display related configuration details. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir resource (v2)Bhawanpreet Lakha2019-08-293-1/+1726
| | | | | | | | | | | | | | | | | | | | Manages the renoir display resources (crtcs, phys, plls, etc.). v2: rebase (Alex) Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir clock managerBhawanpreet Lakha2019-08-297-0/+1013
| | | | | | | | | | | | | | | | | | Controls display clocks and interfaces with powerplay for clock and power requirements. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir Hubbub (v2)Bhawanpreet Lakha2019-08-293-1/+728
| | | | | | | | | | | | | | | | | | | | Controls the display hw's interface to memory. v2: rebase (Alex) Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir hubbub registers listBhawanpreet Lakha2019-08-293-0/+118
| | | | | | | | | | | | | | | | These are the registers used to program the hubbub hw. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add hubp block for Renoir (v2)Bhawanpreet Lakha2019-08-293-0/+387
| | | | | | | | | | | | | | | | | | | | This provides the interface to memory for the display hw. v2: minor cleanup (Alex) Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir irq_services (v2)Bhawanpreet Lakha2019-08-293-0/+418
| | | | | | | | | | | | | | | | | | | | Provides the interface to configure display interrrupts on renoir. v2: rebase fix (Alex) Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add pp_smu functions for RenoirBhawanpreet Lakha2019-08-291-0/+47
| | | | | | | | | | | | | | | | | | This defines the interface for communicating requirements between DC and powerplay. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir hw_seq register listBhawanpreet Lakha2019-08-291-0/+97
| | | | | | | | | | | | | | | | | | These are the registers used to for the hw sequences for modesetting. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Renoir clock registers listBhawanpreet Lakha2019-08-291-0/+17
| | | | | | | | | | | | | | | | These are the registers used to program the clock hw. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORTYueHaibing2019-08-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28: error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control? dc->hwss.dsc_pg_control = dcn20_dsc_pg_control; ^~~~~~~~~~~~~~~~~~~~ dcn20_dpp_pg_control Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this. Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: 3.2.48Anthony Koo2019-08-231-1/+1
| | | | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: flicking observed while installing driver on Navi10 CFhersen wu2019-08-232-27/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] value of dchub_ref_clock is decided by dchubbub global timer settings which is programmed by vbios command table disp_init. for multi-GPU case, vbios is posted only for primary GPU. without vbios posted for the secondary GPU, value of dchub_ref_clock is not set properly. this value will affect dcn bandwidth calcuation and cause underflow. user will see screen flicking during driver installation for dual GPU case. [HOW] dc init_hw always call vbios command table disp_init to make sure dchubbub global timer is configured and enable. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Properly read LVTMA_PWRSEQ_CNTLJoshua Aberback2019-08-231-26/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the embedded display. Currently we do not actually read this register's values, so during power down we think that this display is already off, so we skip calling into VBIOS to actually turn it off. [How] - add relevant fields to shift / mask initialization Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: revert wait in pipelockJun Lei2019-08-231-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Previous workaround to prevent a vsync flip to be converted to immediate flip is no longer needed, and is risky because there are cases where it can result in infinite loop. [how] Remove wait loop (which is potentially infinite) before locking pipe Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Use res_cap to acquire i2c instead of pipe countDerek Lai2019-08-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We should be using the ddc_num from res_caps. As the pipe count != number of i2c resources. [How] Use ddc_num from res_cap instead of pipe count. Signed-off-by: Derek Lai <Derek.Lai@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Expose OTG_V_TOTAL_MID for HW DiagsBayan Zabihiyan2019-08-239-4/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Existing HW Features, HW Diags test requested that the registers be exposed. [How] Add V_TOTAL_MID to existing DC structures. Make sure values are passed down throughout DC Add Register definition. Program the additional registers Add additional Logic for V_TOTAL_CONTROL. Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix DML not calculating delivery timeJun Lei2019-08-231-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Calculating DCFCLK DS time requires calculating delivery time for luma/chroma, but this value is not calculated in DMLv2, it was inadvertently removed when porting DMLv2 [how] Add the calculation back Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: set av_mute in hw_init for HDMICharlene Liu2019-08-234-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | [Description] OS will reserve HW state in UEFI mode. Driver init_hw reset to RGB which caused HDMI green in YCbCr mode. read HW blank_color based on acc_mode. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add Logging for Gamma Related informationWyatt Wood2019-08-231-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] A recent bug showed that logging would be useful in debugging various gamma issues. [How] Add logging in dc. Fix formatting for easier graphing. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Enable HW rotationJaehyun Chung2019-08-233-5/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] HW rotation is not enabled. Calculations for cursor rotation are wrong for the values passed to set_cursor_position. [How] Swap Src rect and height and vertically mirror surface for the correct surface rotation direction. Cursor position is rotated according to angle. Offset calculations are tweaked for non-rotated cursor hotspot and width/height. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: add Cursor Degamma logic for DCN2Bayan Zabihiyan2019-08-237-9/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We need to have the ability to to tell us set degamma on the cursor. [How] Pass a flag down to register programming that tells us if the current surface format needs cursor degamma. Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix odm validationDmytro Laktyushkin2019-08-231-21/+19
| | | | | | | | | | | | | | | | | | | | Update bw validation to use prev and next odm pipe pointers for populating dml inputs. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix odm stream releaseDmytro Laktyushkin2019-08-231-33/+32
| | | | | | | | | | | | | | | | | | Need to memset all odm pipes when calling dc_remove_stream_from_ctx Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix dcn20 odm dpp programmingDmytro Laktyushkin2019-08-232-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | dcn20 requires special casing for odm. This change treats odm as alternative to mpc tree on dcn20. This is planned to be fixed in a future refactor Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix number of slices not being checked for dscNikola Cornij2019-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | [why] num_slices_h was not being checked [How] Fix the typo and check num_slices_h Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix odm pipe copyDmytro Laktyushkin2019-08-232-1/+7
| | | | | | | | | | | | | | | | | | ODM next and prev pipe were missing from dc_copy_state Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix trigger not generated for freesyncYogesh Mohan Marimuthu2019-08-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] In newer hardware MANUAL_FLOW_CONTROL is not a trigger bit. Due to this front porch is fixed and in these hardware freesync does not work. [How] Change the programming to generate a pulse so that the event will be triggered, front porch will be cut short and freesync will work. Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix stuck test pattern on right half of displayZi Yu Liao2019-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] With visual confirm enabled, displays where ODM combine is enabled has a test pattern stuck on the right half of the display even though the display is unblanked. [how] Add a condition to not show the colour ramp test pattern when the display is unblanked. Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: support spdifCharlene Liu2019-08-232-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | [Description] port spdif fix to staging: spdif hardwired to afmt inst 1. spdif func pointer spdif resource allocation (reserve last audio endpoint for spdif only) Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: 3.2.47Anthony Koo2019-08-231-1/+1
| | | | | | | | | | | | | | Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: remove unused functionQingqing Zhuo2019-08-232-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] This function is not being used, it was left in when introducing DCN2 [How] Remove the function Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: cleaned up coding error in init_hwMartin Leung2019-08-231-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] during a refactor a redundant code that has unknown behaviour was added. [how] removed old bad code Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add VM page fault handle implementationJaehyun Chung2019-08-236-3/+21
| | | | | | | | | | | | | | | | | | | | [How] Allocate memory for default page and program memory block addr into default page addr register. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: refactor Device ID for external chipsQingqing Zhuo2019-08-232-6/+17
| | | | | | | | | | | | | | | | | | | | IEEE OUI will now be used while referring to certain vendors. instead of normal index Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Zero-out dsc init regsNikola Cornij2019-08-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Before a statically allocated PPS data structure, that did get zeroed-out at startup, had been re-used for making packed PPS SDP. With S3 fix, using a non-initialized PPS data structure was introduced, while wrongly assuming it'd get initialized before it's populated. As a consequence 'vbr_enable' and perhaps some other fields are left uninitialized when making packed PPS SDP. This can affect 'simple_422' as well because of the way PPS SDP packing is done (the fields are not masked first, only shifted). The behavior will be different, depending on the content of uninitialized data. [how] Zero-out PPS data structure at initialization time before it's populated Fixes: 1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end") Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Implement voltage limitation stubJoseph Gravenor2019-08-231-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | add new function to get the voltage at the end of dcn_validate_bandwidth, to check against the highest voltage we allow. Created a stub to allow for optimizations Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Sun peng Li <Sunpeng.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: add null checks before loggingWyatt Wood2019-08-231-3/+6
| | | | | | | | | | | | | | | | | | | | | | Adding NULL checks to various parameters in log_tf, to avoid nullptr errors Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Nikola Cornij <Nikola.Cornij@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: set Hratio and VRatio in dmlIlya Bakoulin2019-08-231-0/+4
| | | | | | | | | | | | | | | | | | Set the writeback Hratio and Vratio in dml. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix dp stream enableDmytro Laktyushkin2019-08-232-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | A previous odm change broke stream enable by always setting n_multiply as if odm was on. This fixes the check for odm by making sure opp count is >1 rather than not 0. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix MPO HUBP underflow with Scatter GatherZi Yu Liao2019-08-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] With Scatter Gather enabled, HUBP underflows during MPO enabled video playback. hubp_init has a register write that fixes this problem, but the register is cleared when HUBP gets power gated. [how] Make a call to hubp_init during enable_plane, so that the fix can be applied after HUBP powers back on again. Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix audio endpoint not getting disabled issueSu Sung Chung2019-08-2310-42/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Disable_audio_stream gets enum option as a paramenter which will decide if we free acquired resources or not. However checks for the option is guarded by the other condition which check if audio stream is getting diabled more than once. With both conditions combined, if we attempt to disable audio stream twice in a row, first with keep and second with free as an option, we will never free any resources, which will make system think there is audio endpoint connected even after we plug out the device [How] Get rid of option as parameter to disable_audio_stream and move the part of the code that free acquired resources to outside where to keep or to free resources is actually determined Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Delete dead code in command_table_helperJulian Parkin2019-08-233-96/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] dig_encoder_sel_to_atom will always return zero on any ASIC version past DCE80 since programming of the FE selection is handled by driver, but the translation code was left in the function, making it look like a coding error. [How] Remove code that has no effect, and replace with a comment describing why it returns zero. Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: re structure odm to allow 4 to 1 supportDmytro Laktyushkin2019-08-2312-265/+316
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently odm is handled using top_bottom pipe by special casing the differing opps to differentiate from mpc combine. Since top/bottom pipe list was made to track mpc muxing this creates difficulties in adding a 4 pipe odm case support. Rather than continue using mpc combine list, this change reworks odm to use it's own linked list to keep track of odm combine pipes. This also opens up options for using mpo with odm, if a practical use case is ever found. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/display: add flag for multi-display mclk switchingAlex Deucher2019-08-232-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add a dcfeaturemask flag for mclk switching. Disable by default; enable once the feature has seen more testing. Set amdgpu.dcfeaturemask=2 on the kernel command line in grub to enable this. Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
OpenPOWER on IntegriCloud