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| * drm/amdgpu: fix double gpu_recovery for NV of SRIOVMonk Liu2019-12-181-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | issues: gpu_recover() is re-entered by the mailbox interrupt handler mxgpu_nv.c fix: we need to bypass the gpu_recover() invoke in mailbox interrupt as long as the timeout is not infinite (thus the TDR will be triggered automatically after time out, no need to invoke gpu_recover() through mailbox interrupt. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * amd/amdgpu: add sched array to IPs with multiple run-queuesNirmoy Das2019-12-187-46/+89
| | | | | | | | | | | | | | | | | | | | | | This sched array can be passed on to entity creation routine instead of manually creating such sched array on every context creation. v2: squash in missing break fix Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: replace vm_pte's run-queue list with drm gpu scheds listNirmoy Das2019-12-189-38/+24
| | | | | | | | | | | | | | | | | | | | drm_sched_entity_init() takes drm gpu scheduler list instead of drm_sched_rq list. This makes conversion of drm_sched_rq list to drm gpu scheduler list unnecessary Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/scheduler: rework entity creationNirmoy Das2019-12-185-16/+27
| | | | | | | | | | | | | | | | | | | | | | | | Entity currently keeps a copy of run_queue list and modify it in drm_sched_entity_set_priority(). Entities shouldn't modify run_queue list. Use drm_gpu_scheduler list instead of drm_sched_rq list in drm_sched_entity struct. In this way we can select a runqueue based on entity/ctx's priority for a drm scheduler. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/pm_runtime: update usage count in fence handlingAlex Deucher2019-12-181-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Increment the usage count in emit fence, and decrement in process fence to make sure the GPU is always considered in use while there are fences outstanding. We always wait for the engines to drain in runtime suspend, but in practice that only covers short lived jobs for gfx. This should cover us for longer lived fences. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Remove unneeded semicolon in amdgpu_ras.czhengbin2019-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:318:2-3: Unneeded semicolon Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Remove unneeded semicolon in gfx_v10_0.czhengbin2019-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:1967:2-3: Unneeded semicolon Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Remove unneeded semicolon in amdgpu_pmu.czhengbin2019-12-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:110:3-4: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:133:2-3: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:163:2-3: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:191:2-3: Unneeded semicolon Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/sdma5: make ring tests less chattyAlex Deucher2019-12-181-15/+5
| | | | | | | | | | | | | | We already did this for older generations. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/gfx10: make ring tests less chattyAlex Deucher2019-12-181-29/+10
| | | | | | | | | | | | | | We already did this for older generations. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/vcn: remove JPEG related code from idle handler and begin useLeo Liu2019-12-181-23/+5
| | | | | | | | | | | | | | | | For VCN2.0 and above, VCN has been separated from JPEG Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/vcn1.0: use its own idle handler and begin use funcsLeo Liu2019-12-185-6/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Because VCN1.0 power management and DPG mode are managed together with JPEG1.0 under both HW and FW, so separated them from general VCN code. Also the multiple instances case got removed, since VCN1.0 HW just have a single instance. v2: override work func with vcn1.0's own Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: enable gfxoff for raven1 refreshchangzhu2019-12-181-11/+4
| | | | | | | | | | | | | | | | | | | | | | | | When smu version is larger than 0x41e2b, it will load raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads raven_kicker_rlc.bin. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/sriov: Tonga sriov also need load firmware with smuEmily Deng2019-12-181-1/+2
| | | | | | | | | | | | | | | | Fix Tonga sriov load driver fail issue. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewd-by Yintian Tao <Yintian.tao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: drop useless BACO arg in amdgpu_ras_reset_gpuGuchun Chen2019-12-186-8/+7
| | | | | | | | | | | | | | | | | | | | BACO reset mode strategy is determined by latter func when calling amdgpu_ras_reset_gpu. So not to confuse audience, drop it. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Add CU info print logYong Zhao2019-12-181-0/+6
| | | | | | | | | | | | | | | | | | The log will be useful for easily getting the CU info on various emulation models or ASICs. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdkfd: Use Arcturus specific set_vm_context_page_table_base()Yong Zhao2019-12-183-14/+22
| | | | | | | | | | | | | | | | | | | | Since Arcturus has it own function pointer, we can move Arcturus specific logic to there rather than leaving it entangled with other GFX9 chips. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * Merge tag 'drm-next-5.6-2019-12-11' of ↵Daniel Vetter2019-12-1775-2249/+4253
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~agd5f/linux into drm-next drm-next-5.6-2019-12-11: amdgpu: - Add MST atomic routines - Add support for DMCUB (new helper microengine for displays) - Add OEM i2c support in DC - Use vstartup for vblank events on DCN - Simplify Kconfig for DC - Renoir fixes for DC - Clean up function pointers in DC - Initial support for HDCP 2.x - Misc code cleanups - GFX10 fixes - Rework JPEG engine handling for VCN - Add clock and power gating support for JPEG - BACO support for Arcturus - Cleanup PSP ring handling - Add framework for using BACO with runtime pm to save power - Move core pci state handling out of the driver for pm ops - Allow guest power control in 1 VF case with SR-IOV - SR-IOV fixes - RAS fixes - Support for power metrics on renoir - Golden settings updates for gfx10 - Enable gfxoff on supported navi10 skus - Update MAINTAINERS amdkfd: - Clean up generational gfx code - Fixes for gfx10 - DIQ fixes - Share more code with amdgpu radeon: - PPC DMA fix - Register checker fixes for r1xx/r2xx - Misc cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191211223020.7510-1-alexander.deucher@amd.com
| | * drm/amdgpu: fix license on Kconfig and MakefilesAlex Deucher2019-12-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | amdgpu is MIT licensed. Fixes: ec8f24b7faaf3d ("treewide: Add SPDX license identifier - Makefile/Kconfig") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: log when amdgpu.dc=1 but ASIC is unsupportedSimon Ser2019-12-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes it easier to figure out whether the kernel parameter has been taken into account. Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Harry Wentland <hwentlan@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: fix JPEG instance checking when ctx initLeo Liu2019-12-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use proper structure. Fixes: 0388aee766376ed ("drm/amdgpu: use the JPEG structure for general driver support") Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: fix VCN2.x number of irq typesLeo Liu2019-12-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The JPEG irq type has been moved to its own structure Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/gfx10: update gfx golden settings for navi14Tianci.Yin2019-12-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2 Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/gfx10: update gfx golden settingsTianci.Yin2019-12-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2 Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: enable gfxoff feature for navi10 asicKevin Wang2019-12-111-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | enable gfxoff feature for some navi10 asics Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/gfx10: update gfx golden settings for navi14Tianci.Yin2019-12-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | add registers: mmSPI_CONFIG_CNTL Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/gfx10: update gfx golden settingsTianci.Yin2019-12-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | add registers: mmSPI_CONFIG_CNTL Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/powerplay: enable pp one vf mode for vega10Yintian Tao2019-12-118-224/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally, due to the restriction from PSP and SMU, VF has to send message to hypervisor driver to handle powerplay change which is complicated and redundant. Currently, SMU and PSP can support VF to directly handle powerplay change by itself. Therefore, the old code about the handshake between VF and PF to handle powerplay will be removed and VF will use new the registers below to handshake with SMU. mmMP1_SMN_C2PMSG_101: register to handle SMU message mmMP1_SMN_C2PMSG_102: register to handle SMU parameter mmMP1_SMN_C2PMSG_103: register to handle SMU response v2: remove module parameter pp_one_vf v3: fix the parens v4: forbid vf to change smu feature v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute v6: change skip condition at vega10_copy_table_to_smc Signed-off-by: Yintian Tao <yttao@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Added RAS UMC error query support for ArcturusJohn Clements2019-12-113-16/+74
| | | | | | | | | | | | | | | | | | | | | | | | Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: avoid using invalidate semaphore for picassochangzhu2019-12-111-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It may cause timeout waiting for sem acquire in VM flush when using invalidate semaphore for picasso. So it needs to avoid using invalidate semaphore for piasso. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add condition to enable baco for ras recoveryLe Ma2019-12-111-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to baco reset method for ras recovery if the PMFW supported. If not, keep the original reset method. v2: revise the condition Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: fix resume failures due to psp fw loading sequence change (v3)Hawking Zhang2019-12-091-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this fix the regression caused by asd/ta loading sequence adjustment recently. asd/ta loading was move out from hw_start and should also be applied to psp_resume. otherwise those fw loading will be ignored in resume phase. v2: add the mutex unlock for asd loading failure case v3: merge the error handling to failed tag Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * Revert "drm/amdgpu: enable VCN DPG on Raven and Raven2"Thong Thai2019-12-091-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a4840d91c984f93b2acdcd44441d624bbc1af0d2. Reverting due to power efficiency issues seen on Raven 1 and 2 when DPG mode is enabled. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add VM eviction lock v3Christian König2019-12-092-7/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows to invalidate VM entries without taking the reservation lock. v3: use -EBUSY Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: stop adding VM updates fences to the resv objChristian König2019-12-094-13/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't add the VM update fences to the resv object and remove the handling to stop implicitely syncing to them. Ongoing updates prevent page tables from being evicted and we manually block for all updates to complete before releasing PDs and PTS. This way we can do updates even without the resv obj locked. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: explicitely sync to VM updates v2Christian König2019-12-097-40/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows us to reduce the overhead while syncing to fences a bit. v2: also drop adev parameter from the functions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: move VM eviction decision into amdgpu_vm.cChristian König2019-12-093-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | When a page tables needs to be evicted the VM code should decide if that is possible or not. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: reduce redundant uvd context lost warning messageLe Ma2019-12-051-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the print out of uvd instance loop in amdgpu_uvd_suspend v2: drop unnecessary brackets v3: grab ras_intr state once for multiple times use Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: clear err_event_athub flag after reset exitLe Ma2019-12-052-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise next err_event_athub error cannot call gpu reset. And following resume sequence will not be affected by this flag. v2: create function to clear amdgpu_ras_in_intr for modularity of ras driver Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: support full gpu reset workflow when ras err_event_athub occursLe Ma2019-12-051-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This athub fatal error can be recovered by baco without system-level reboot, so add a mode to use baco for the recovery. Not affect the default psp reset situations for now. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add concurrent baco reset support for XGMILe Ma2019-12-052-12/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently each XGMI node reset wq does not run in parrallel if bound to same cpu. Make change to bound the xgmi_reset_work item to different cpus. XGMI requires all nodes enter into baco within very close proximity before any node exit baco. So schedule the xgmi_reset_work wq twice for enter/exit baco respectively. To use baco for XGMI, PMFW supported for baco on XGMI needs to be involved. The case that PSP reset and baco reset coexist within an XGMI hive never exist and is not in the consideration. v2: define use_baco flag to simplify the code for xgmi baco sequence Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: enable/disable doorbell interrupt in baco entry/exit helperLe Ma2019-12-051-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | This operation is needed when baco entry/exit for ras recovery Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: clear uncorrectable parity error status bitLe Ma2019-12-051-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | This should be cleared during every nbif uncorrectable error cleanup work. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: clear ras controller status registers when interrupt occursLe Ma2019-12-051-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To fix issue that ras controller interrupt cannot be triggered anymore after one time nbif uncorrectable error. And error count is stored in nbif ras object for query. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: export amdgpu_ras_find_obj to use externallyLe Ma2019-12-052-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Change it to external interface. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: remove ras global recovery handling from ras_controller_int handlerLe Ma2019-12-051-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | v2: add notification when ras controller interrupt generates Signed-off-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add cache flush workaround to gfx8 emit_fencePierre-Eric Pelloux-Prayer2019-12-051-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The same workaround is used for gfx7. Both PAL and Mesa use it for gfx8 too, so port this commit to gfx_v8_0_ring_emit_fence_gfx. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/gfx: Improvement on EDC GPR workaroundsJames Zhu2019-12-051-20/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI limits total CS waves in flight per SE to no more than 32 * num_cu and we need to stuff 40 waves on a CU to completely clean the SGPR. This is accomplished in the WR by cleaning the SE in two steps, half of the CU per step. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add check before enabling/disabling broadcast modeGuchun Chen2019-12-051-16/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When security violation from new vbios happens, data fabric is risky to stop working. So prevent the direct access to DF mmFabricConfigAccessControl from the new vbios and onwards. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdkfd: Contain MMHUB number in mmhub_v9_4_setup_vm_pt_regs()Yong Zhao2019-12-034-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the exposed function prototype so that the caller does not need to know the MMHUB number. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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