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path: root/drivers/gpu/drm/amd/amdgpu
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| * | | | drm/amdgpu: reorganize sdma v4 code to support more instancesLe Ma2019-07-182-45/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is needed for Arcturus which has 8 sdma instances. The CG/PG part is not covered for now. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: update vmc interrupt routine to support 3 vmhubsLe Ma2019-07-181-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is one more vmc interrupt and mmhub on Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add VMC1 interrupt client id for ArcturusLe Ma2019-07-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New IH client id for VMC1. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: dynamically initialize IP offset for ArcturusLe Ma2019-07-184-1/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the IP offsets on Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: increase max number of ip base instances to 8Le Ma2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Arcturus, the number of IP base instances is 8. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add SDMA 2~7 ip block typeLe Ma2019-07-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IP block type. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: use new mmhub interfaces for ArcturusLe Ma2019-07-181-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arcturus has two MMHUBs. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add mmhub v9.4.1 block for Arcturus (v2)Le Ma2019-07-183-1/+538
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arcturus as an updated mmhub block. mmhub is the memory controller hub used for sdma and multimedia. v2: squash in AGP BAR programming (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add one more mmhub instance for Arcturus (v2)Le Ma2019-07-182-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: set mmhub num under CHIP_ARCTURUS switch case and add one more mmhub id_mgr Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add new member in amdgpu_device for vmhub counts per asic chipLe Ma2019-07-183-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It aims to replace AMDGPU_MAX_VMHUBS in for loop to initialize registers. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub numberLe Ma2019-07-1816-46/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of GFXHUB/MMHUB may be expanded in later ASICs. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add gmc basic support for ArcturusLe Ma2019-07-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial GMC support for Arcturus Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add Arcturus asic typeLe Ma2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add asic type for Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: consolidate navi14 IP initAlex Deucher2019-07-181-15/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's the same as navi10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: disable concurrent flushes on Navi14Alex Deucher2019-07-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same thing applies to navi14 as navi10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: enable gfxoff code path for navi14Jack Xiao2019-07-182-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on navi10 gfxoff logic, enable the related code path for navi14. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/vcn: enable indirect DPG SRAM mode for navi14Xiaojie Yuan2019-07-182-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable VCN dynamic powergating for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/nv: set vcn pg flag for navi14Xiaojie Yuan2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable VCN power gating by default. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: enable async gfx ring for navi14Xiaojie Yuan2019-07-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: enable clock gatings for navi14Xiaojie Yuan2019-07-181-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set appropriate CG flags for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/athub2: set clock gating for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/mmhub2: set clock gating for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: declare asd firmware for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So the dependency gets properly tracked. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <snow.zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: Enable VCN on navi14James Zhu2019-07-182-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add navi14 vcn firmware, and enable VCN on navi14. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: skip to load ta firmware for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not relevant on navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amd/display: add dm blockBhawanpreet Lakha2019-07-182-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable DC for navi14. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: enable sw smu ip for navi14Xiaojie Yuan2019-07-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/psp: start rlc autoload after psp received rlcg for navi14Xiaojie Yuan2019-07-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: enable psp ip block for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/psp: add psp support for navi14 (v3)Xiaojie Yuan2019-07-182-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as navi10. v2: squash in logic fix (Colin Ian King) v3: squash in logic simplification (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: enable virtual display for navi14Xiaojie Yuan2019-07-182-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virtual display is a sw based kms interface for virtualization and emulation. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add ip blocks for navi14Xiaojie Yuan2019-07-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the initial IP blocks for navi14 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/soc15: add support for navi14Xiaojie Yuan2019-07-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | same as navi10 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: fix programming of SC_HIZ_TILE_FIFO_SIZE fieldJack Xiao2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE field is programmed in units of two entries, but 6 bits is insufficient to hold value 128/2 = 64, so set this field as 0 which is interpreted by the hardware as maximum physical fifo size(128). Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: update gfx golden settings for navi14Tao Zhou2019-07-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated settings from hw team. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: update gfx golden settings for navi14Xiaojie Yuan2019-07-181-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add updated settings from hw team. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx: update gc_v10_1_1 golden settingXiaojie Yuan2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated settings for hw team. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: add gfx v10_1_1 golden settings for navi14Xiaojie Yuan2019-07-181-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add golden settings for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx: add definition of mmCGTT_GS_NGG_CLK_CTRLXiaojie Yuan2019-07-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for clockgating. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: set tcp harvest for navi14Xiaojie Yuan2019-07-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update settings for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: set rlc funcs for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu: add me/mec configurations for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add navi14 to appropriate cases. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: add clockgating support for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: add gfx config for navi14Xiaojie Yuan2019-07-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gfx config details for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: add placeholder for navi14 golden settingsXiaojie Yuan2019-07-181-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To be filled in once available. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/gfx10: add support for navi14 firmwareXiaojie Yuan2019-07-181-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for navi14 CP firmware files. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/sdma5: set clock gating for navi14Xiaojie Yuan2019-07-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/sdma5: update sdma5 golden settings for navi14tiancyin2019-07-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add new registers: mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/sdma5: add sdma5_0 golden settings for navi14Xiaojie Yuan2019-07-181-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add settings for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | drm/amdgpu/sdma5: add placeholder for navi14 golden settingsXiaojie Yuan2019-07-181-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To be filled in once they are available. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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