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* drm/amdgpu: validate user GEM object sizeYu Zhao2019-01-081-0/+8
| | | | | | | | | | | | | | | When creating frame buffer, userspace may request to attach to a previously allocated GEM object that is smaller than what GPU requires. Validation must be done to prevent out-of-bound DMA, otherwise it could be exploited to reveal sensitive data. This fix is not done in a common code path because individual driver might have different requirement. Cc: stable@vger.kernel.org # v4.2+ Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Yu Zhao <yuzhao@google.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: validate user pitch alignmentYu Zhao2019-01-081-0/+10
| | | | | | | | | | | | Userspace may request pitch alignment that is not supported by GPU. Some requests 32, but GPU ignores it and uses default 64 when cpp is 4. If GEM object is allocated based on the smaller alignment, GPU DMA will go out of bound. Cc: stable@vger.kernel.org # v4.2+ Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Yu Zhao <yuzhao@google.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: create pp_od_clk_voltage device file under OD supportEvan Quan2019-01-081-8/+14
| | | | | | | | Since pp_od_clk_voltage device file is for OD related sysfs operations. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: make gfx9 enter into rlc safe mode when set MGCGLikun Gao2019-01-031-0/+4
| | | | | | | | MGCG should RLC enter into safe mode first. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Cleanup 2 compiler warningsKent Russell2019-01-031-2/+0
| | | | | | | | | | | | These 2 variables are unused now, so remove their references. Fixes: e4ae0fc drm/amdgpu: implement gfx8 post_soft_reset Fixes: 5e01c09 drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequence Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequenceTiecheng Zhou2019-01-021-13/+35
| | | | | | | | | | | | The kiq ring and the very first compute ring may fail occasionally if they are tested directly following kiq_kcq_enable. Insert the gfx ring test before kiq ring test to delay the kiq and kcq ring tests will fix the issue. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/sriov:Correct pfvf exchange logicEmily Deng2019-01-022-5/+5
| | | | | | | | | The pfvf exchange need be in exclusive mode. And add pfvf exchange in gpu reset. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-By: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/virtual_dce: No need to pin the cursor boEmily Deng2019-01-021-2/+2
| | | | | | | | For virtual display feature, no need to pin cursor bo. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/virtual_dce: No need to pin the fb's boEmily Deng2019-01-022-22/+15
| | | | | | | | For virtual display, no need to pin the fb's bo. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add new VegaM pci idAlex Deucher2018-12-211-0/+1
| | | | | | | | Add a new pci id. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/amdgpu: add Vega20 PSP ASD firmware loadingEvan Quan2018-12-211-9/+31
| | | | | | | | | | Add PSP ASD firmware loading on Vega20. Not sure why this was missing before. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/amdgpu/uvd:Change uvd ring name conventionJames Zhu2018-12-201-2/+2
| | | | | | | | | Since umr tool can't handle bracket, change uvd ring name convention. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: print process info when job timeoutTrigger Huang2018-12-201-0/+6
| | | | | | | | | When a job is timeout, try to print the related process information for debugging Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/nbio7.4: add hw bug workaround for vega20Alex Deucher2018-12-201-0/+7
| | | | | | | | | Configure PCIE_CI_CNTL to work around a hw bug that affects some multi-GPU compute workloads. Acked-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/nbio6.1: add hw bug workaround for vega10/12Alex Deucher2018-12-201-0/+7
| | | | | | | | | Configure PCIE_CI_CNTL to work around a hw bug that affects some multi-GPU compute workloads. Acked-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: correct the return value for error caseEvan Quan2018-12-183-16/+31
| | | | | | | | | It should not return 0 for error case as '0' is actually a special value for index. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREGJames Zhu2018-12-181-2/+7
| | | | | | | | | If register value is updating, reset timeout counter. It improves robustness of SOC15_WAIT_ON_RREG. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vcn:Remove bit 31 for scratch2 to indicate the WA is activeJames Zhu2018-12-181-2/+2
| | | | | | | | Remove bit 31 for scratch2 to indicate the Hardware bug work around is active. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vcn:Scan enc/jpeg fences to init dpg pause new stateJames Zhu2018-12-181-4/+14
| | | | | | | | | Scan enc/jpeg fences to init dpg pause new state in begin use. It will help set dpg mode to desire state actively. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vcn:Always check all vcn ring status during dpg mode stopJames Zhu2018-12-181-8/+16
| | | | | | | | | Always check all vcn ring status during dpg mode stop, it will help identify which vcn ring may cause the issue. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vcn:Update ring point to JPEG before init JPEG wptrJames Zhu2018-12-181-1/+2
| | | | | | | | It is a bug fix. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vcn:Always gate vcn block during hw finishingJames Zhu2018-12-181-1/+2
| | | | | | | | Under Dynamic Power Gate mode, UVD_STATUS needn't be checked. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vcn: Update vcn.cur_state during suspendJames Zhu2018-12-181-1/+2
| | | | | | | | | Replace vcn_v1_0_stop with vcn_v1_0_set_powergating_state during suspend, to keep adev->vcn.cur_state update. It will fix VCN S3 hung issue. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: WARN once if amdgpu_bo_unpin is called for an unpinned BOMichel Dänzer2018-12-141-1/+1
| | | | | | | | | | It indicates a pin/unpin imbalance bug somewhere. While the bug isn't necessarily in the call chain hitting this, it's at least one part involved. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable Vega20 page queue supportEvan Quan2018-12-141-2/+1
| | | | | | | | | Page queue is supported on Vega20 with SDMA firmware 123 onwards. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: use different irq ring ID for Vega20 page queuesEvan Quan2018-12-141-2/+4
| | | | | | | | | Vega20 uses ring id 1 for page queues EOP irq while previous ASICs take ring id 3. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: update the vm invalidation engine layout V2Evan Quan2018-12-142-22/+41
| | | | | | | | | | | | | We need new invalidation engine layout due to new SDMA page queues added. V2: fix coding style and add correct return value Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: increase the MAX ring numberEvan Quan2018-12-141-1/+1
| | | | | | | | | As two more SDMA page queue rings are added on Vega20. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: fix NULL fence handling in amdgpu_cs_fence_to_handle_ioctlChristian König2018-12-141-0/+3
| | | | | | | | | When the fence is already signaled it is perfectly normal to get a NULL fence here. But since we can't export that we need to use a stub fence. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/psp: Correct and refine the vmr support. (v2)Emily Deng2018-12-143-15/+16
| | | | | | | | | | Currently driver only psp v11 support vmr. v2: squash in unused variable removal (Alex) Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/psp_v3_1: Get psp fw version through reading registerEmily Deng2018-12-141-1/+4
| | | | | | | | | | If PSP FW is running already, driver will not load PSP FW again and skip it. So psp fw version is not correct if reading it from FW binary file, need to get right version from register. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: access register without KIQEmily Deng2018-12-141-9/+9
| | | | | | | | | | There is no need to access register such as mmSMC_IND_INDEX_11 and mmSMC_IND_DATA_11, PCIE_INDEX, PCIE_DATA through KIQ because they are VF-copy. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: kfd_pre_reset outside req_full_gpu cause sriov hangwentalou2018-12-141-4/+6
| | | | | | | | | | XGMI hive put kfd_pre_reset into amdgpu_device_lock_adev, but outside req_full_gpu of sriov. It would make sriov hang during reset. Signed-off-by: Wentao Lou <Wentao.Lou@amd.com> Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'drm-next-4.21' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2018-12-1341-477/+563
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next [airlied: make etnaviv build again] amdgpu: - DC trace support - More DC documentation - XGMI hive reset support - Rework IH interaction with KFD - Misc fixes and cleanups - Powerplay updates for newer polaris variants - Add cursor plane update fast path - Enable gpu reset by default on CI parts - Fix config with KFD/HSA not enabled amdkfd: - Limit vram overcommit - dmabuf support - Support for doorbell BOs ttm: - Support for simultaneous submissions to multiple engines scheduler: - Add helpers for hw with preemption support Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181207233119.16861-1-alexander.deucher@amd.com
| * drm/amdgpu: Enable GPU recovery by default for CIAndrey Grodzovsky2018-12-121-0/+2
| | | | | | | | | | | | | | | | I retested Bonaire (gfx7 dGPU) and it works fine. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Fix stub function nameKuehling, Felix2018-12-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | This function was renamed in a previous commit. Update the stub function name for builds with CONFIG_HSA_AMD disabled. Fixes: 611736d8447c ("drm/amdgpu: Add KFD VRAM limit checking") Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: remove set but not used variable 'grbm_soft_reset'YueHaibing2018-12-101-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function 'gfx_v8_0_pre_soft_reset': drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:4950:27: warning: variable 'srbm_soft_reset' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function 'gfx_v8_0_post_soft_reset': drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:5054:27: warning: variable 'srbm_soft_reset' set but not used [-Wunused-but-set-variable] It never used since introduction in commit d31a501ead7f ("drm/amdgpu: add pre_soft_reset ip func") and e4ae0fc33631 ("drm/amdgpu: implement gfx8 post_soft_reset") Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Limit vm max ctx number to 4096Rex Zhu2018-12-102-1/+2
| | | | | | | | | | | | | | | | | | driver need to reserve resource for each ctx for some hw features. so add this limitation. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: bypass RLC init under sriov for Tonga (v2)Tiecheng Zhou2018-12-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | RLC will go wrong in soft_reset under sriov Workaroound: only need to init RLC csb, and skip RLC stop, reset, start this is because host-driver has already done full initialization on RLC v2: squash in build fix Signed-off-by: Tiecehng Zhou <Tiecheng.Zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: move IV prescreening into the GMC codeChristian König2018-12-079-154/+59
| | | | | | | | | | | | | | | | | | | | The GMC/VM subsystem is causing the faults, so move the handling here as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: remove VM fault_credit handlingChristian König2018-12-077-115/+6
| | | | | | | | | | | | | | | | | | | | printk_ratelimit() is much better suited to limit the number of reported VM faults. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: send IVs to the KFD only after processing them v3Christian König2018-12-071-21/+17
| | | | | | | | | | | | | | | | | | | | | | This allows us to filter out VM faults in the GMC code. v2: don't filter out all faults v3: fix copy&paste typo, send all IV to the KFD, don't change message level Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdkfd: Add support for doorbell BOsFelix Kuehling2018-12-071-5/+54
| | | | | | | | | | | | | | | | | | This allows user mode to map doorbell pages into GPUVM address space. That way GPUs can submit to user mode queues (self-dispatch). Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdkfd: Add DMABuf import functionalityFelix Kuehling2018-12-075-3/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | This is used for interoperability between ROCm compute and graphics APIs. It allows importing graphics driver BOs into the ROCm SVM address space for zero-copy GPU access. The API is split into two steps (query and import) to allow user mode to manage the virtual address space allocation for the imported buffer. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Add KFD VRAM limit checkingFelix Kuehling2018-12-075-54/+75
| | | | | | | | | | | | | | | | | | | | | | | | We don't want KFD processes evicting each other over VRAM usage. Therefore prevent overcommitting VRAM among KFD applications with a per-GPU limit. Also leave enough room for page tables on top of the application memory usage. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Workaround build failure due to trace conflictKuehling, Felix2018-12-074-1/+3
| | | | | | | | | | | | | | | | | | | | | | Avoid including mmu_context.h in amdgpu_amdkfd.h since that may be included in other header files that define traces. This leads to conflicts due to traces defined in other headers included via mmu_context.h. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Skip ring soft recovery when fence was NULLwentalou2018-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | amdgpu_ring_soft_recovery would have Call-Trace, when s_fence->parent was NULL inside amdgpu_job_timedout. Check fence first, as drm_sched_hw_job_reset did. Signed-off-by: Wentao Lou <Wentao.Lou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/psp: Destroy psp ring when doing gpu resetXiangliang Yu2018-12-071-1/+3
| | | | | | | | | | | | | | | | | | | | PSP ring need to be destroy before starting reinit for vf. This patche move it from hypervisor driver into guest. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Frank Min <Frank.Min@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/psp: Add support VMR ring for VFXiangliang Yu2018-12-074-31/+85
| | | | | | | | | | | | | | | | | | | | | | PSP only support VMR ring for SRIOV vf since v45 and all commands will be send to VMR ring for executing. VMR ring use C2PMSG 101 ~ 103 instead of C2PMSG 64 ~ 71. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/psp: Get psp fw version through reading registerXiangliang Yu2018-12-071-1/+3
| | | | | | | | | | | | | | | | | | | | If PSP FW is running already, driver will not load PSP FW again and skip it. So psp fw version is not correct if reading it from FW binary file, need to get right version from register. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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