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| * drm/amdgpu: move PSP init prior to IH in gpu resetEmily Deng2018-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | since we use PSP to program IH regs now Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Fix SDMA hang in prt mode v2Tao Zhou2018-09-101-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix SDMA hang in prt mode, clear XNACK_WATERMARK in reg SDMA0_UTCL1_WATERMK to avoid the issue Affected ASICs: VEGA10 VEGA12 RV1 RV2 v2: add reg clear for SDMA1 Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Tested-by: Yukun Li <yukun1.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: fix amdgpu_mn_unlock() in the CS error pathChristian König2018-09-101-1/+1
| | | | | | | | | | | | | | | | Avoid unlocking a lock we never locked. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2018-09-21104-3662/+5473
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next This is a new pull for drm-next on top of last weeks with the following changes: - Fixed 64 bit divide - Fixed vram type on vega20 - Misc vega20 fixes - Misc DC fixes - Fix GDS/GWS/OA domain handling Previous changes from last week: amdgpu/kfd: - Picasso (new APU) support - Raven2 (new APU) support - Vega20 enablement - ACP powergating improvements - Add ABGR/XBGR display support - VCN JPEG engine support - Initial xGMI support - Use load balancing for engine scheduling - Lots of new documentation - Rework and clean up i2c and aux handling in DC - Add DP YCbCr 4:2:0 support in DC - Add DMCU firmware loading for Raven (used for ABM and PSR) - New debugfs features in DC - LVDS support in DC - Implement wave kill for gfx/compute (light weight reset for shaders) - Use AGP aperture to avoid gart mappings when possible - GPUVM performance improvements - Bulk moves for more efficient GPUVM LRU handling - Merge amdgpu and amdkfd into one module - Enable gfxoff and stutter mode on Raven - Misc cleanups Scheduler: - Load balancing support - Bug fixes ttm: - Bulk move functionality - Bug fixes radeon: - Misc cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180920150438.12693-1-alexander.deucher@amd.com
| * | drm/amdgpu: Exclude MM engines for vega20 virtual deviceFrank Min2018-09-191-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Temporary disable UVD/VCE block if is virtual device Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add vega20 sriov capability detectionFrank Min2018-09-191-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sriov capability detection for vega20, then can check if device is virtual device. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: move reserving GDS/GWS/OA into common codeChristian König2018-09-194-57/+18
| | | | | | | | | | | | | | | | | | | | | | | | We don't need that in the per ASIC code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: initialize GDS/GWS/OA domains even when they are zero sizedChristian König2018-09-191-30/+18
| | | | | | | | | | | | | | | | | | | | | | | | Stops crashing on SI. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix up GDS/GWS/OA shiftingChristian König2018-09-199-71/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | That only worked by pure coincident. Completely remove the shifting and always apply correct PAGE_SHIFT. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix shadow BO restoringChristian König2018-09-193-120/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Don't grab the reservation lock any more and simplify the handling quite a bit. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: always recover VRAM during GPU recoveryChristian König2018-09-191-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | It shouldn't add much overhead and we should make sure that critical VRAM content is always restored. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: shadow BOs don't need any alignmentChristian König2018-09-191-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | They aren't directly used by the hardware. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: always enable shadow BOs v2Christian König2018-09-191-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even when GPU recovery is disabled we could run into a manually triggered recovery. v2: keep accidental removed comments Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: stop pipelining VM PDs/PTs movesChristian König2018-09-192-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | We are going to need this for recoverable page fault handling and it makes shadow handling during GPU reset much more easier. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: remove fence fallbackChristian König2018-09-193-58/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DC doesn't seem to have a fallback path either. So when interrupts doesn't work any more we are pretty much busted no matter what. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/powerplay: update OD to take voltage value instead of offsetEvan Quan2018-09-191-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the latest SMC fw, we are able to get the voltage value for specific frequency point. So, we update the OD relates to take absolute voltage instead of offset. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix unknown vram mem type for vega20Hawking Zhang2018-09-191-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vega20 should use umc_info v3_3 instead of v3_1. There are serveral versions of umc_info for vega series. Compared to various versions of these structures, vram_info strucure is unified for vega series. The patch switch to query mem_type from vram_info structure for all the vega series dGPU. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: update vram_info structure in atomfirmware.hHawking Zhang2018-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | atomfirmware has structure changes in varm_info. Updated it to the latest one. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use processed values for countingA. Wilcox2018-09-192-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adev->gfx.rlc has the values from rlc_hdr already processed by le32_to_cpu. Using the rlc_hdr values on big-endian machines causes a kernel Oops due to writing well outside of the array (0x24000000 instead of 0x24). Signed-off-by: A. Wilcox <AWilcox@Wilcox-Tech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amd/amdgpu: Avoid fault when allocating an empty buffer objectTom St Denis2018-09-191-1/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: drop size checkChristian König2018-09-191-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | We no don't allocate zero sized kernel BOs any longer. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: don't allocate zero sized kernel BOsChristian König2018-09-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Just free the BO if the size should be zero. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: stop crashing on GDS/GWS/OA evictionChristian König2018-09-191-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Simply ignore any copying here. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add GDS, GWS and OA debugfs filesChristian König2018-09-191-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Additional to the existing files for VRAM and GTT. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix parameter documentation for amdgpu_vm_free_ptsChristian König2018-09-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | The function was modified without updating the documentation. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add amdgpu_vm_entries_mask v2Christian König2018-09-191-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can't get the mask for the root directory from the number of entries. So add a new function to avoid that problem. v2: fix typo in mask Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: revert "stop using gart_start as offset for the GTT domain"Christian König2018-09-142-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turned out the commit is incomplete and since we remove using the AGP mapping from the GTT manager it is also not necessary any more. This reverts commit 22d8bfafcc12dfa17b91d2e8ae4e1898e782003a. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix mask in GART location calculationChristian König2018-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to mask the lower bits not the upper one. Fixes: ec210e3226dc0 drm/amdgpu: put GART away from VRAM v2 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: James Zhu <James.Zhu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: simplify Raven, Raven2, and Picasso handlingAlex Deucher2018-09-1412-101/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Treat them all as Raven rather than adding a new picasso asic type. This simplifies a lot of code and also handles the case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu fw handling for picasso. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/soc15: clean up picasso supportAlex Deucher2018-09-141-17/+0
| | | | | | | | | | | | | | | | | | | | | It's the same as raven so remove the duplicate case. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Add DMCU to firmware query interfaceDavid Francis2018-09-141-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | DMCU firmware version can be read using the AMDGPU_INFO ioctl or the amdgpu_firmware_info debugfs entry Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Style fixes to PRIME code documentationVijetha Malkai2018-09-141-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Use consistent capitalization in the description of function arguments * Define and consistently use the BO acronym for buffer objects * Some minor wording improvements Signed-off-by: Vijetha Malkai <vijetha.malkai@amd.com> [ Michel Dänzer: Made commit log more specific ] Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: Initialize fences array entries in amdgpu_sa_bo_next_holeMichel Dänzer2018-09-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The entries were only initialized once in amdgpu_sa_bo_new. If a fence wasn't signalled yet in the first amdgpu_sa_bo_next_hole call, but then got signalled before a later amdgpu_sa_bo_next_hole call, it could destroy the fence but leave its pointer in the array, resulting in use-after-free in amdgpu_sa_bo_new. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: set CG flags for raven2 (v2)Huang Rui2018-09-141-20/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raven2 does not enable all of the CG flags that raven1 does. v2: rebase (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: fix the VM fault while write at the top of the invisible vramHuang Rui2018-09-142-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raven2 has a HW issue that it is unable to use the vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the workaround that increase system aperture high address to get rid of the VM fault and hardware hang. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx9: add raven2 golden settingFeifei Xu2018-09-141-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | Golden register settings from the hw team. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/gfx9: add support for raven2 gfx firmwareFeifei Xu2018-09-141-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | use raven2 gfx firmware. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma4: Add raven2 golden settingFeifei Xu2018-09-141-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | Golden register settings from the hw team. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu/sdma4: specify raven2 firmware.Feifei Xu2018-09-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | use raven2 sdma firmware. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add psp support for raven2Likun Gao2018-09-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Modified for using raven2_asd.bin to replace raven_asd.bin for raven2 Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add raven2 vcn firmware supportFeifei Xu2018-09-141-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | Specify raven2 vcn firmware on amdgpu_vce_sw_init. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add raven2 to gpu_info firmwareFeifei Xu2018-09-141-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add gpu_info firmware for raven2. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: set external rev id for raven2Alex Deucher2018-09-141-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | It's different from raven1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: move get_rev_id at first before load gpu_info firmwareHuang Rui2018-09-141-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rev id is used for identifying Raven2 series of chips. So we would better to initialize it at first. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: use IP presence to free uvd and vce handlesAlex Deucher2018-09-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Rather than checking the asic type, check whether the UVD or VCE IP blocks exist. This way we don't have to update the check with new asics that use VCN. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable gfxoff in non-sriov and stutter mode by defaultKenneth Feng2018-09-142-2/+4
| | | | | | | | | | | | | | | | | | | | | enable gfxoff in non-sriov and stutter mode by default Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add new raven series deviceHuang Rui2018-09-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to add new pci device for raven series. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: add ip blocks for picasso (v2)Huang Rui2018-09-141-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCO IPs. V2: enable VCN as well Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable vcn powergating for PCOKenneth Feng2018-09-141-1/+3
| | | | | | | | | | | | | | | | | | | | | enable vcn pg Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | drm/amdgpu: enable mmhub power gatingKenneth Feng2018-09-144-223/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove some functions due to the design change. All the mmhub power gating sequence is moved to smu fw.Driver sends the message to enable mmhub powergating.We can also skip the fw version check since the old fw version is in a very early stage and we don't use that fw for release. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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