summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu
Commit message (Collapse)AuthorAgeFilesLines
...
* | drm/amdgpu:fix missing programing critical registersMonk Liu2017-03-293-1/+21
| | | | | | | | | | | | | | | | | | those MC_VM registers won't be programed by VBIOS in VF so driver is responsible to programe them. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:fix ring_write_multipleMonk Liu2017-03-291-2/+2
| | | | | | | | | | | | | | | | ring_write_multiple should use buf_mask instead of ptr_mask Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:fix gmc_v9 vm fault process for SRIOVMonk Liu2017-03-291-8/+16
| | | | | | | | | | | | | | | | | | for SRIOV we cannot use access register when in IRQ routine with regular KIQ method Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:no cg for soc15 of SRIOVMonk Liu2017-03-291-0/+3
| | | | | | | | | | | | | | | | no CG for SRIOV on SOC15 Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:two fixings for sdma v4 for SRIOVMonk Liu2017-03-291-0/+6
| | | | | | | | | | | | | | | | | | no hw_fini for SRIOV, otherwise other VF will be affected no CG for SRIOV Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:change sequence of SDMA v4 initMonk Liu2017-03-291-10/+27
| | | | | | | | | | | | | | | | | | | | | | | | must set minor_update.enable before write smaller value to wptr/doorbell, so for sriov we need set that register bit in hw_init period. this could fix the SDMA ring test fail after guest reboot Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:fix ring init sequenceMonk Liu2017-03-292-4/+4
| | | | | | | | | | | | | | | | | | | | ring->buf_mask need be set prior to ring_clear_ring invoke and fix ring_clear_ring as well which should use buf_mask instead of ptr_mask Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:virt_init_setting invoke is missed!Monk Liu2017-03-291-0/+4
| | | | | | | | | | | | | | | | this must be invoked during early init Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:enable MCBP for SR-IOV (v2)Monk Liu2017-03-292-0/+4
| | | | | | | | | | | | | | | | | | | | Apply the new IB during IB emit for SRIOV with MCBP v2: agd: use define instead of magic number Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:enable mcbp for gfx9(v2)Monk Liu2017-03-292-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | set bit 21 of IB.control filed to actually enable MCBP for SRIOV v2: add flag for preemption enable bit for soc15 and use this flag instead of hardcode. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:implement cond_exec for gfx8Monk Liu2017-03-291-0/+30
| | | | | | | | | | | | | | | | | | | | | | when MCBP enabled for gfx8, the cond_exec must also be implemented, otherwise there will be odds to meet cross engine (ce and me) deadlock when world switch happens. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:fix the check in cs_ib_fill for SRIOVMonk Liu2017-03-291-9/+10
| | | | | | | | | | | | | | | | | | 1,the check is only appliable for SRIOV GFX engine. 2,use chunk_ib instead of ib. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Ken Wang <Qingqing.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:protect cs submitMonk Liu2017-03-291-1/+12
| | | | | | | | | | | | | | | | to prevent submit two or more IBs with PREEMPT flags. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu:fix cs_ib_fillMonk Liu2017-03-291-1/+1
| | | | | | | | | | | | | | | | | | should use chunk_ib instead of ib, otherwise the logic is incorrect. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Ken Wang <Qingqing.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: clear freed mappings immediately when BO may be freedNicolai Hähnle2017-03-291-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also, add the fence of the clear operations to the BO to ensure that the underlying memory can only be re-used after all PTEs pointing to it have been cleared. This avoids the following sequence of events that could be triggered by user space: 1. Submit a CS that accesses some BO _without_ adding that BO to the buffer list. 2. Free that BO. 3. Some other task re-uses the memory underlying the BO. 4. The CS is submitted to the hardware and accesses memory that is now already in use by somebody else. By clearing the page tables immediately in step 2, a GPU VM fault will be triggered in step 4 instead of wild memory accesses. v2: use amdgpu_bo_fence directly Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: enable four level VMPT for gmc9Chunming Zhou2017-03-291-1/+1
| | | | | | | | | | | | Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: set page table depth by num_levelChunming Zhou2017-03-292-2/+3
| | | | | | | | | | | | Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: adapt vm size for multi vmptChunming Zhou2017-03-291-0/+6
| | | | | | | | | | | | | | Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: limit block size to one pageChunming Zhou2017-03-291-0/+8
| | | | | | | | | | | | | | Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: abstract block size to one functionChunming Zhou2017-03-291-27/+32
| | | | | | | | | | | | Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add alloc/free for multi level PDs V2Christian König2017-03-291-69/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate and free page directories on demand. V2: a. clear entries allocation b. fix entries index calculation c. need alloc sub level even parent bo was allocated Signed-off-by: Christian König <christian.koenig@amd.com> (v1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (v2) Acked-by: Alex Deucher <alexander.deucher@amd.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: handle multi level PD during PT updatesChristian König2017-03-291-5/+34
| | | | | | | | | | | | | | | | Not the best solution, but good enough for now. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: handle multi level PD updates V2Christian König2017-03-294-37/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all levels of the page directory. V2: a. sub level pdes always are written to incorrect place. b. sub levels need to update regardless of parent updates. Signed-off-by: Christian König <christian.koenig@amd.com> (V1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (V1) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (V2) Acked-by: Alex Deucher <alexander.deucher@amd.com> (V2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: handle multi level PD in the LRUChristian König2017-03-291-9/+27
| | | | | | | | | | | | | | | | Move all levels to the end after command submission. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: handle multi level PD during validationChristian König2017-03-291-15/+42
| | | | | | | | | | | | | | | | All page directory levels should be in place after this. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: handle multi level PD size calculation (v2)Christian König2017-03-291-12/+22
| | | | | | | | | | | | | | | | | | | | | | Allows us to get the size for all levels as well. v2: agd: fix warning Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: generalize page table levelChristian König2017-03-293-50/+50
| | | | | | | | | | | | | | | | No functional change, but the base for multi level page tables. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add num_level to the VM managerChristian König2017-03-295-0/+5
| | | | | | | | | | | | | | | | Needs to be filled with handling. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as wellChristian König2017-03-291-10/+11
| | | | | | | | | | | | | | | | This way we save passing it through the different functions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: rename page_directory_fence to last_dir_updateChristian König2017-03-293-6/+6
| | | | | | | | | | | | | | | | Decribes better what this is used for. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add get_clockgating callback for mmhub v1Huang Rui2017-03-291-0/+20
| | | | | | | | | | | | | | Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add get_clockgating for sdma v4Huang Rui2017-03-291-0/+20
| | | | | | | | | | | | | | Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add get_clockgating callback for soc15 (v3)Huang Rui2017-03-292-0/+40
| | | | | | | | | | | | | | | | | | | | v2: squash register typo fix from Ray v3: fix spelling Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add get_clockgating callback for nbio v6.1Huang Rui2017-03-293-0/+17
| | | | | | | | | | | | | | Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add get_clockgating callback for gfx v9Huang Rui2017-03-292-0/+45
| | | | | | | | | | | | | | Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/gfx9: further KIQ parameter cleanupAlex Deucher2017-03-291-11/+11
| | | | | | | | | | | | | | The ring structure already has what we need. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/gfx9: store the eop gpu addr in the ring structureAlex Deucher2017-03-291-8/+6
| | | | | | | | | | | | | | Avoids passing around additional parameters during setup. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/gfx9: reduce the functon params for mpq setupAlex Deucher2017-03-291-16/+14
| | | | | | | | | | | | | | | | Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/gfx9: reserve kiq eop object before unmapping itAlex Deucher2017-03-291-0/+4
| | | | | | | | | | | | | | It's required. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/gfx9: reserve mqd objects before mapping themAlex Deucher2017-03-291-11/+21
| | | | | | | | | | | | | | It's required. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/gfx9: rename some functionsAlex Deucher2017-03-291-4/+4
| | | | | | | | | | | | | | | | To better match where they are used. Called from sw_init and sw_fini. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/gfx9: whitespace cleanupAlex Deucher2017-03-291-6/+5
| | | | | | | | | | Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/amdgpu: Fix some warnings in vce4Harry Wentland2017-03-291-4/+4
| | | | | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/vce4: impl vce & mmsch sriov startXiangliang Yu2017-03-291-1/+204
| | | | | | | | | | | | | | | | | | | | | | For MM sriov, need use MMSCH to init engine and the init procedures are all saved in mm table. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: add mmsch structuresXiangliang Yu2017-03-291-0/+87
| | | | | | | | | | | | | | | | | | | | | | For MM SRIOV, need to prepare MM table send send it to MMSCH to initial UVD & VCE engine. Create new header file for the structures. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/vce4: Ignore vce ring/ib test temporarilyXiangliang Yu2017-03-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | In order to not break SRIOV gfx development, will revert this patch after vce proved working. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/vce4: alloc mm table for MM sriovXiangliang Yu2017-03-291-0/+21
| | | | | | | | | | | | | | | | | | | | | | Allocate MM table for sriov device. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/virt: add structure for MM tableXiangliang Yu2017-03-291-0/+7
| | | | | | | | | | | | | | | | | | | | Add new structure for MM table for multi media scheduler of sriov. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: disable uvd for sriovXiangliang Yu2017-03-291-1/+2
| | | | | | | | | | | | | | | | | | | | disable uvd for sriov temporarily. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu/vce4: enable doorbell for SRIOVXiangliang Yu2017-03-291-1/+24
| | | | | | | | | | | | | | | | | | | | VCE SRIOV need use doorbell and only works on VCN0 ring now Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
OpenPOWER on IntegriCloud