summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
...
| | | | * | | clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driverJeffrey Hugo2019-11-073-0/+348
| | | | * | | clk: qcom: Allow constant ratio freq tables for rcgJeffrey Hugo2019-11-072-0/+5
| | | | * | | clk: qcom: smd: Add missing pnoc clockJeffrey Hugo2019-11-071-0/+3
| | | | * | | clk: qcom: Enumerate clocks and reset needed to boot the 8998 modemJeffrey Hugo2019-11-071-0/+72
| | | | * | | clk: qcom: clk-rpmh: Add support for RPMHCC for SC7180Taniya Das2019-11-071-0/+19
| | | | * | | clk: qcom: Add Global Clock controller (GCC) driver for SC7180Taniya Das2019-11-073-0/+2460
| | | | * | | clk: qcom: common: Return NULL from clk_hw OF providerTaniya Das2019-11-071-1/+1
| | | | * | | clk: qcom: rcg: update the DFS macro for RCGTaniya Das2019-11-072-49/+49
| | | | * | | clk: qcom: remove unneeded semicolonYueHaibing2019-11-071-2/+2
| | | | * | | clk: qcom: Add Q6SSTOP clock controller for QCS404Govind Singh2019-11-073-0/+232
| | | | |/ /
| | | * | | clk: sunxi-ng: h3: Export MBUS clockJernej Skrabec2019-11-051-4/+0
| | | * | | clk: sunxi-ng: h6: Allow GPU to change parent rateJernej Skrabec2019-10-021-1/+1
| | | * | | clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLLJernej Skrabec2019-09-301-6/+15
| | | |/ /
| | * | | clk/ti/adpll: allocate room for terminating nullStephen Kitt2019-11-081-9/+2
| | * | | clk: ti: divider: convert to use min,max,mask instead of widthTero Kristo2019-10-312-91/+74
| | * | | clk: ti: divider: cleanup ti_clk_parse_divider_data APITero Kristo2019-10-313-14/+9
| | * | | clk: ti: divider: cleanup _register_divider and ti_clk_get_div_tableTero Kristo2019-10-311-72/+41
| | * | | clk: ti: am43xx: drop idlest polling from gfx clockTero Kristo2019-10-311-1/+1
| | * | | clk: ti: am33xx: drop idlest polling from gfx clockTero Kristo2019-10-311-1/+1
| | * | | clk: ti: am33xx: drop idlest polling from pruss clkctrl clockTero Kristo2019-10-311-1/+1
| | * | | clk: ti: am43xx: drop idlest polling from pruss clkctrl clockTero Kristo2019-10-311-1/+1
| | * | | clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocksSuman Anna2019-10-311-2/+2
| | * | | clk: ti: omap4: Drop idlest polling from IPU & DSP clkctrl clocksSuman Anna2019-10-311-2/+2
| | * | | clk: ti: dra7xx: Drop idlest polling from IPU & DSP clkctrl clocksTero Kristo2019-10-311-4/+4
| | * | | clk: ti: omap5: add IVA subsystem clkctrl dataTero Kristo2019-10-311-0/+7
| | * | | clk: ti: clkctrl: add new exported API for checking standby infoTero Kristo2019-10-311-0/+33
| | * | | clk: ti: clkctrl: convert to use bit helper macros instead of bitopsTero Kristo2019-10-311-4/+4
| | * | | clk: ti: clkctrl: fix setting up clkctrl clocksTero Kristo2019-10-311-1/+1
| | |/ /
| | | |
| | \ \
| | \ \
| | \ \
| | \ \
| | \ \
| | \ \
| | \ \
| *-------. \ \ Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and 'c...Stephen Boyd2019-11-2728-1530/+2058
| |\ \ \ \ \ \ \
| | | | | | * | | clk: imx: imx8mq: fix sys3_pll_out_selsPeng Fan2019-11-041-2/+2
| | | | | | * | | clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clockFancy Fang2019-10-281-2/+1
| | | | | | * | | clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify codePeng Fan2019-10-281-4/+4
| | | | | | * | | clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify codePeng Fan2019-10-281-6/+6
| | | | | | * | | clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify codePeng Fan2019-10-281-4/+4
| | | | | | * | | clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify codePeng Fan2019-10-281-2/+2
| | | | | | * | | clk: imx7ulp: Correct DDR clock mux optionsAnson Huang2019-10-261-2/+2
| | | | | | * | | clk: imx7ulp: Correct system clock source option #7Anson Huang2019-10-261-1/+1
| | | | | | * | | clk: imx: imx8mq: mark sys1/2_pll as fixed clockPeng Fan2019-10-251-6/+2
| | | | | | * | | clk: imx: imx8mn: mark sys_pll1/2 as fixed clockPeng Fan2019-10-251-26/+20
| | | | | | * | | clk: imx: imx8mm: mark sys_pll1/2 as fixed clockPeng Fan2019-10-251-26/+20
| | | | | | * | | clk: imx8mn: Define gates for pll1/2 fixed dividersLeonard Crestez2019-10-251-19/+38
| | | | | | * | | clk: imx8mm: Define gates for pll1/2 fixed dividersLeonard Crestez2019-10-251-19/+38
| | | | | | * | | clk: imx8mq: Define gates for pll1/2 fixed dividersLeonard Crestez2019-10-251-20/+41
| | | | | | * | | clk: imx: clk-pll14xx: Make two variables staticYueHaibing2019-10-141-2/+2
| | | | | | * | | clk: imx8mq: Add VIDEO2_PLL clockLaurentiu Palcu2019-10-141-0/+4
| | | | | | * | | clk: imx8mn: Use common 1443X/1416X PLL clock structureAnson Huang2019-10-062-79/+12
| | | | | | * | | clk: imx8mm: Move 1443X/1416X PLL clock structure to common placeAnson Huang2019-10-063-77/+43
| | | | | | * | | clk: imx: pll14xx: Fix quick switch of S/K parameterLeonard Crestez2019-10-061-32/+8
| | | | | | |/ /
| | | | | * | | clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportGeert Uytterhoeven2019-11-014-4/+32
| | | | | * | | clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960Geert Uytterhoeven2019-11-013-4/+4
OpenPOWER on IntegriCloud