summaryrefslogtreecommitdiffstats
path: root/drivers/clk/zynq/pll.c
Commit message (Collapse)AuthorAgeFilesLines
* clk/zynq/pll: Use #defines for fbdiv min/max valuesSoren Brinkmann2013-08-201-4/+7
| | | | | | | | Use more descriptive #defines for the minimum and maximum PLL feedback divider. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* clk/zynq/pll: Fix documentation for PLL register functionSoren Brinkmann2013-08-201-1/+7
| | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* clk: zynq: Factor out PLL driverSoren Brinkmann2013-05-211-0/+235
Refactor the PLL driver so it works with the clock controller driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org>
OpenPOWER on IntegriCloud