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path: root/drivers/clk/tegra
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* clk: tegra: Do not print errors for clk_round_rate()Thierry Reding2013-11-281-6/+3
* clk: tegra: Initialize DSI low-power clocksThierry Reding2013-11-261-0/+2
* clk: tegra: add FUSE clock deviceAlexandre Courbot2013-11-264-1/+4
* clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding2013-11-261-1/+3
* clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding2013-11-261-0/+1
* clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen2013-11-261-0/+2
* clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo2013-11-261-0/+27
* clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo2013-11-261-0/+26
* clk: tegra124: Add support for Tegra124 clocksPeter De Schrijver2013-11-262-0/+1371
* clk: tegra124: Add new peripheral clocksPeter De Schrijver2013-11-261-0/+69
* clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver2013-11-261-0/+22
* clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver2013-11-263-3/+22
* clk: tegra: add locking to periph clksPeter De Schrijver2013-11-262-19/+24
* clk: tegra: Add periph regs bank XPeter De Schrijver2013-11-261-0/+10
* clk: tegra: Add support for PLLSSPeter De Schrijver2013-11-262-2/+126
* clk: tegra: move tegra20 to common infraPeter De Schrijver2013-11-261-402/+255
* clk: tegra: move tegra30 to common infraPeter De Schrijver2013-11-261-895/+403
* clk: tegra: introduce common gen4 super clockPeter De Schrijver2013-11-264-74/+155
* clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver2013-11-265-74/+253
* clk: tegra: move periph clocks to common filePeter De Schrijver2013-11-266-581/+627
* clk: tegra: move audio clk to common filePeter De Schrijver2013-11-264-208/+402
* clk: tegra: add clkdev registration infraPeter De Schrijver2013-11-263-159/+179
* clk: tegra: add common infra for DT clocksPeter De Schrijver2013-11-262-0/+16
* clk: tegra: add header for common tegra clock IDsPeter De Schrijver2013-11-261-0/+213
* clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver2013-11-265-177/+175
* clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver2013-11-262-4/+7
* clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver2013-11-262-93/+111
* clk: tegra: Add TEGRA_PERIPH_NO_DIV flagPeter De Schrijver2013-11-262-3/+9
* clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver2013-11-266-108/+85
* clk: tegra: simplify periph clock dataPeter De Schrijver2013-11-267-584/+464
* clk: tegra: Fix clock rate computationThierry Reding2013-11-261-0/+2
* clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3dThierry Reding2013-11-261-4/+4
* clk: tegra: PLLE spread spectrum controlPeter De Schrijver2013-11-261-1/+29
* clk: tegra: Set the clk parent of host1x to pll_pAndrew Chew2013-11-261-0/+1
* clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver2013-11-262-33/+39
* clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2Mark Zhang2013-11-251-0/+3
* clk: tegra: Fix vde/2d/3d clock src offsetMark Zhang2013-11-251-10/+3
* clk: tegra: Correct sbc mux width & parentMark Zhang2013-11-251-6/+6
* clk: tegra: replace enum tegra114_clk by binding headerPeter De Schrijver2013-11-251-233/+198
* Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-09-093-29/+54
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| * clk: tegra30: Don't wait for PLL_U lock bitTuomas Tynkkynen2013-08-281-1/+1
| * clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-193-25/+50
| * clk: tegra30: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
| * clk: tegra20: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
| * clk: tegra114: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
* | clk: tegra114: add LP1 suspend/resume supportJoseph Lo2013-08-121-0/+12
* | clk: tegra: add suspend/resume function for tegra_cpu_car_opsJoseph Lo2013-07-191-0/+26
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* Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-07-036-181/+472
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| * clk: tegra: T114: add DFLL DVCO reset controlPaul Walmsley2013-06-182-0/+39
| * clk: tegra: T114: add DFLL source clocksPaul Walmsley2013-06-181-0/+11
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