summaryrefslogtreecommitdiffstats
path: root/drivers/clk/meson/clk-pll.c
Commit message (Collapse)AuthorAgeFilesLines
* clk: meson: fractional pll supportMichael Turquette2016-06-221-2/+30
| | | | | | | | | Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add in a couple of new bitfields for further dividing the clock rate to achieve rates with fractional hertz. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: meson8b: clean up pll clocksMichael Turquette2016-06-221-61/+11
| | | | | | | | | Remove the pll registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: meson: Add support for Meson clock controllerCarlo Caione2015-06-051-0/+227
This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
OpenPOWER on IntegriCloud