| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | x86, mce, cmci: define MSR names and fields for new CMCI registers | Andi Kleen | 2009-02-24 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | Impact: New register definitions only CMCI means support for raising an interrupt on a corrected machine check event instead of having to poll for it. It's a new feature in Intel Nehalem CPUs available on some machine check banks. For details see the IA32 SDM Vol3a 14.5 Define the registers for it as a preparation for further patches. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> | ||||
| * | x86: Fix ASM_X86__ header guards | H. Peter Anvin | 2008-10-22 | 1 | -3/+3 |
| | | | | | | | | | | Change header guards named "ASM_X86__*" to "_ASM_X86_*" since: a. the double underscore is ugly and pointless. b. no leading underscore violates namespace constraints. Signed-off-by: H. Peter Anvin <hpa@zytor.com> | ||||
| * | x86, um: ... and asm-x86 move | Al Viro | 2008-10-22 | 1 | -0/+417 |
| Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: H. Peter Anvin <hpa@zytor.com> | |||||
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index : talos-op-linux | |
| Talos™ II Linux sources for OpenPOWER | Raptor Computing Systems |
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