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* powerpc: Create disable_kernel_{fp,altivec,vsx,spe}()Anton Blanchard2015-12-011-0/+2
| | | | | | | | | | | | | The enable_kernel_*() functions leave the relevant MSR bits enabled until we exit the kernel sometime later. Create disable versions that wrap the kernel use of FP, Altivec VSX or SPE. While we don't want to disable it normally for performance reasons (MSR writes are slow), it will be used for a debug boot option that does this and catches bad uses in other areas of the kernel. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc: Remove double braces in alignment code.Anton Blanchard2014-11-101-1/+1
| | | | | | | Looks like I introduced this when adding LE support. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* KVM: PPC: BOOK3S: Remove open coded make_dsisr in alignment handlerAneesh Kumar K.V2014-05-301-33/+1
| | | | | | | | | Use make_dsisr instead of open coding it. This also have the added benefit of handling alignment interrupt on additional instructions. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* powerpc: Add lq/stq emulationAnton Blanchard2014-04-091-8/+44
| | | | | | | | Recent CPUs support quad word load and store instructions. Add support to the alignment handler for them. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Enable Little Endian Alignment Handler for Float Pair InstructionsTom Musta2013-10-301-6/+0
| | | | | | | | | This patch enables alignment handling for the load/store floating point pair instructions (lfdp, lfdpx, stfdp, stfdpx). The handler routine is properly coded and only needs to be enabled. Signed-off-by: Tom Musta <tmusta@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Fix Handler of Unaligned Load/Store StringsTom Musta2013-10-301-5/+16
| | | | | | | | | | | | | | The alignment handler is incorrect for unaligned string instructions in little endian mode. These instructions access data as arrays of bytes and thus are endian neutral. However, the routine also handles the load/store multiple instructions, which are NOT endian neutral. This patch toggles the byte swapping flag for the string instructions in little endian builds. This effectively disables the byte swapping logic. Signed-off-by: Tom Musta <tmusta@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Merge branch 'for-kvm' into nextBenjamin Herrenschmidt2013-10-111-4/+4
|\ | | | | | | | | | | | | | | | | Topic branch for commits that the KVM tree might want to pull in separately. Hand merged a few files due to conflicts with the LE stuff Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc: Put FP/VSX and VR state into structuresPaul Mackerras2013-10-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This creates new 'thread_fp_state' and 'thread_vr_state' structures to store FP/VSX state (including FPSCR) and Altivec/VSX state (including VSCR), and uses them in the thread_struct. In the thread_fp_state, the FPRs and VSRs are represented as u64 rather than double, since we rarely perform floating-point computations on the values, and this will enable the structures to be used in KVM code as well. Similarly FPSCR is now a u64 rather than a structure of two 32-bit values. This takes the offsets out of the macros such as SAVE_32FPRS, REST_32FPRS, etc. This enables the same macros to be used for normal and transactional state, enabling us to delete the transactional versions of the macros. This also removes the unused do_load_up_fpu and do_load_up_altivec, which were in fact buggy since they didn't create large enough stack frames to account for the fact that load_up_fpu and load_up_altivec are not designed to be called from C and assume that their caller's stack frame is an interrupt frame. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Handle VSX alignment faults in little endian modeAnton Blanchard2013-10-111-8/+33
| | | | | | | | | | | | | | | | | | Things are complicated by the fact that VSX elements are big endian ordered even in little endian mode. 8 byte loads and stores also write to the top 8 bytes of the register. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Add little endian support to alignment handlerAnton Blanchard2013-10-111-30/+63
| | | | | | | | | | | | | | | | Handle most unaligned load and store faults in little endian mode. Strings, multiples and VSX are not supported. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Alignment handler shouldn't access VSX registers with TS_FPRAnton Blanchard2013-10-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The TS_FPR macro selects the FPR component of a VSX register (the high doubleword). emulate_vsx is using this macro to get the address of the associated VSX register. This happens to work on big endian, but fails on little endian. Replace it with an explicit array access. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Remove hard coded FP offsets in alignment handlerAnton Blanchard2013-10-111-2/+2
| | | | | | | | | | | | | | | | | | The alignment handler assumes big endian ordering when selecting the low word of a 64bit floating point value. Use the existing union which works in both little and big endian. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | powerpc: Remove open coded byte swap macro in alignment handlerAnton Blanchard2013-10-111-24/+12
|/ | | | | | | Use swab64/32/16 instead of open coding it. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Never handle VSX alignment exceptions from kernelAnton Blanchard2013-08-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The VSX alignment handler needs to write out the existing VSX state to memory before operating on it (flush_vsx_to_thread()). If we take a VSX alignment exception in the kernel bad things will happen. It looks like we could write the kernel state out to the user process, or we could handle the kernel exception using data from the user process (depending if MSR_VSX is set or not). Worse still, if the code to read or write the VSX state causes an alignment exception, we will recurse forever. I ended up with hundreds of megabytes of kernel stack to look through as a result. Floating point and SPE code have similar issues but already include a user check. Add the same check to emulate_vsx(). With this patch any unaligned VSX loads and stores in the kernel will show up as a clear oops rather than silent corruption of kernel or userspace VSX state, or worse, corruption of a potentially unlimited amount of kernel memory. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Handle unaligned ldbrx/stdbrxAnton Blanchard2013-08-141-0/+10
| | | | | | | | | | | | | | | | | | | | | Normally when we haven't implemented an alignment handler for a load or store instruction the process will be terminated. The alignment handler uses the DSISR (or a pseudo one) to locate the right handler. Unfortunately ldbrx and stdbrx overlap lfs and stfs so we incorrectly think ldbrx is an lfs and stdbrx is an stfs. This bug is particularly nasty - instead of terminating the process we apply an incorrect fixup and continue on. With more and more overlapping instructions we should stop creating a pseudo DSISR and index using the instruction directly, but for now add a special case to catch ldbrx/stdbrx. Signed-off-by: Anton Blanchard <anton@samba.org> Cc: <stable@vger.kernel.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Disintegrate asm/system.h for PowerPCDavid Howells2012-03-281-1/+1
| | | | | | | | Disintegrate asm/system.h for PowerPC. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> cc: linuxppc-dev@lists.ozlabs.org
* powerpc: Remove fpscr use from [kvm_]cvt_{fd,df}Andreas Schwab2010-09-021-2/+2
| | | | | | | | Neither lfs nor stfs touch the fpscr, so remove the restore/save of it around them. Signed-off-by: Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Handle VSX alignment faults correctly in little-endian modeNeil Campbell2009-12-181-17/+46
| | | | | | | | | | | | | | | This patch fixes the handling of VSX alignment faults in little-endian mode (the current code assumes the processor is in big-endian mode). The patch also makes the handlers clear the top 8 bytes of the register when handling an 8 byte VSX load. This is based on 2.6.32. Signed-off-by: Neil Campbell <neilc@linux.vnet.ibm.com> Cc: <stable@kernel.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Create PPC_WARN_ALIGNMENT to match PPC_WARN_EMULATEDAnton Blanchard2009-10-281-6/+6
| | | | | | | | | | | perf_event wants a separate event for alignment and emulation faults, so create another emulation event. This will make it easy to hook in perf_event at one spot. We pass in regs which will be required for these events. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Keep track of emulated instructionsGeert Uytterhoeven2009-05-211-4/+16
| | | | | | | | | | | | If CONFIG_PPC_EMULATED_STATS is enabled, make available counters for the various classes of emulated instructions under /sys/kernel/debug/powerpc/emulated_instructions/ (assumed debugfs is mounted on /sys/kernel/debug). Optionally (controlled by /sys/kernel/debug/powerpc/emulated_instructions/do_warn), rate-limited warnings can be printed to the console when instructions are emulated. Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Fix load/store float double alignment handlerMichael Neuling2009-02-231-16/+13
| | | | | | | | | | | | When we introduced VSX, we changed the way FPRs are stored in the thread_struct. Unfortunately we missed the load/store float double alignment handler code when updating how we access FPRs in the thread_struct. Below fixes this and merges the little/big endian case. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add alignment handler for new lfiwzx instructionMichael Neuling2009-02-231-1/+1
| | | | | | | | | | lfiwzx is a new floating point load instruction in 2.06 that needs an alignment handler for Linux. Turns out to be the worlds easiest handler to add. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/vsx: Fix VSX alignment handler for regs 32-63Michael Neuling2009-02-131-1/+6
| | | | | | | | | Fix the VSX alignment handler for VSX registers > 32. 32-63 are stored in the VMX part of the thread_struct not the FPR part. Signed-off-by: Michael Neuling <mikey@neuling.org> CC: stable@kernel.org (2.6.27 & .28 please) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Fix uninitialised variable in VSX alignment codeMichael Neuling2008-09-031-1/+1
| | | | | | | | | | | This fixes an uninitialised variable in the VSX alignment code. It can cause warnings from GCC (noticed with gcc-4.1.1). Gcc is actually correct in this instance, and this bug could cause the alignment interrupt handler to send a SIGSEGV to the process on a legitimate access. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Add VSX load/store alignment exception handlerMichael Neuling2008-07-151-1/+57
| | | | | | | | | | | VSX loads and stores will take an alignment exception when the address is not on a 4 byte boundary. This add support for these alignment exceptions and will emulate the requested load or store. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: remove unused variable in emulate_fp_pairMichael Neuling2008-07-091-3/+3
| | | | | | | regs is not used in emulate_fp_pair so remove it. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add macros to access floating point registers in thread_struct.Michael Neuling2008-07-011-3/+3
| | | | | | | | | We are going to change where the floating point registers are stored in the thread_struct, so in preparation add some macros to access the floating point registers. Update all code to use these new macros. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Handle alignment faults on SPE load/store instructionsKumar Gala2007-09-141-0/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds code to handle alignment traps generated by the following SPE (signal processing engine) load/store instructions, by emulating the instruction in the kernel (as is done for other instructions that generate alignment traps): evldd[x] Vector Load Double Word into Double Word [Indexed] evldw[x] Vector Load Double into Two Words [Indexed] evldh[x] Vector Load Double into Four Half Words [Indexed] evlhhesplat[x] Vector Load Half Word into Half Words Even and Splat [Indexed] evlhhousplat[x] Vector Load Half Word into Half Word Odd Unsigned and Splat [Indexed] evlhhossplat[x] Vector Load Half Word into Half Word Odd Signed and Splat [Indexed] evlwhe[x] Vector Load Word into Two Half Words Even [Indexed] evlwhou[x] Vector Load Word into Two Half Words Odd Unsigned (zero-extended) [Indexed] evlwhos[x] Vector Load Word into Two Half Words Odd Signed (with sign extension) [Indexed] evlwwsplat[x] Vector Load Word into Word and Splat [Indexed] evlwhsplat[x] Vector Load Word into Two Half Words and Splat [Indexed] evstdd[x] Vector Store Double of Double [Indexed] evstdw[x] Vector Store Double of Two Words [Indexed] evstdh[x] Vector Store Double of Four Half Words [Indexed] evstwhe[x] Vector Store Word of Two Half Words from Even [Indexed] evstwho[x] Vector Store Word of Two Half Words from Odd [Indexed] evstwwe[x] Vector Store Word of Word from Even [Indexed] evstwwo[x] Vector Store Word of Word from Odd [Indexed] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Handle alignment faults on new FP load/store instructionsPaul Mackerras2007-08-171-8/+49
| | | | | | | | | | | | | | | | | | | | | | | | | This adds code to handle alignment traps generated by the following new floating-point load/store instructions, by emulating the instruction in the kernel (as is done for other instructions that generate alignment traps): lfiwax load floating-point as integer word algebraic indexed stfiwx store floating-point as integer word indexed lfdp load floating-point double pair lfdpx load floating-point double pair indexed stfdp store floating-point double pair stfdpx store floating-point double pair indexed All these except stfiwx are new in POWER6. lfdp/lfdpx/stfdp/stfdpx load and store 16 bytes of memory into an even/odd FP register pair. In little-endian mode each 8-byte value is byte-reversed separately (i.e. not as a 16-byte unit). lfiwax/stfiwx load or store the lower 4 bytes of a floating-point register from/to memory; lfiwax sets the upper 4 bytes of the FP register to the sign extension of the value loaded. Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Alignment exception uses __get/put_user_inatomicBenjamin Herrenschmidt2007-04-131-25/+31
| | | | | | | | | | | | | Make the alignment exception handler use the new _inatomic variants of __get/put_user. This fixes erroneous warnings in the very rare cases where we manage to have copy_tofrom_user_inatomic() trigger an alignment exception. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> arch/powerpc/kernel/align.c | 56 ++++++++++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 25 deletions(-) Signed-off-by: Paul Mackerras <paulus@samba.org>
* [PATCH] powerpc: Implement support for setting little-endian mode via prctlPaul Mackerras2006-06-091-71/+118
| | | | | | | | | | | | | | | | | | | | | | | | This adds the PowerPC part of the code to allow processes to change their endian mode via prctl. This also extends the alignment exception handler to be able to fix up alignment exceptions that occur in little-endian mode, both for "PowerPC" little-endian and true little-endian. We always enter signal handlers in big-endian mode -- the support for little-endian mode does not amount to the creation of a little-endian user/kernel ABI. If the signal handler returns, the endian mode is restored to what it was when the signal was delivered. We have two new kernel CPU feature bits, one for PPC little-endian and one for true little-endian. Most of the classic 32-bit processors support PPC little-endian, and this is reflected in the CPU feature table. There are two corresponding feature bits reported to userland in the AT_HWCAP aux vector entry. This is based on an earlier patch by Anton Blanchard. Signed-off-by: Paul Mackerras <paulus@samba.org>
* [PATCH] powerpc: merge align.cBenjamin Herrenschmidt2005-11-181-0/+530
This patch merges align.c, the result isn't quite what was in ppc64 nor what was in ppc32 :) It should implement all the functionalities of both though. Kumar, since you played with that in the past, I suppose you have some test cases for verifying that it works properly before I dig out the 601 machine ? :) Since it's likely that I won't be able to test all scenario, code inspection is much welcome. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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