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* Merge branch '4.0-fixes' into mips-for-linux-nextRalf Baechle2015-04-1312-191/+317
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| * MIPS: asm: elf: Set O32 default FPU flagsMarkos Chandras2015-04-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set good default FPU flags (FR0) for O32 binaries similar to what the kernel does for the N64/N32 ones. This also fixes a regression introduced in commit 46490b572544 ("MIPS: kernel: elf: Improve the overall ABI and FPU mode checks") when MIPS_O32_FP64_SUPPORT is disabled. In that case, the mips_set_personality_fp() did not set the FPU mode at all because it assumed that the FPU mode was already set properly. That led to O32 userland problems. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reported-by: Mans Rullgard <mans@mansr.com> Fixes: 46490b572544 ("MIPS: kernel: elf: Improve the overall ABI and FPU mode checks") Tested-by: Mans Rullgard <mans@mansr.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/9344/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lose_fpu(): Disable FPU when MSA enabledJames Hogan2015-04-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lose_fpu() function only disables the FPU in CP0_Status.CU1 if the FPU is in use and MSA isn't enabled. This isn't necessarily a problem because KSTK_STATUS(current), the version of CP0_Status stored on the kernel stack on entry from user mode, does always get updated and gets restored when returning to user mode, but I don't think it was intended, and it is inconsistent with the case of only the FPU being in use. Sometimes leaving the FPU enabled may also mask kernel bugs where FPU operations are executed when the FPU might not be enabled. So lets disable the FPU in the MSA case too. Fixes: 33c771ba5c5d ("MIPS: save/disable MSA in lose_fpu") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9323/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.Ralf Baechle2015-04-101-1/+0
| | | | | | | | | | | | | | | | | | This is no longer needed with the fixed, new and improved definition of cpu_has_mips_r2_exec_hazard in <asm/cpu-features.h>. For a discussion, see http://patchwork.linux-mips.org/patch/9539/. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Fix cpu_has_mips_r2_exec_hazard.Ralf Baechle2015-04-101-1/+32
| | | | | | | | | | | | | | | | | | | | Returns a non-zero value if the current processor implementation requires an IHB instruction to deal with an instruction hazard as per MIPS R2 architecture specification, zero otherwise. For a discussion, see http://patchwork.linux-mips.org/patch/9539/. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR caseMarkos Chandras2015-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu") replaced the "sub" instruction with addiu but it did not update the immediate value in the R10000_LLSC_WAR case. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu"") Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9385/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: r4kcache: Use correct base register for MIPS R6 cache flushesMarkos Chandras2015-04-101-44/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") added support for MIPS R6 cache flushes but it used the wrong base address register to perform the flushes so the same lines were flushed over and over. Moreover, replace the "addiu" instructions with LONG_ADDIU so the correct base address is calculated for 64-bit cores. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") Cc: linux-mips@linux-mips.org Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9384/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: asm: asm-eva: Introduce kernel load/store variantsMarkos Chandras2015-04-101-44/+93
| | | | | | | | | | | | | | | | | | | | | | | | Introduce new macros for kernel load/store variants which will be used to perform regular kernel space load/store operations in EVA mode. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Remove udelay() causing huge IRQ latencyAlexander Sverdlin2015-04-101-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon platforms because these operations are called from PCI_OP_READ() and PCI_OP_WRITE() under raw_spin_lock_irqsave(). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney@cavium.com> Cc: Rob Herring <robh@kernel.org> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Masanari Iida <standby24x7@gmail.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Mathias <mathias.rulf@nokia.com> Patchwork: https://patchwork.linux-mips.org/patch/9576/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Fix race condition in lazy cache flushing.Lars Persson2015-03-251-15/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lazy cache flushing implemented in the MIPS kernel suffers from a race condition that is exposed by do_set_pte() in mm/memory.c. A pre-condition is a file-system that writes to the page from the CPU in its readpage method and then calls flush_dcache_page(). One example is ubifs. Another pre-condition is that the dcache flush is postponed in __flush_dcache_page(). Upon a page fault for an executable mapping not existing in the page-cache, the following will happen: 1. Write to the page 2. flush_dcache_page 3. flush_icache_page 4. set_pte_at 5. update_mmu_cache (commits the flush of a dcache-dirty page) Between steps 4 and 5 another thread can hit the same page and it will encounter a valid pte. Because the data still is in the L1 dcache the CPU will fetch stale data from L2 into the icache and execute garbage. This fix moves the commit of the cache flush to step 3 to close the race window. It also reduces the amount of flushes on non-executable mappings because we never enter __flush_dcache_page() for non-aliasing CPUs. Regressions can occur in drivers that mistakenly relies on the flush_dcache_page() in get_user_pages() for DMA operations. [ralf@linux-mips.org: Folded in patch 9346 to fix highmem issue.] Signed-off-by: Lars Persson <larper@axis.com> Cc: linux-mips@linux-mips.org Cc: paul.burton@imgtec.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9346/ Patchwork: https://patchwork.linux-mips.org/patch/9738/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * Revert "MIPS: Remove race window in page fault handling"Lars Persson2015-03-251-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Revert commit 2a4a8b1e5d9d ("MIPS: Remove race window in page fault handling") because it increased the number of flushed dcache pages and became a performance problem for some workloads. Signed-off-by: Lars Persson <larper@axis.com> Cc: linux-mips@linux-mips.org Cc: paul.burton@imgtec.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9345/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: OCTEON: Use correct CSR to soft resetChandrakala Chavva2015-03-251-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Also delete unused cvmx_reset_octeon() This fixes reboot for Octeon III boards Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/9471/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Add support for XPA.Steven J. Hill2015-03-195-30/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for extended physical addressing (XPA) so that 32-bit platforms can access equal to or greater than 40 bits of physical addresses. NOTE: 1) XPA and EVA are not the same and cannot be used simultaneously. 2) If you configure your kernel for XPA, the PTEs and all address sizes become 64-bit. 3) Your platform MUST have working HIGHMEM support. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Rearrange PTE bits into fixed positions.Steven J. Hill2015-03-182-47/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch rearranges the PTE bits into fixed positions for R2 and later cores. In the past, the TLB handling code did runtime checking of RI/XI and adjusted the shifts and rotates in order to fit the largest PFN value into the PTE. The checking now occurs when building the TLB handler, thus eliminating those checks. These new arrangements also define the largest possible PFN value that can fit in the PTE. HUGE page support is only available for 64-bit cores. Layouts of the PTE bits are now: 64-bit, R1 or earlier: CCC D V G [S H] M A W R P 32-bit, R1 or earler: CCC D V G M A W R P 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P 32-bit, R2 or later: CCC D V G RI/R XI M A W P [ralf@linux-mips.org: Fix another build error *rant* *rant*] Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9353/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch '4.1-fp' into mips-for-linux-nextRalf Baechle2015-04-134-131/+173
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| * | MIPS: MSA: Fix big-endian FPR_IDX implementationJames Hogan2015-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The maximum word size is 64-bits since MSA state is saved using st.d which stores two 64-bit words, therefore reimplement FPR_IDX using xor, and only within each 64-bit word. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9169/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | Revert "MIPS: Don't assume 64-bit FP registers for context switch"James Hogan2015-03-272-128/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 02987633df7ba2f62967791dda816eb191d1add3. The basic premise of the patch was incorrect since MSA context (including FP state) is saved using st.d which stores two consecutive 64-bit words in memory rather than a single 128-bit word. This means that even with big endian MSA, the FP state is still in the first 64-bit word. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9168/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: disable FPU if the mode is unsupportedPaul Burton2015-03-271-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The expected semantics of __enable_fpu are for the FPU to be enabled in the given mode if possible, otherwise for the FPU to be left disabled and SIGFPE returned. The FPU was incorrectly being left enabled in cases where the desired value for FR was unavailable. Without ensuring the FPU is disabled in this case, it would be possible for userland to go on to execute further FP instructions natively in the incorrect mode, rather than those instructions being trapped & emulated as they need to be. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9167/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA supportPaul Burton2015-03-271-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Uses of the cfcmsa & ctcmsa instructions were not being wrapped by a macro in the case where the toolchain supports MSA, since the arguments exactly match a typical use of the instructions. However using current toolchains this leads to errors such as: arch/mips/kernel/genex.S:437: Error: opcode not supported on this processor: mips32r2 (mips32r2) `cfcmsa $5,1' Thus uses of the instructions must be in the context of a ".set msa" directive, however doing that from the users of the instructions would be messy due to the possibility that the toolchain does not support MSA. Fix this by renaming the macros (prepending an underscore) in order to avoid recursion when attempting to emit the instructions, and provide implementations for the TOOLCHAIN_SUPPORTS_MSA case which ".set msa" as appropriate. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9163/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: remove MSA macro recursionPaul Burton2015-03-271-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recursive macros made the code more concise & worked great for the case where the toolchain doesn't support MSA. However, with toolchains which do support MSA they lead to build failures such as: arch/mips/kernel/r4k_switch.S: Assembler messages: arch/mips/kernel/r4k_switch.S:148: Error: invalid operands `insert.w $w(0+1)[2],$1' arch/mips/kernel/r4k_switch.S:148: Error: invalid operands `insert.w $w(0+1)[3],$1' arch/mips/kernel/r4k_switch.S:148: Error: invalid operands `insert.w $w((0+1)+1)[2],$1' arch/mips/kernel/r4k_switch.S:148: Error: invalid operands `insert.w $w((0+1)+1)[3],$1' ... Drop the recursion from msa_init_all_upper invoking the msa_init_upper macro explicitly for each vector register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9162/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: assume at as source/dest of MSA copy/insert instructionsPaul Burton2015-03-271-16/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Push .set mips64r* into the functions needing itPaul Burton2015-03-271-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The {save,restore}_fp_context{,32} functions require that the assembler allows the use of sdc instructions on any FP register, and this is acomplished by setting the arch to mips64r2 or mips64r6 (using MIPS_ISA_ARCH_LEVEL_RAW). However this has the effect of enabling the assembler to use mips64 instructions in the expansion of pseudo-instructions. This was done in the (now-reverted) commit eec43a224cf1 "MIPS: Save/restore MSA context around signals" which led to my mistakenly believing that there was an assembler bug, when in reality the assembler was just emitting mips64 instructions. Avoid the issue for future commits which will add code to r4k_fpu.S by pushing the .set MIPS_ISA_ARCH_LEVEL_RAW directives into the functions that require it, and remove the spurious assertion declaring the assembler bug. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [james.hogan@imgtec.com: Rebase on v4.0-rc1 and reword commit message to reflect use of MIPS_ISA_ARCH_LEVEL_RAW] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9612/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: lose_fpu(): Disable FPU when MSA enabledJames Hogan2015-03-271-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lose_fpu() function only disables the FPU in CP0_Status.CU1 if the FPU is in use and MSA isn't enabled. This isn't necessarily a problem because KSTK_STATUS(current), the version of CP0_Status stored on the kernel stack on entry from user mode, does always get updated and gets restored when returning to user mode, but I don't think it was intended, and it is inconsistent with the case of only the FPU being in use. Sometimes leaving the FPU enabled may also mask kernel bugs where FPU operations are executed when the FPU might not be enabled. So lets disable the FPU in the MSA case too. Fixes: 33c771ba5c5d ("MIPS: save/disable MSA in lose_fpu") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9323/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Provide a plat_post_dma_flush hookFlorian Fainelli2015-04-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Broadcom BCM63xx DSL SoCs utilize BMIPS CPUs, and as such are required to perform a read-ahead cache flush after a DMA transfer. Utilize asm/bmips.h to provide a plat_post_dma_flush_hook, and mach-generic/dma-coherence.h for everything else. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/9726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: DMA: Allow platforms to override only the post DMA hookFlorian Fainelli2015-04-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of having platforms to copy the entirety of mach-generic/dma-coherence.h, check whether these platforms have already defined a plat_post_dma_flush hook, and if not, provide an inline stub. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/9725/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BMIPS: Move post DMA flush implementation to common headerFlorian Fainelli2015-04-082-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/mips/include/asm/mach-bmips/dma-coherence.h contains the plat_post_dma_flush implementation which is not specific to mach-bmips, but required for all BMIPS-based systems. Move plat_post_dma_flush to arch/mips/include/asm/bmips.h, rename it to bmips_post_dma_flush such that other platforms like bcm63xx can utilize it. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/9724/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Respect the ISA level in FCSR handlingMaciej W. Rozycki2015-04-084-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the central place the default FCSR value is set from, initialised in `cpu_probe'. Determine the FCSR mask applied to values written to the register with CTC1 in the full emulation mode and via ptrace(2), according to the ISA level of processor hardware or the writability of bits 31:18 if actual FPU hardware is used. Software may rely on FCSR bits whose functions our emulator does not implement, so it should not allow them to be set or software may get confused. For ptrace(2) it's just sanity. [ralf@linux-mips.org: Fixed double inclusion of <asm/current.h>.] Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9711/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: math-emu: Define IEEE 754-2008 feature control bitsMaciej W. Rozycki2015-04-081-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | Define IEEE 754-2008 feature control bits: FIR.HAS2008, FCSR.ABS2008 and FCSR.NAN2008, and update the `_ieee754_csr' structure accordingly. For completeness define FIR.UFRP too. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9709/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: math-emu: Implement the FCCR, FEXR and FENR registersMaciej W. Rozycki2015-04-081-12/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the FCCR, FEXR and FENR "shadow" FPU registers for the architecture levels that include them, for the CFC1 and CTC1 instructions in the full emulation mode. For completeness add macros for the CP1 UFR and UNFR registers too, no actual implementation though. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Set `si_code' for SIGFPE signals sent from emulation tooMaciej W. Rozycki2015-04-082-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Correct FP ISA requirementsMaciej W. Rozycki2015-04-081-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct ISA requirements for floating-point instructions: * the CU3 exception signifies a real COP3 instruction in MIPS I & II, * the BC1FL and BC1TL instructions are not supported in MIPS I, * the SQRT.fmt instructions are indeed supported in MIPS II, * the LDC1 and SDC1 instructions are indeed supported in MIPS32r1, * the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions are indeed supported in MIPS32, * the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in MIPS32r2 and MIPS32r6, * the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions are indeed supported in MIPS32r2 and MIPS32r6, * the RSQRT.fmt and RECIP.fmt instructions are indeed supported in MIPS64r1, Also simplify conditionals for MIPS III and MIPS IV FPU instructions and the handling of the MOVCI minor opcode. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Correct MIPS I FP context layoutMaciej W. Rozycki2015-04-081-64/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the correct ordering of individual floating-point registers within double-precision register pairs for the MIPS I FP context, as required by our FP emulation code and expected by userland talking via ptrace(2). Use L.D and S.D assembly macros that do the right thing like LDC1 and SDC1 from MIPS II up, avoiding the need to mess up with endianness conditionals. This in particular fixes the handling of denormals and NaN generation in Unimplemented Operation emulation traps. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Correct `nofpu' non-functionalityMaciej W. Rozycki2015-04-087-6/+1
| | | | | | | | | | | | | | | | | | | | | | The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu' kernel option will be ignored. Remove any such overrides and add a cautionary note. Hardcoding to 0 is fine for FPU-less platforms. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9694/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: bitops.h: Avoid inline asm for constant FLSMaciej W. Rozycki2015-04-081-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC is smart enough to substitute the final result for FLS calculations as implemented in the fallback C code we have in `__fls' and `fls' applied to constant values. The presence of inline asm defeats the compiler though, forcing it to emit extraneous CLZ/DCLZ calculation for processors that support these instructions. Use `__builtin_constant_p' then to avoid inline asm altogether for constants. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9681/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: mips-r2-to-r6-emul.h: Inline empty `mipsr2_decoder'Maciej W. Rozycki2015-04-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use `static inline' rather than `static __maybe_unused' for `mipsr2_decoder' in the empty case, making inlining explicit where it will happen anyway. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9678/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: mipsregs.h: Reindent CP0 Cause macrosMaciej W. Rozycki2015-04-081-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reindent CP0 Cause macros for a single space after #define, leaving extra indentation for individual Interrupt Pending bits as with CP0 Status register's Interrupt Mask bits. [ralf@linux-mips.org: Fix conflict.] [ralf@linux-mips.org: Fix indentation of the CAUSEB_FDCI and CAUSEF_FDCI definitions.] Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9669/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: mipsregs.h: Move TX39 macros out of the wayMaciej W. Rozycki2015-04-081-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TX39 CP0 Configuration Register 3 macro definitions have been randomly thrown in the middle of a block of CP0 Status register value macros. Move them to the end of the whole CP0 register value macro block, complementing the location of the TX39 Cache register name macro at the end of the CP0 register name macro block. [ralf@linux-mips.org: Fix conflict.] Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: mipsregs.h: Reorder CP1 macro definitionsMaciej W. Rozycki2015-04-081-72/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally CP1 macros were placed between CP0 register name macros and CP0 register value macros. As changes were applied to the header the position of CP1 macros gradually has become more and more arbitrary and two separate blocks were created. This may only cause confusion. Move them out of the way then and place together after all the CP0 macros. No semantic change. [ralf@linux-mips.org: Fix conflict.] Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9667/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: mipsregs.h: Remove broken commentsMaciej W. Rozycki2015-04-081-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove a duplicate FPU Status Register reference that has been there since forever and a mistakenly copied and pasted R4xx0 manual reference. [ralf@linux-mips.org: Fix conflict.] Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM47xx: Devices database update for 4.1 (or 4.2?)Rafał Miłecki2015-04-021-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/9656/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Remove prototype for copy_user_pageGuenter Roeck2015-04-021-2/+0
| | | | | | | | | | | | | | | | | | | | | | MIPS architecture code does not provide copy_user_page, so it should not provide a prototype for it either. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9266/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Loongson-3: Add CPU Hwmon platform driverHuacai Chen2015-04-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This add CPU Hwmon (temperature sensor) platform driver for Loongson-3. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9617/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: PCI: Add a hook for IORESOURCE_BUS in pci_controller/bridge_controllerJoshua Kinard2015-04-012-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On SGI Origin 2k/Onyx2 and SGI Octane systems, there can exist multiple PCI buses attached to the Xtalk bus. The current code will stop counting PCI buses after it finds the first one. If one installs the optional PCI cardcage ("shoebox") into these systems, because of the order of the Xtalk widgets, the current PCI code will find the cardcage first, and fail to detect the BaseIO PCI devices, which are on a higher Xtalk widget ID. This patch adds the hooks needed for resolving this issue in the IP27 PCI code (in a later patch). Verified on both an SGI Onyx2 and an SGI Octane. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9074/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Use bool function return values of true/false not 1/0Joe Perches2015-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | Use the normal return values for bool functions Signed-off-by: Joe Perches <joe@perches.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9640/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Octeon: Reverse the order of register accesses to the FAUPaul Martin2015-04-011-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | 64 bit access is unaffected but for 32 bit access, swap high and low words. Similarly for 16 bit access, reverse the order of the four possible words, and for 8 bit access reverse the order of byte accesses. Signed-off-by: Paul Martin <paul.martin@codethink.co.uk> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9630/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Octeon: Turn hardware bitfields and structures inside out.Paul Martin2015-04-018-0/+454
| | | | | | | | | | | | | | | | | | | | | | Although the proper way to do this for bitfields would be to use the macro that Ralf has provided, this is a little easier to understand as a diff. Signed-off-by: Paul Martin <paul.martin@codethink.co.uk> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9628/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Add R16000 detectionJoshua Kinard2015-04-012-3/+4
| | | | | | | | | | | | | | | | | | | | | | This allows the kernel to correctly detect an R16000 MIPS CPU on systems that have those. Otherwise, such systems will detect the CPU as an R14000, due to similarities in the CPU PRId value. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9092/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: SEAD3: New header file sead3-addr.h with hardware addresses.Ralf Baechle2015-04-011-0/+83
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BMIPS: Flush the readahead cache after DMA.Ralf Baechle2015-04-011-0/+16
| | | | | | | | | | | | | | | | | | | | | | BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer may cause parts of the DMA buffer to be prefetched into the RAC. To avoid possible coherency problems, flush the RAC upon DMA completion. Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: DMA: Implement platform hook to perform post-DMA cache flushes.Ralf Baechle2015-04-018-0/+32
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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