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* MIPS: Octeon: mangle-port: fix build failure with VDSO codeAaro Koskinen2016-09-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1685ddbe35cd ("MIPS: Octeon: Changes to support readq()/writeq() usage.") added bitwise shift operations that assume that unsigned long is always 64-bits. This broke the build of VDSO code, as it gets compiled also in "faked" 32-bit mode. Althought the failing inline functions are never executed in 32-bit mode, they still need to pass the compilation. Fix by using 64-bit types explicitly. The patch fixes the following build failure: CC arch/mips/vdso/gettimeofday-o32.o In file included from los/git/devel/linux/arch/mips/include/asm/io.h:32:0, from los/git/devel/linux/arch/mips/include/asm/page.h:194, from los/git/devel/linux/arch/mips/vdso/vdso.h:26, from los/git/devel/linux/arch/mips/vdso/gettimeofday.c:11: los/git/devel/linux/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h: In function '__should_swizzle_bits': los/git/devel/linux/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h:19:40: error: right shift count >= width of type [-Werror=shift-count-overflow] unsigned long did = ((unsigned long)a >> 40) & 0xff; ^~ Fixes: 1685ddbe35cd ("MIPS: Octeon: Changes to support readq()/writeq() usage.") Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: David Daney <ddaney@caviumnetworks.com> Cc: David Daney <david.daney@cavium.com> Cc: Steven J. Hill <steven.hill@cavium.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14039/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2016-08-062-31/+13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for 4.8. Also includes is a minor SSB cleanup as SSB code traditionally is merged through the MIPS tree: ATH25: - MIPS: Add default configuration for ath25 Boot: - For zboot, copy appended dtb to the end of the kernel - store the appended dtb address in a variable BPF: - Fix off by one error in offset allocation Cobalt code: - Fix typos Core code: - debugfs_create_file returns NULL on error, so don't use IS_ERR for testing for errors. - Fix double locking issue in RM7000 S-cache code. This would only affect RM7000 ARC systems on reboot. - Fix page table corruption on THP permission changes. - Use compat_sys_keyctl for 32 bit userspace on 64 bit kernels. David says, there are no compatibility issues raised by this fix. - Move some signal code around. - Rewrite r4k count/compare clockevent device registration such that min_delta_ticks/max_delta_ticks files are guaranteed to be initialized. - Only register r4k count/compare as clockevent device if we can assume the clock to be constant. - Fix MSA asm warnings in control reg accessors - uasm and tlbex fixes and tweaking. - Print segment physical address when EU=1. - Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO. - CP: Allow booting by VP other than VP 0 - Cache handling fixes and optimizations for r4k class caches - Add hotplug support for R6 processors - Cleanup hotplug bits in kconfig - traps: return correct si code for accessing nonmapped addresses - Remove cpu_has_safe_index_cacheops Lantiq: - Register IRQ handler for virtual IRQ number - Fix EIU interrupt loading code - Use the real EXIN count - Fix build error. Loongson 3: - Increase HPET_MIN_PROG_DELTA and decrease HPET_MIN_CYCLES Octeon: - Delete built-in DTB pruning code for D-Link DSR-1000N. - Clean up GPIO definitions in dlink_dsr-1000n.dts. - Add more LEDs to the DSR-100n DTS - Fix off by one in octeon_irq_gpio_map() - Typo fixes - Enable SATA by default in cavium_octeon_defconfig - Support readq/writeq() - Remove forced mappings of USB interrupts. - Ensure DMA descriptors are always in the low 4GB - Improve USB reset code for OCTEON II. Pistachio: - Add maintainers entry for pistachio SoC Support - Remove plat_setup_iocoherency Ralink: - Fix pwm UART in spis group pinmux. SSB: - Change bare unsigned to unsigned int to suit coding style Tools: - Fix reloc tool compiler warnings. Other: - Delete use of ARCH_WANT_OPTIONAL_GPIOLIB" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (61 commits) MIPS: mm: Fix definition of R6 cache instruction MIPS: tools: Fix relocs tool compiler warnings MIPS: Cobalt: Fix typo MIPS: Octeon: Fix typo MIPS: Lantiq: Fix build failure MIPS: Use CPHYSADDR to implement mips32 __pa MIPS: Octeon: Dlink_dsr-1000n.dts: add more leds. MIPS: Octeon: Clean up GPIO definitions in dlink_dsr-1000n.dts. MIPS: Octeon: Delete built-in DTB pruning code for D-Link DSR-1000N. MIPS: store the appended dtb address in a variable MIPS: ZBOOT: copy appended dtb to the end of the kernel MIPS: ralink: fix spis group pinmux MIPS: Factor o32 specific code into signal_o32.c MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present MIPS: Use per-mm page to execute branch delay slot instructions MIPS: Modify error handling MIPS: c-r4k: Use SMP calls for CM indexed cache ops MIPS: c-r4k: Avoid small flush_icache_range SMP calls MIPS: c-r4k: Local flush_icache_range cache op override MIPS: c-r4k: Split r4k_flush_kernel_vmap_range() ...
| * MIPS: Octeon: Remove forced mappings of USB interrupts.Steven J. Hill2016-07-281-2/+0
| | | | | | | | | | | | | | | | | | | | | | Get rid of unnecessary forced interrupt mappings for the USB host controller on OCTEON II. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13824/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Changes to support readq()/writeq() usage.Steven J. Hill2016-07-111-29/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update OCTEON port mangling code to support readq() and writeq() functions to allow driver code to be more portable. Updates also for word and long function pairs. We also remove SWAP_IO_SPACE for OCTEON platforms as the function macros are redundant with the new mangling code. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13780/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Clean up RDHWR handlingJames Hogan2016-06-151-1/+1
|/ | | | | | | | | | | | | | | | | | | No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* MIPS: Fix misspellings in comments.Adam Buchbinder2016-04-031-1/+1
| | | | | | | | Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12617/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove all the uses of custom gpio.hAlban Bedel2015-09-031-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently CONFIG_ARCH_HAVE_CUSTOM_GPIO_H is defined for all MIPS machines, and each machine type provides its own gpio.h. However only a handful really implement the GPIO API, most just forward everythings to gpiolib. The Alchemy machine is notable as it provides a system to allow implementing the GPIO API at the board level. But it is not used by any board currently supported, so it can also be removed. For most machine types we can just remove the custom gpio.h, as well as the custom wrappers if some exists. Some of the code found in the wrappers must be moved to the respective GPIO driver. A few more fixes are need in some drivers as they rely on linux/gpio.h to provides some machine specific definitions, or used asm/gpio.h instead of linux/gpio.h for the gpio API. Signed-off-by: Alban Bedel <albeu@free.fr> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Tejun Heo <tj@kernel.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Florian Fainelli <florian@openwrt.org> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Joe Perches <joe@perches.com> Cc: Daniel Walter <dwalter@google.com> Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: James Hartley <james.hartley@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Varka Bhadram <varkabhadram@gmail.com> Cc: Masanari Iida <standby24x7@gmail.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Michael Buesch <m@bues.ch> Cc: abdoulaye berthe <berthe.ab@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-ide@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-input@vger.kernel.org Cc: netdev@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10828/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '4.0-fixes' into mips-for-linux-nextRalf Baechle2015-04-131-1/+0
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| * MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.Ralf Baechle2015-04-101-1/+0
| | | | | | | | | | | | | | | | | | This is no longer needed with the fixed, new and improved definition of cpu_has_mips_r2_exec_hazard in <asm/cpu-features.h>. For a discussion, see http://patchwork.linux-mips.org/patch/9539/. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: DMA: Implement platform hook to perform post-DMA cache flushes.Ralf Baechle2015-04-011-0/+4
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.hDavid Daney2015-04-011-0/+74
|/ | | | | | | | | | | | Needed for little-endian ioport access. This fixes NOR flash in little-endian mode Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9591/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: More OCTEONIII supportChandrakala Chavva2015-02-201-0/+3
| | | | | | | | | | | | Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII. Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8945/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.Chad Reese2015-02-201-20/+0
| | | | | | | | | | | | | | CN38XX pass 1 required icache prefetching to be turned off. This chip never reached production and is long dead. Other processor specific icache settings are done by the bootloader. Remove these bits from the kernel. Signed-off-by: Chad Reese <kreese@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/8944/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.David Daney2015-02-201-3/+16
| | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8943/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Implement DCache errata workaround for all CN6XXXDavid Daney2015-02-201-0/+3
| | | | | | | | | | | Make messages refer to all CN6XXX. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8941/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Implement the core-16057 workaroundDavid Daney2015-02-201-0/+22
| | | | | | | | | | | Disable ICache prefetch for certian Octeon II processors. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8938/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use WSBH/DSBH/DSHD on Loongson 3AChen Jie2014-09-221-0/+1
| | | | | | | | | Signed-off-by: chenj <chenj@lemote.com> Cc: linux-mips@linux-mips.org Cc: chenhc@lemote.com Patchwork: https://patchwork.linux-mips.org/patch/7542/ Patchwork: https://patchwork.linux-mips.org/patch/7550/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Add twsi interrupt initialization for OCTEON 3XXX, 5XXX, 63XXEunbong Song2014-06-041-0/+2
| | | | | | | | | | | | In octeon_3xxx.dts file, there is a definiton for twsi/twsi2 interrupts. But there is no code for initialization of this interrupts. This patch adds code for initialization of twsi interrupts. Signed-off-by: Eunbong Song <eunb.song@samsung.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6816/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Enable use of FPUDavid Daney2014-05-301-1/+0
| | | | | | | | | | | | | | | | | | | | Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove unnecessary platform dma helper functionsFelix Fietkau2013-10-291-12/+0
| | | | | | | | | | | The semantics stay the same - on Cavium Octeon the functions were dead code (it overrides the MIPS DMA ops) - on other platforms they contained no code at all. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5720/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIBDavid Daney2013-08-261-0/+21
| | | | | | | | | | | | | | | ... and create asm/mach-cavium-octeon/gpio.h so that things continue to build. This allows us to use the existing I2C connected GPIO expanders. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5632/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '3.10-fixes' into mips-for-linux-nextRalf Baechle2013-07-122-0/+31
|\ | | | | | | | | This that should have been fixed but weren't, way to much, intrusive and late.
| * MIPS/OCTEON: Override default address space layout.David Daney2013-06-211-0/+24
| | | | | | | | | | | | | | | | | | | | OCTEON II cannot execute code in the default CAC_BASE space, so we supply a value (0x8000000000000000) that does work. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5457/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Fix build error if CONFIG_BUG=nDavid Daney2013-06-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CC init/do_mounts.o In file included from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/dma-mapping.h:10:0, from include/linux/dma-mapping.h:76, from include/linux/skbuff.h:33, from include/linux/icmpv6.h:4, from include/linux/ipv6.h:59, from include/net/ipv6.h:16, from include/linux/sunrpc/clnt.h:26, from include/linux/nfs_fs.h:30, from init/do_mounts.c:30: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:24:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem_page’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:30:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_addr_to_phys’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:36:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_supported’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:47:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_mapping_error’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:63:1: warning: no return statement in function returning non-void [-Wreturn-type] LD init/mounts.o CC init/init_task.o In file included from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/dma-mapping.h:10:0, from include/linux/dma-mapping.h:76, from include/linux/skbuff.h:33, from include/linux/netfilter.h:5, from include/net/netns/netfilter.h:5, from include/net/net_namespace.h:20, from include/linux/init_task.h:14, from init/init_task.c:1: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:24:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem_page’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:30:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_addr_to_phys’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:36:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_supported’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:47:1: warning: no return statement in function returning non-void [-Wreturn-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_mapping_error’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:63:1: warning: no return statement in function returning non-void [-Wreturn-type] LD init/built-in.o CC arch/mips/cavium-octeon/setup.o In file included from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/dma-mapping.h:10:0, from include/linux/dma-mapping.h:76, from include/asm-generic/pci-dma-compat.h:7, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/pci.h:129, from include/linux/pci.h:1451, from /home/ralf/src/linux/linux-mips/arch/mips/include/asm/octeon/pci-octeon.h:12, from arch/mips/cavium-octeon/setup.c:41: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:24:1: error: no return statement in function returning non-void [-Werror=return-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_map_dma_mem_page’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:30:1: error: no return statement in function returning non-void [-Werror=return-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_addr_to_phys’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:36:1: error: no return statement in function returning non-void [-Werror=return-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_supported’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:47:1: error: no return statement in function returning non-void [-Werror=return-type] /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h: In function ‘plat_dma_mapping_error’: /home/ralf/src/linux/linux-mips/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h:63:1: error: no return statement in function returning non-void [-Werror=return-type] cc1: all warnings being treated as errors make[2]: *** [arch/mips/cavium-octeon/setup.o] Error 1 make[1]: *** [arch/mips/cavium-octeon] Error 2 make: *** [arch/mips] Error 2 [ralf@linux-mips.org: while at it, also include <linux/bug.h> directly.] Signed-off-by: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5519/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: OCTEON: Get rid of CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNEDDavid Daney2013-06-101-6/+1
|/ | | | | | | | | | | | | When you turn it off, the kernel is unusable, so get rid of the option and always allow unaligned access. The Octeon specific memcpy intentionally does unaligned accesses and it must not fault. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5303/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-012-20/+20
| | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle2012-12-131-1/+0
| | | | | | | Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree.David Daney2012-12-131-1/+0
| | | | | | | | | | | | | The patch needs to eliminate the definition of OCTEON_IRQ_BOOTDMA so that the device tree code can map the interrupt, so in order to not temporarily break things, we do a single patch to both the interrupt registration code and the pata_octeon_cf driver. Also rolled in is a conversion to use hrtimers and corrections to the timing calculations. Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David Daney <david.daney@cavium.com>
* MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.Ralf Baechle2012-10-111-0/+1
| | | | | | | | Most supported systems currently hardwire cpu_has_dsp to 0, so we also can disable support for cpu_has_dsp2 resulting in a slightly smaller kernel. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'rixi-3.7' of ↵Ralf Baechle2012-09-281-1/+1
|\ | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill2012-09-131-1/+1
| | | | | | | | | | | | | | | | Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
* | MIPS: OCTEON: Add OCTEON_IRQ_* definitions for cn68XX chips.David Daney2012-08-311-3/+4
| | | | | | | | | | | | There are 64 workqueue, 32 watchdog, and 4 mbox. Signed-off-by: David Daney <david.daney@cavium.com>
* | MIPS: Octeon: Fix broken interrupt controller code.David Daney2012-08-171-9/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 3.6.0-rc1, We are getting many messages like: WARNING: at kernel/irq/irqdomain.c:444 irq_domain_associate_many+0x23c/0x260() Modules linked in: Call Trace: [<ffffffff814cb698>] dump_stack+0x8/0x34 [<ffffffff81133d00>] warn_slowpath_common+0x78/0xa8 [<ffffffff81187e44>] irq_domain_associate_many+0x23c/0x260 [<ffffffff81187f38>] irq_create_mapping+0xd0/0x220 [<ffffffff81188104>] irq_create_of_mapping+0x7c/0x158 [<ffffffff813e5f08>] irq_of_parse_and_map+0x28/0x40 . . . Both the CIU and GPIO interrupt domains were somewhat screwed up. For the CIU domain, we need to call irq_domain_associate() for each of the preassigned irq numbers. For the GPIO domain, we were applying the register bit offset in octeon_irq_gpio_xlat, but it should be done in octeon_irq_gpio_map instead. Also: Reserve all 8 'core' irqs for the 'core' irq_chip so that they don't get used by the other domains. Remove unused OCTEON_IRQ_* symbols. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4190/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Remove unneeded OCTEON_IRQ_* defines.David Daney2012-07-231-38/+2
| | | | | | | | | | | The follow-on patch to add irq_domain support will be the supported method for using these irq lines, so get these defines out of the way in preperation for that. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3930/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Remove use of OCTEON_IRQ_RST.David Daney2012-07-231-2/+3
| | | | | | | | | | | | | This symbol will be removed, so don't use it as part of the definition of OCTEON_IRQ_LAST. Set OCTEON_IRQ_LAST to 127 so there is space for all the automatically allocated (via irq_domain) irqs. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3946/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Enable C0_UserLocal probing.David Daney2011-09-241-1/+0
| | | | | | | | | | | Octeon2 processor cores have a UserLocal register. Remove the hard coded negative probe and allow the standard probing to detect this feature. Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2578/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Octeon: Fix interrupt irq settings for performance counters.Chandrakala Chavva2011-05-191-0/+5
| | | | | | | | | | | | Octeon uses different interrupt irq for timer and performance counters. Set CvmCtl[IPPCI] to correct irq value very early. Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Chandrakala Chavva <cchavva@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/2085/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Rewrite interrupt handling code.David Daney2011-03-291-162/+81
| | | | | | | | | | | | | | | | | This includes conversion to new style irq_chip functions, and correctly enabling/disabling per-CPU interrupts. The hardware interrupt bit to irq number mapping is now done with a flexible map, instead of by bit twiddling the irq number. [ tglx: Adjusted to new irq_cpu_on/offline callbacks and __irq_set_affinity_lock ] Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org LKML-Reference: <1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II.David Daney2010-10-291-1/+1
| | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Rewrite DMA mapping functions.David Daney2010-10-291-8/+14
| | | | | | | | | | | | | All Octeon chips can support more than 4GB of RAM. Also due to how Octeon PCI is setup, even some configurations with less than 4GB of RAM will have portions that are not accessible from 32-bit devices. Enable the swiotlb code to handle the cases where a device cannot directly do DMA. This is a complete rewrite of the Octeon DMA mapping code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1639/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Convert DMA to use dma-mapping-common.hDavid Daney2010-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | Use asm-generic/dma-mapping-common.h to handle all DMA mapping operations and establish a default get_dma_ops() that forwards all operations to the existing code. Augment dev_archdata to carry a pointer to the struct dma_map_ops, allowing DMA operations to be overridden on a per device basis. Currently this is never filled in, so the default dma_map_ops are used. A follow-on patch sets this for Octeon PCI devices. Also initialize the dma_debug system as it is now used if it is configured. Includes fixes by Kevin Cernekee <cernekee@gmail.com>. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1637/ Patchwork: http://patchwork.linux-mips.org/patch/1678/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Adjust top of DMA32 zone.David Daney2010-10-291-0/+6
| | | | | | | | | | On OCTEON, we reserve the last 256MB of 32-bit PCI address space, mapping the RAM in this region at a high DMA address. This makes memory in this region unavailable for 32-bit DMA. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1634/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Support 256 MSI on PCIeDavid Daney2010-08-051-1/+1
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Implement delays with cycle counter.David Daney2010-08-051-11/+0
| | | | | | | | | | | Power throttling make deterministic delay loops impossible. Re-implement delays using the cycle counter. This also allows us to get rid of the code that calculates loops per jiffy. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1317/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Get rid of a bunch of MSI IRQ number definitions.David Daney2010-08-051-64/+2
| | | | | | | | | | MSI IRQ numbers are allocated dynamically, so there is no reason to have all these static definitions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Define ARCH_HAS_USABLE_BUILTIN_POPCOUNT for OCTEON.David Daney2010-08-051-0/+8
| | | | | | | | | | OCTEON implements __builtin_popcount with a single instruction, so lets use it. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/1431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUsDavid Daney2010-02-271-0/+3
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Set kernel_uses_llsc to false on non-SMP builds.David Daney2009-09-171-4/+8
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.hDavid Daney2009-06-171-0/+1
| | | | | | | | We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove it to mach-cavium-octeon/cpu-feature-overrides.h Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove execution hazard barriers for Octeon.David Daney2009-06-171-0/+1
| | | | | | | | | The Octeon has no execution hazards, so we can remove them and save an instruction per TLB handler invocation. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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