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* MIPS: Remove all the uses of custom gpio.hAlban Bedel2015-09-031-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently CONFIG_ARCH_HAVE_CUSTOM_GPIO_H is defined for all MIPS machines, and each machine type provides its own gpio.h. However only a handful really implement the GPIO API, most just forward everythings to gpiolib. The Alchemy machine is notable as it provides a system to allow implementing the GPIO API at the board level. But it is not used by any board currently supported, so it can also be removed. For most machine types we can just remove the custom gpio.h, as well as the custom wrappers if some exists. Some of the code found in the wrappers must be moved to the respective GPIO driver. A few more fixes are need in some drivers as they rely on linux/gpio.h to provides some machine specific definitions, or used asm/gpio.h instead of linux/gpio.h for the gpio API. Signed-off-by: Alban Bedel <albeu@free.fr> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Tejun Heo <tj@kernel.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Florian Fainelli <florian@openwrt.org> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: Joe Perches <joe@perches.com> Cc: Daniel Walter <dwalter@google.com> Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: James Hartley <james.hartley@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Varka Bhadram <varkabhadram@gmail.com> Cc: Masanari Iida <standby24x7@gmail.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Michael Buesch <m@bues.ch> Cc: abdoulaye berthe <berthe.ab@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-ide@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-input@vger.kernel.org Cc: netdev@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10828/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Unify Devboard support.Manuel Lauss2014-03-261-11/+8
| | | | | | | | | | | | | | This patch merges support for all DB1xxx and PB1xxx boards into a single image, along with a new single defconfig for them. Run-tested on DB1300 and DB1500. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6577/ Patchwork: https://patchwork.linux-mips.org/patch/6659/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Determine cohereny at runtime based on cpu typeManuel Lauss2014-03-261-5/+0
| | | | | | | | | | | | All Alchemy chips have coherent DMA, but for example the USB or AC97 peripherals on the Au1000/1500/1100 are not. This patch uses DMA_MAYBE_COHERENT on Alchemy and sets coherentio based on CPU type. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6576/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig: remove "config MIPS_DISABLE_OBSOLETE_IDE"Paul Bolle2013-05-081-3/+0
| | | | | | | | | | | | | | | | | | The Kconfig symbol MIPS_DISABLE_OBSOLETE_IDE was added in v2.6.10. It has never been used. Let's remove it. The symbol was originally introduced by the following commit commit 2bfa662b64a7ee593f3039c1d3fd81a7766a63cd Author: Pete Popov <ppopov@embeddedalley.com> Date: Tue Oct 12 06:24:19 2004 +0000 - Db1550 bug fixes - updated defconfig - updated Kconfig to use DMA_COHERENT since new silicon is coherent Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Patchwork: http://patchwork.linux-mips.org/patch/5064/ Acked-by: John Crispin <blogic@openwrt.org>
* MIPS: Alchemy: Merge PB1100/1500 support into DB1000 code.Manuel Lauss2012-10-111-18/+1
| | | | | | | | | | | | | The PB1100/1500 are similar to their DB-cousins but with a few more devices on the bus. This patch adds PB1100/1500 support to the existing DB1100/1500 code. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: lnux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4338/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: merge PB1550 support into DB1550 codeManuel Lauss2012-10-111-10/+1
| | | | | | | | | | | | | | The PB1550 is more or less a DB1550 without the PCI IDE controller, a more complicated (read: configurable) Flash setup and some other minor changes. Like the DB1550 it can be automatically detected by reading the CPLD ID register bits. This patch adds PB1550 detection and setup to the DB1550 code. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4337/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Single kernel for DB1200/1300/1550Manuel Lauss2012-10-111-19/+3
| | | | | | | | | | | | Combine support for the DB1200/PB1200, DB1300 and DB1550 boards into a single kernel image. defconfig-generated image verified on DB1200, DB1300 and DB1550. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4335/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: one kernel for DB1000/DB1500/DB1100Manuel Lauss2011-12-071-18/+3
| | | | | | | | | | | | These 3 boards are very similar; with this patch a single kernel image which runs on all three can be built. Tested on DB1500 and DB1100. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2872/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Merge PB1200 support into DB1200 code.Manuel Lauss2011-12-071-9/+1
| | | | | | | | | | | | | | | The PB1200 is basically a DB1200 with additional MMC and camera sockets and different base addresses for external hardware (CPLD, IDE, Net, NAND). This patch implements the missing PB1200 features in DB1200 support code and runtime board detection. Tested on DB1200 only. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2880/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Improved DB1550 support, with audio and serial busses.Manuel Lauss2011-12-071-1/+1
| | | | | | | Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Basic support for the DB1300 board.Manuel Lauss2011-12-071-0/+8
| | | | | | | | | Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2867/ Patchwork: https://patchwork.linux-mips.org/patch/2919/ Patchwork: https://patchwork.linux-mips.org/patch/2928/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Au1300 SoC supportManuel Lauss2011-12-071-0/+4
| | | | | | | | | | | | | | | Add basic support for the Au1300 variant(s): - New GPIO/Interrupt controller - DBDMA ids - USB setup - MMC support - enable various PSC drivers - detection code. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Drop MIRAGE/BOSPORUS board supportManuel Lauss2011-12-071-14/+0
| | | | | | | | | | | | No test hardware and no (apparent) users. These boards seem very similar to the DB1500, so if required support can be brought back again (I have datasheets) but then with dedicated board code, not tacked on to DB1000 support. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2864/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: remove PB1000 supportManuel Lauss2011-12-071-9/+0
| | | | | | | | | | | | Noone seems to have test hardware or care anymore. Drop PB1000 support and along with it the old Alchemy PCMCIA socket driver. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: linux-pcmcia@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/2881/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: remove all CONFIG_SOC_AU1??? definesManuel Lauss2011-10-241-35/+15
| | | | | | | | | | | | | Now that no driver any longer depends on the CONFIG_SOC_AU1??? symbols, it's time to get rid of them: Move some of the platform devices to the boards which can use them, Rename a few (unused) constants in the header, Replace them with MIPS_ALCHEMY in the various Kconfig files. Finally delete them altogether from the Alchemy Kconfig file. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Add basic support for the GPR boardWolfgang Grandegger2010-08-051-0/+9
| | | | | | | | | | | | From: Wolfgang Grandegger <wg@denx.de> Add basic support for the General Purpose Router (GPR) board from Trapeze ITS. Signed-off-by: Wolfgang Grandegger <wg@denx.de> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: remove SOC_AU1X00 in favor of MIPS_ALCHEMYManuel Lauss2010-08-051-18/+1
| | | | | | | | | | Remove the CONFIG_SOC_AU1X00 Kconfig symbol since its job can also be done by MACH_ALCHEMY, now renamed to MIPS_ALCHEMY. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/1461/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Only build AU1000 INTC code for compatible cpusManuel Lauss2010-02-271-7/+7
| | | | | | | | | | Use the GPIO config symbol to only build Au1000 interrupt code on chips with compatible hw. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/670/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: prom_putchar is board dependentManuel Lauss2010-02-271-0/+14
| | | | | | | | | | | | | | | This patch replaces the general alchemy prom_putchar() implementation in favor of board-specific versions: The UART where the output of prom_putchar is directed to really depends on the board, the current implementation hardcodes this on a per-SoC basis which is just wrong. So a generic uart tx function is provided in the alchemy headers, and the boards can provide their own prom_putchar with custom destination uart, and all in-kernel alchemy boards support early printk. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Rewrite GPIO support.Manuel Lauss2009-06-171-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current in-kernel Alchemy GPIO support is far too inflexible for all my use cases. To address this, the following changes are made: * create generic functions which deal with manipulating the on-chip GPIO1/2 blocks. Such functions are universally useful. * Macros for GPIO2 shared interrupt management and block control. * support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros. If CONFIG_GPIOLIB is not enabled, provide linux gpio framework compatibility by directly inlining the GPIO1/2 functions. GPIO access is limited to on-chip ones and they can be accessed as documented in the datasheets (GPIO0-31 and 200-215). If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and one for GPIO2, are registered. GPIOs can still be accessed by using the numberspace established in the databooks. However this is not yet flexible enough for my uses: My Alchemy systems have a documented "external" gpio interface (fixed, different numberspace) and can support a variety of baseboards, some of which are equipped with I2C gpio expanders. I want to be able to provide the default 16 GPIOs of the CPU board numbered as 0..15 and also support gpio expanders, if present, starting as gpio16. To achieve this, a new Kconfig symbol for Alchemy is introduced, CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal that they don't want the Alchemy numberspace exposed to the outside world, but instead want to provide their own. Boards are now respon- sible for providing the linux gpio interface glue code (either in a custom gpio.h header (in board include directory) or with gpio_chips). To make the board-specific inlined gpio functions work, the MIPS Makefile must be changed so that the mach-au1x00/gpio.h header is included _after_ the board headers, by moving the inclusion of the mach-au1x00/ to the end of the header list. See arch/mips/include/asm/mach-au1x00/gpio.h for more info. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platformsRalf Baechle2009-03-301-1/+0
| | | | | | __do_IRQ() is deprecated and will go away. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Au1000: convert to using gpiolibFlorian Fainelli2009-03-301-0/+1
| | | | | | | This patch converts the GPIO board code to use gpiolib. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: RTC counter clocksource / clockevent support.Manuel Lauss2009-01-111-2/+2
| | | | | | | | | | | | Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: update core interrupt code.Manuel Lauss2009-01-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch attempts to modernize core Alchemy interrupt handling code. - add irq_chips for irq controllers instead of irq type, - add a set_type() hook to change irq trigger type during runtime, - add a set_wake() hook to control GPIO0..7 based wakeup, - use linux' IRQF_TRIGGER_ constants instead of homebrew ones, - enable GENERIC_HARDIRQS_NO__DO_IRQ. - simplify plat_irq_dispatch - merge au1xxx_irqmap into irq.c file, the only place where its contents are referenced. - board_init_irq() is now mandatory for every board; use it to register the remaining (gpio-based) interrupt sources; update all boards accordingly. Run-tested on Db1200 and other Au1200 based platforms. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/au1xxx_irqmap.c
* MIPS: Alchemy: rename directoryRalf Baechle2008-10-111-0/+136
It's more than the au1000 these days. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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