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* [MIPS] Fix shadow register support.Ralf Baechle2007-11-151-9/+0
| | | | | | | | | | | | | Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Qemu: Add early printk, your friend in a cold night.Ralf Baechle2007-11-151-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Bigsur supports highmem.Ralf Baechle2007-11-021-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Split and move clock code.Ralf Baechle2007-11-021-0/+12
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] txx9tmr clockevent/clocksource driverAtsushi Nemoto2007-10-291-0/+6
| | | | | | | | | | | | | | Convert jmr3927_clock_event_device to more generic txx9tmr_clock_event_device which supports one-shot mode. The txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer interrupt was not available. Convert jmr3927_hpt_read to txx9_clocksource driver which does not depends jiffies anymore. The txx9_clocksource itself can be used for TX49, but normally TX49 uses higher precision clocksource_mips. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Add GT641xx timer0 clockevent driverYoichi Yuasa2007-10-221-0/+4
| | | | | | | | And make use of it for Cobalt. A few others such as the Malta could make use of it as well. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* typo fixesMatt LaPlante2007-10-201-1/+1
| | | | | | | | | | | | Most of these fixes were already submitted for old kernel versions, and were approved, but for some reason they never made it into the releases. Because this is a consolidation of a couple old missed patches, it touches both Kconfigs and documentation texts. Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
* Combine instrumentation menus in kernel/Kconfig.instrumentationMathieu Desnoyers2007-10-191-1/+1
| | | | | | | | | | | | | | | | | Quoting Randy: "It seems sad that this patch sources Kconfig.marker, a 7-line file, 20-something times. Yes, you (we) don't want to put those 7 lines into 20-something different files, so sourcing is the right thing. However, what you did for avr32 seems more on the right track to me: make _one_ Instrumentation support menu that includes PROFILING, OPROFILE, KPROBES, and MARKERS and then use (source) that in all of the arches." Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] time: Move R4000 clockevent device code to separate configurable fileRalf Baechle2007-10-181-0/+24
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Lasat: Fix build by conversion to irq_cpu.c.Ralf Baechle2007-10-161-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP32: Fix build by conversion to irq_cpu.c.Ralf Baechle2007-10-161-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] i8253 PIT clocksource and clockevent driversRalf Baechle2007-10-111-0/+9
| | | | | | Derived from the i386 variant with a few x86 complexities chopped off. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Dyntick support for SMTC:Ralf Baechle2007-10-111-0/+4
| | | | | | | | | The kernel currently only supports broadcasting of the timer interrupt from a single timer, not multicasting into two multicast groups of processors. So the implemented mechanism for SMTC works by broadcasting the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle2007-10-111-0/+7
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Switch from to_tm to rtc_time_to_tmRalf Baechle2007-10-111-0/+1
| | | | | | | | | This replaces the MIPS-specific to_tm function with the generic rtc_time_to_tm function. The big difference between the two functions is that rtc_time_to_tm uses epoch 70 while to_tm uses 1970, so the result of rtc_time_to_tm needs to be fixed up. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use generic NTP code for all MIPS platformsRalf Baechle2007-10-111-0/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add CFE support to BCM47XXAurelien Jarno2007-10-111-0/+2
| | | | | | | | | Add CFE support to the BCM47XX code. That includes querying CFE environment variables as well as using CFE to print messages before the serial port is initialized (early printk). Signed-off-by: Aurelien Jarno <aurel32@farad.aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Move CFE code into arch/mips/fw/cfeAurelien Jarno2007-10-111-0/+3
| | | | | | | | Move the platform independent part of the CFE code to arch/mips/fw/cfe from arch/mips/sibyte/cfe. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add GT641xx IRQ routines.Yoichi Yuasa2007-10-111-0/+4
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PCI: Always enable CONFIG_PCI_DOMAINSRalf Baechle2007-10-111-3/+1
| | | | | | The cost is just too low. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add support for BCM47XX CPUs.Aurelien Jarno2007-10-111-0/+14
| | | | | | | | | | | | | | Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] JAZZ fixesThomas Bogendoerfer2007-10-111-0/+1
| | | | | | | | | | - restructured irq handling - switched vdma to use memory allocated via get_free_pages - setup platform devices for serial, jazz_esp and jazzsonic - fixed cmos rtc access Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add back support for LASAT platformsBrian Murphy2007-10-111-0/+18
| | | | | Signed-off-by: Brian Murphy <brian@murphy.dk> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Automatically set CONFIG_BUILD_ELF64Franck Bui-Huu2007-10-111-15/+0
| | | | | | | | | | | | | We do not rely on user anymore to setup this config correctly. Instead we make our choice depending on the load address. If we want to force Kbuild to use ELF64 format whatever the load address we can still do: $ make BUILD_ELF32=no Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IRQ Affinity Support for SMTC on Malta PlatformKevin D. Kissell2007-10-111-0/+13
| | | | | Signed-off-by: Kevin D. Kissell <kevink@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Ocelot: remove remaining bitsYoichi Yuasa2007-09-101-14/+0
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Kconfig: whitespace cleanup.Ralf Baechle2007-09-101-4/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fulong doesn't need ISA DMA.Ralf Baechle2007-08-271-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sort out handling of ISA-less PCI systems.Ralf Baechle2007-08-271-5/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Excite: disable 64-bit kernel support.Ralf Baechle2007-08-271-1/+0
| | | | | | | CC arch/mips/basler/excite/excite_prom.o arch/mips/basler/excite/excite_prom.c:136:3: #error 64 bit support not implemented Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Kconfig: Fix configuration warning by hardwiring HOTPLUG_CPU to n.Ralf Baechle2007-08-271-0/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SEAD: Don't mark as experimental.Ralf Baechle2007-08-271-2/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Drop unneeded config options for RBTX4938Atsushi Nemoto2007-08-271-2/+0
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup TX39/TX49 irq codeAtsushi Nemoto2007-08-271-2/+6
| | | | | | | | Cleanup jmr3927, tx4927 and tx4938 irq codes, using common IRQ_CPU, I8259 and IRQ_TXX9 irq routines. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] The irq_chip for TX39/TX49 SoCsAtsushi Nemoto2007-08-271-0/+3
| | | | | | | | Add generic irq_chip for TX39/TX49 SoCs. This can be replace jmr3927_irq_irc, tx4927_irq_pic_type and tx4938_irq_pic_type. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove unused pnx8550 KconfigYoichi Yuasa2007-08-271-1/+0
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Kconfig: Enable 64BIT_PHYS_ADDR only through select.Ralf Baechle2007-08-271-2/+1
| | | | | | The user should not have to have any clue about this setting. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] DDB5477: Remove supportYoichi Yuasa2007-07-311-25/+0
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove Momentum Ocelot support.Ralf Baechle2007-07-311-18/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Enable coexistence of AP/SP with VSMP and SMTC.Ralf Baechle2007-07-311-12/+12
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sort system types alphabeticallyYoichi Yuasa2007-07-311-100/+100
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix RBTX49x7 board nameYoichi Yuasa2007-07-311-1/+1
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fixup secure computing stuff.Ralf Baechle2007-07-311-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make support for weakly ordered LL/SC a config option.Ralf Baechle2007-07-201-0/+11
| | | | | | | None of weakly ordered processor supported in tree need this but it seems like this could change ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Rename PC speaker codeRalf Baechle2007-07-121-4/+4
| | | | | | | | While the PC speaker is wired up to the i8254 there is more to the i8254 than just the PC speaker so this code was getting in the way under its current name. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Interrupt mask backstop hackKevin D. Kissell2007-07-121-0/+13
| | | | | | | | | | | To support multiple TC microthreads acting as "CPUs" within a VPE, VPE-wide interrupt mask bits must be specially manipulated during interrupt handling. To support legacy drivers and interrupt controller management code, SMTC has a "backstop" to track and if necessary restore the interrupt mask. This has some performance impact on interrupt service overhead. Disable it only if you know what you are doing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Delete Ocelot 3 support.Ralf Baechle2007-07-101-25/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] remove LASAT Networks platforms supportYoichi Yuasa2007-07-101-18/+0
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] rbtx4938: Add generic GPIO supportAtsushi Nemoto2007-07-101-0/+1
| | | | | | | | GPIO 0..15 are for TX4938 PIO pins, GPIO 16..18 are for FPGA-driven chipselect signals for SPI devices. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SNI RM updatesThomas Bogendoerfer2007-07-101-2/+2
| | | | | | | | | | | | - use RTC_CLASS instead of GEN_RTC - get rid of ds1216 in favour of a RTC_CLASS driver - use correct console device for older RM400 - use physical addresses for 82596 device - use 128 byte L1 cache line size (this is needed because most of the SNI caches are using 128 L2 cache lines) Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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