| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define | Ke Wei | 2008-06-22 | 1 | -3/+3 |
| | | | | | | | | | | | | | Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> | ||||
| * | plat-orion: share time handling code | Lennert Buytenhek | 2008-03-27 | 1 | -0/+203 |
| Split off Orion time handling code into plat-orion/. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com> | |||||
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