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* mxc/iomux: add GPIO bank offset for iomux v3 platformsJason Wang2010-07-261-0/+15
| | | | | | | | | | These GPIO bank offsets are useful when define a gpio number. E.G. when GPIO PORTC pin 6 is used for irq request pin of external expanding device, we can define it like: #define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6) Signed-off-by: Jason Wang <jason77.wang@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mxc: Core support for Freescale i.MX5 seriesAmit Kucheria2010-02-091-3/+5
| | | | | | | Add basic clock support, cpu identification, I/O mapping, interrupt controller, serial port and ethernet. Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
* mxc: iomux v3: remove resource handlingSascha Hauer2009-11-241-16/+1
| | | | | | | The current model does not allow to put a pad into different modes once a pins is allocated. Remove the resource handling. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* iomux-v3: Allow for a runtime base addressSascha Hauer2009-08-141-0/+5
| | | | | | | also, check for a valid pad_ctrl_ofs before changing the pad control register. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXC iomux-v3: Fix defines for PAD_CTL registersSascha Hauer2009-08-071-17/+13
| | | | | | | The old defines leaked in from an old version of the patch. Change the defines to match the register layout of the iomuxer. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXC: Add iomux support for MX35 SoCsSascha Hauer2009-05-071-0/+121
This iomux is called iomux-v3 in the tree because it is the third known incarnation of MXC iomuxers. It is not only found on the MX35 but also on the MX51 and probably others. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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